stm32f4/stm32f413/exti/
emr.rs

1///Register `EMR` reader
2pub type R = crate::R<EMRrs>;
3///Register `EMR` writer
4pub type W = crate::W<EMRrs>;
5/**Event Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EVENT_MASK {
11    ///0: Event request line is masked
12    Masked = 0,
13    ///1: Event request line is unmasked
14    Unmasked = 1,
15}
16impl From<EVENT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: EVENT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR(0-22)` reader - Event Mask on line %s
23pub type MR_R = crate::BitReader<EVENT_MASK>;
24impl MR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EVENT_MASK {
28        match self.bits {
29            false => EVENT_MASK::Masked,
30            true => EVENT_MASK::Unmasked,
31        }
32    }
33    ///Event request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == EVENT_MASK::Masked
37    }
38    ///Event request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == EVENT_MASK::Unmasked
42    }
43}
44///Field `MR(0-22)` writer - Event Mask on line %s
45pub type MR_W<'a, REG> = crate::BitWriter<'a, REG, EVENT_MASK>;
46impl<'a, REG> MR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Event request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(EVENT_MASK::Masked)
54    }
55    ///Event request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(EVENT_MASK::Unmasked)
59    }
60}
61impl R {
62    ///Event Mask on line (0-22)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
65    #[inline(always)]
66    pub fn mr(&self, n: u8) -> MR_R {
67        #[allow(clippy::no_effect)]
68        [(); 23][n as usize];
69        MR_R::new(((self.bits >> n) & 1) != 0)
70    }
71    ///Iterator for array of:
72    ///Event Mask on line (0-22)
73    #[inline(always)]
74    pub fn mr_iter(&self) -> impl Iterator<Item = MR_R> + '_ {
75        (0..23).map(move |n| MR_R::new(((self.bits >> n) & 1) != 0))
76    }
77    ///Bit 0 - Event Mask on line 0
78    #[inline(always)]
79    pub fn mr0(&self) -> MR_R {
80        MR_R::new((self.bits & 1) != 0)
81    }
82    ///Bit 1 - Event Mask on line 1
83    #[inline(always)]
84    pub fn mr1(&self) -> MR_R {
85        MR_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    ///Bit 2 - Event Mask on line 2
88    #[inline(always)]
89    pub fn mr2(&self) -> MR_R {
90        MR_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    ///Bit 3 - Event Mask on line 3
93    #[inline(always)]
94    pub fn mr3(&self) -> MR_R {
95        MR_R::new(((self.bits >> 3) & 1) != 0)
96    }
97    ///Bit 4 - Event Mask on line 4
98    #[inline(always)]
99    pub fn mr4(&self) -> MR_R {
100        MR_R::new(((self.bits >> 4) & 1) != 0)
101    }
102    ///Bit 5 - Event Mask on line 5
103    #[inline(always)]
104    pub fn mr5(&self) -> MR_R {
105        MR_R::new(((self.bits >> 5) & 1) != 0)
106    }
107    ///Bit 6 - Event Mask on line 6
108    #[inline(always)]
109    pub fn mr6(&self) -> MR_R {
110        MR_R::new(((self.bits >> 6) & 1) != 0)
111    }
112    ///Bit 7 - Event Mask on line 7
113    #[inline(always)]
114    pub fn mr7(&self) -> MR_R {
115        MR_R::new(((self.bits >> 7) & 1) != 0)
116    }
117    ///Bit 8 - Event Mask on line 8
118    #[inline(always)]
119    pub fn mr8(&self) -> MR_R {
120        MR_R::new(((self.bits >> 8) & 1) != 0)
121    }
122    ///Bit 9 - Event Mask on line 9
123    #[inline(always)]
124    pub fn mr9(&self) -> MR_R {
125        MR_R::new(((self.bits >> 9) & 1) != 0)
126    }
127    ///Bit 10 - Event Mask on line 10
128    #[inline(always)]
129    pub fn mr10(&self) -> MR_R {
130        MR_R::new(((self.bits >> 10) & 1) != 0)
131    }
132    ///Bit 11 - Event Mask on line 11
133    #[inline(always)]
134    pub fn mr11(&self) -> MR_R {
135        MR_R::new(((self.bits >> 11) & 1) != 0)
136    }
137    ///Bit 12 - Event Mask on line 12
138    #[inline(always)]
139    pub fn mr12(&self) -> MR_R {
140        MR_R::new(((self.bits >> 12) & 1) != 0)
141    }
142    ///Bit 13 - Event Mask on line 13
143    #[inline(always)]
144    pub fn mr13(&self) -> MR_R {
145        MR_R::new(((self.bits >> 13) & 1) != 0)
146    }
147    ///Bit 14 - Event Mask on line 14
148    #[inline(always)]
149    pub fn mr14(&self) -> MR_R {
150        MR_R::new(((self.bits >> 14) & 1) != 0)
151    }
152    ///Bit 15 - Event Mask on line 15
153    #[inline(always)]
154    pub fn mr15(&self) -> MR_R {
155        MR_R::new(((self.bits >> 15) & 1) != 0)
156    }
157    ///Bit 16 - Event Mask on line 16
158    #[inline(always)]
159    pub fn mr16(&self) -> MR_R {
160        MR_R::new(((self.bits >> 16) & 1) != 0)
161    }
162    ///Bit 17 - Event Mask on line 17
163    #[inline(always)]
164    pub fn mr17(&self) -> MR_R {
165        MR_R::new(((self.bits >> 17) & 1) != 0)
166    }
167    ///Bit 18 - Event Mask on line 18
168    #[inline(always)]
169    pub fn mr18(&self) -> MR_R {
170        MR_R::new(((self.bits >> 18) & 1) != 0)
171    }
172    ///Bit 19 - Event Mask on line 19
173    #[inline(always)]
174    pub fn mr19(&self) -> MR_R {
175        MR_R::new(((self.bits >> 19) & 1) != 0)
176    }
177    ///Bit 20 - Event Mask on line 20
178    #[inline(always)]
179    pub fn mr20(&self) -> MR_R {
180        MR_R::new(((self.bits >> 20) & 1) != 0)
181    }
182    ///Bit 21 - Event Mask on line 21
183    #[inline(always)]
184    pub fn mr21(&self) -> MR_R {
185        MR_R::new(((self.bits >> 21) & 1) != 0)
186    }
187    ///Bit 22 - Event Mask on line 22
188    #[inline(always)]
189    pub fn mr22(&self) -> MR_R {
190        MR_R::new(((self.bits >> 22) & 1) != 0)
191    }
192}
193impl core::fmt::Debug for R {
194    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
195        f.debug_struct("EMR")
196            .field("mr0", &self.mr0())
197            .field("mr1", &self.mr1())
198            .field("mr2", &self.mr2())
199            .field("mr3", &self.mr3())
200            .field("mr4", &self.mr4())
201            .field("mr5", &self.mr5())
202            .field("mr6", &self.mr6())
203            .field("mr7", &self.mr7())
204            .field("mr8", &self.mr8())
205            .field("mr9", &self.mr9())
206            .field("mr10", &self.mr10())
207            .field("mr11", &self.mr11())
208            .field("mr12", &self.mr12())
209            .field("mr13", &self.mr13())
210            .field("mr14", &self.mr14())
211            .field("mr15", &self.mr15())
212            .field("mr16", &self.mr16())
213            .field("mr17", &self.mr17())
214            .field("mr18", &self.mr18())
215            .field("mr19", &self.mr19())
216            .field("mr20", &self.mr20())
217            .field("mr21", &self.mr21())
218            .field("mr22", &self.mr22())
219            .finish()
220    }
221}
222impl W {
223    ///Event Mask on line (0-22)
224    ///
225    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
226    #[inline(always)]
227    pub fn mr(&mut self, n: u8) -> MR_W<EMRrs> {
228        #[allow(clippy::no_effect)]
229        [(); 23][n as usize];
230        MR_W::new(self, n)
231    }
232    ///Bit 0 - Event Mask on line 0
233    #[inline(always)]
234    pub fn mr0(&mut self) -> MR_W<EMRrs> {
235        MR_W::new(self, 0)
236    }
237    ///Bit 1 - Event Mask on line 1
238    #[inline(always)]
239    pub fn mr1(&mut self) -> MR_W<EMRrs> {
240        MR_W::new(self, 1)
241    }
242    ///Bit 2 - Event Mask on line 2
243    #[inline(always)]
244    pub fn mr2(&mut self) -> MR_W<EMRrs> {
245        MR_W::new(self, 2)
246    }
247    ///Bit 3 - Event Mask on line 3
248    #[inline(always)]
249    pub fn mr3(&mut self) -> MR_W<EMRrs> {
250        MR_W::new(self, 3)
251    }
252    ///Bit 4 - Event Mask on line 4
253    #[inline(always)]
254    pub fn mr4(&mut self) -> MR_W<EMRrs> {
255        MR_W::new(self, 4)
256    }
257    ///Bit 5 - Event Mask on line 5
258    #[inline(always)]
259    pub fn mr5(&mut self) -> MR_W<EMRrs> {
260        MR_W::new(self, 5)
261    }
262    ///Bit 6 - Event Mask on line 6
263    #[inline(always)]
264    pub fn mr6(&mut self) -> MR_W<EMRrs> {
265        MR_W::new(self, 6)
266    }
267    ///Bit 7 - Event Mask on line 7
268    #[inline(always)]
269    pub fn mr7(&mut self) -> MR_W<EMRrs> {
270        MR_W::new(self, 7)
271    }
272    ///Bit 8 - Event Mask on line 8
273    #[inline(always)]
274    pub fn mr8(&mut self) -> MR_W<EMRrs> {
275        MR_W::new(self, 8)
276    }
277    ///Bit 9 - Event Mask on line 9
278    #[inline(always)]
279    pub fn mr9(&mut self) -> MR_W<EMRrs> {
280        MR_W::new(self, 9)
281    }
282    ///Bit 10 - Event Mask on line 10
283    #[inline(always)]
284    pub fn mr10(&mut self) -> MR_W<EMRrs> {
285        MR_W::new(self, 10)
286    }
287    ///Bit 11 - Event Mask on line 11
288    #[inline(always)]
289    pub fn mr11(&mut self) -> MR_W<EMRrs> {
290        MR_W::new(self, 11)
291    }
292    ///Bit 12 - Event Mask on line 12
293    #[inline(always)]
294    pub fn mr12(&mut self) -> MR_W<EMRrs> {
295        MR_W::new(self, 12)
296    }
297    ///Bit 13 - Event Mask on line 13
298    #[inline(always)]
299    pub fn mr13(&mut self) -> MR_W<EMRrs> {
300        MR_W::new(self, 13)
301    }
302    ///Bit 14 - Event Mask on line 14
303    #[inline(always)]
304    pub fn mr14(&mut self) -> MR_W<EMRrs> {
305        MR_W::new(self, 14)
306    }
307    ///Bit 15 - Event Mask on line 15
308    #[inline(always)]
309    pub fn mr15(&mut self) -> MR_W<EMRrs> {
310        MR_W::new(self, 15)
311    }
312    ///Bit 16 - Event Mask on line 16
313    #[inline(always)]
314    pub fn mr16(&mut self) -> MR_W<EMRrs> {
315        MR_W::new(self, 16)
316    }
317    ///Bit 17 - Event Mask on line 17
318    #[inline(always)]
319    pub fn mr17(&mut self) -> MR_W<EMRrs> {
320        MR_W::new(self, 17)
321    }
322    ///Bit 18 - Event Mask on line 18
323    #[inline(always)]
324    pub fn mr18(&mut self) -> MR_W<EMRrs> {
325        MR_W::new(self, 18)
326    }
327    ///Bit 19 - Event Mask on line 19
328    #[inline(always)]
329    pub fn mr19(&mut self) -> MR_W<EMRrs> {
330        MR_W::new(self, 19)
331    }
332    ///Bit 20 - Event Mask on line 20
333    #[inline(always)]
334    pub fn mr20(&mut self) -> MR_W<EMRrs> {
335        MR_W::new(self, 20)
336    }
337    ///Bit 21 - Event Mask on line 21
338    #[inline(always)]
339    pub fn mr21(&mut self) -> MR_W<EMRrs> {
340        MR_W::new(self, 21)
341    }
342    ///Bit 22 - Event Mask on line 22
343    #[inline(always)]
344    pub fn mr22(&mut self) -> MR_W<EMRrs> {
345        MR_W::new(self, 22)
346    }
347}
348/**Event mask register (EXTI_EMR)
349
350You can [`read`](crate::Reg::read) this register and get [`emr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
351
352See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#EXTI:EMR)*/
353pub struct EMRrs;
354impl crate::RegisterSpec for EMRrs {
355    type Ux = u32;
356}
357///`read()` method returns [`emr::R`](R) reader structure
358impl crate::Readable for EMRrs {}
359///`write(|w| ..)` method takes [`emr::W`](W) writer structure
360impl crate::Writable for EMRrs {
361    type Safety = crate::Unsafe;
362}
363///`reset()` method sets EMR to value 0
364impl crate::Resettable for EMRrs {}
stm32f4/stm32f413/exti/emr.rs

stm32f4/stm32f413/exti/
emr.rs
