stm32f4/stm32f401/tim1/
ccmr1_input.rs

1///Register `CCMR1_Input` reader
2pub type R = crate::R<CCMR1_INPUTrs>;
3///Register `CCMR1_Input` writer
4pub type W = crate::W<CCMR1_INPUTrs>;
5/**Capture/Compare 1 selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC1S {
12    ///1: CC1 channel is configured as input, IC1 is mapped on TI1
13    Ti1 = 1,
14    ///2: CC1 channel is configured as input, IC1 is mapped on TI2
15    Ti2 = 2,
16    ///3: CC1 channel is configured as input, IC1 is mapped on TRC
17    Trc = 3,
18}
19impl From<CC1S> for u8 {
20    #[inline(always)]
21    fn from(variant: CC1S) -> Self {
22        variant as _
23    }
24}
25impl crate::FieldSpec for CC1S {
26    type Ux = u8;
27}
28impl crate::IsEnum for CC1S {}
29///Field `CC1S` reader - Capture/Compare 1 selection
30pub type CC1S_R = crate::FieldReader<CC1S>;
31impl CC1S_R {
32    ///Get enumerated values variant
33    #[inline(always)]
34    pub const fn variant(&self) -> Option<CC1S> {
35        match self.bits {
36            1 => Some(CC1S::Ti1),
37            2 => Some(CC1S::Ti2),
38            3 => Some(CC1S::Trc),
39            _ => None,
40        }
41    }
42    ///CC1 channel is configured as input, IC1 is mapped on TI1
43    #[inline(always)]
44    pub fn is_ti1(&self) -> bool {
45        *self == CC1S::Ti1
46    }
47    ///CC1 channel is configured as input, IC1 is mapped on TI2
48    #[inline(always)]
49    pub fn is_ti2(&self) -> bool {
50        *self == CC1S::Ti2
51    }
52    ///CC1 channel is configured as input, IC1 is mapped on TRC
53    #[inline(always)]
54    pub fn is_trc(&self) -> bool {
55        *self == CC1S::Trc
56    }
57}
58///Field `CC1S` writer - Capture/Compare 1 selection
59pub type CC1S_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC1S>;
60impl<'a, REG> CC1S_W<'a, REG>
61where
62    REG: crate::Writable + crate::RegisterSpec,
63    REG::Ux: From<u8>,
64{
65    ///CC1 channel is configured as input, IC1 is mapped on TI1
66    #[inline(always)]
67    pub fn ti1(self) -> &'a mut crate::W<REG> {
68        self.variant(CC1S::Ti1)
69    }
70    ///CC1 channel is configured as input, IC1 is mapped on TI2
71    #[inline(always)]
72    pub fn ti2(self) -> &'a mut crate::W<REG> {
73        self.variant(CC1S::Ti2)
74    }
75    ///CC1 channel is configured as input, IC1 is mapped on TRC
76    #[inline(always)]
77    pub fn trc(self) -> &'a mut crate::W<REG> {
78        self.variant(CC1S::Trc)
79    }
80}
81/**Input capture %s prescaler
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86#[repr(u8)]
87pub enum ICPRESCALER {
88    ///0: No prescaler, capture is done each time an edge is detected on the capture input
89    NoPrescaler = 0,
90    ///1: Capture is done once every 2 events
91    TwoEvents = 1,
92    ///2: Capture is done once every 4 events
93    FourEvents = 2,
94    ///3: Capture is done once every 8 events
95    EightEvents = 3,
96}
97impl From<ICPRESCALER> for u8 {
98    #[inline(always)]
99    fn from(variant: ICPRESCALER) -> Self {
100        variant as _
101    }
102}
103impl crate::FieldSpec for ICPRESCALER {
104    type Ux = u8;
105}
106impl crate::IsEnum for ICPRESCALER {}
107///Field `ICPSC(1-2)` reader - Input capture %s prescaler
108pub type ICPSC_R = crate::FieldReader<ICPRESCALER>;
109impl ICPSC_R {
110    ///Get enumerated values variant
111    #[inline(always)]
112    pub const fn variant(&self) -> ICPRESCALER {
113        match self.bits {
114            0 => ICPRESCALER::NoPrescaler,
115            1 => ICPRESCALER::TwoEvents,
116            2 => ICPRESCALER::FourEvents,
117            3 => ICPRESCALER::EightEvents,
118            _ => unreachable!(),
119        }
120    }
121    ///No prescaler, capture is done each time an edge is detected on the capture input
122    #[inline(always)]
123    pub fn is_no_prescaler(&self) -> bool {
124        *self == ICPRESCALER::NoPrescaler
125    }
126    ///Capture is done once every 2 events
127    #[inline(always)]
128    pub fn is_two_events(&self) -> bool {
129        *self == ICPRESCALER::TwoEvents
130    }
131    ///Capture is done once every 4 events
132    #[inline(always)]
133    pub fn is_four_events(&self) -> bool {
134        *self == ICPRESCALER::FourEvents
135    }
136    ///Capture is done once every 8 events
137    #[inline(always)]
138    pub fn is_eight_events(&self) -> bool {
139        *self == ICPRESCALER::EightEvents
140    }
141}
142///Field `ICPSC(1-2)` writer - Input capture %s prescaler
143pub type ICPSC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, ICPRESCALER, crate::Safe>;
144impl<'a, REG> ICPSC_W<'a, REG>
145where
146    REG: crate::Writable + crate::RegisterSpec,
147    REG::Ux: From<u8>,
148{
149    ///No prescaler, capture is done each time an edge is detected on the capture input
150    #[inline(always)]
151    pub fn no_prescaler(self) -> &'a mut crate::W<REG> {
152        self.variant(ICPRESCALER::NoPrescaler)
153    }
154    ///Capture is done once every 2 events
155    #[inline(always)]
156    pub fn two_events(self) -> &'a mut crate::W<REG> {
157        self.variant(ICPRESCALER::TwoEvents)
158    }
159    ///Capture is done once every 4 events
160    #[inline(always)]
161    pub fn four_events(self) -> &'a mut crate::W<REG> {
162        self.variant(ICPRESCALER::FourEvents)
163    }
164    ///Capture is done once every 8 events
165    #[inline(always)]
166    pub fn eight_events(self) -> &'a mut crate::W<REG> {
167        self.variant(ICPRESCALER::EightEvents)
168    }
169}
170/**Input capture %s filter
171
172Value on reset: 0*/
173#[cfg_attr(feature = "defmt", derive(defmt::Format))]
174#[derive(Clone, Copy, Debug, PartialEq, Eq)]
175#[repr(u8)]
176pub enum ICFILTER {
177    ///0: No filter, sampling is done at fDTS
178    NoFilter = 0,
179    ///1: fSAMPLING=fCK_INT, N=2
180    FckIntN2 = 1,
181    ///2: fSAMPLING=fCK_INT, N=4
182    FckIntN4 = 2,
183    ///3: fSAMPLING=fCK_INT, N=8
184    FckIntN8 = 3,
185    ///4: fSAMPLING=fDTS/2, N=6
186    FdtsDiv2N6 = 4,
187    ///5: fSAMPLING=fDTS/2, N=8
188    FdtsDiv2N8 = 5,
189    ///6: fSAMPLING=fDTS/4, N=6
190    FdtsDiv4N6 = 6,
191    ///7: fSAMPLING=fDTS/4, N=8
192    FdtsDiv4N8 = 7,
193    ///8: fSAMPLING=fDTS/8, N=6
194    FdtsDiv8N6 = 8,
195    ///9: fSAMPLING=fDTS/8, N=8
196    FdtsDiv8N8 = 9,
197    ///10: fSAMPLING=fDTS/16, N=5
198    FdtsDiv16N5 = 10,
199    ///11: fSAMPLING=fDTS/16, N=6
200    FdtsDiv16N6 = 11,
201    ///12: fSAMPLING=fDTS/16, N=8
202    FdtsDiv16N8 = 12,
203    ///13: fSAMPLING=fDTS/32, N=5
204    FdtsDiv32N5 = 13,
205    ///14: fSAMPLING=fDTS/32, N=6
206    FdtsDiv32N6 = 14,
207    ///15: fSAMPLING=fDTS/32, N=8
208    FdtsDiv32N8 = 15,
209}
210impl From<ICFILTER> for u8 {
211    #[inline(always)]
212    fn from(variant: ICFILTER) -> Self {
213        variant as _
214    }
215}
216impl crate::FieldSpec for ICFILTER {
217    type Ux = u8;
218}
219impl crate::IsEnum for ICFILTER {}
220///Field `ICF(1-2)` reader - Input capture %s filter
221pub type ICF_R = crate::FieldReader<ICFILTER>;
222impl ICF_R {
223    ///Get enumerated values variant
224    #[inline(always)]
225    pub const fn variant(&self) -> ICFILTER {
226        match self.bits {
227            0 => ICFILTER::NoFilter,
228            1 => ICFILTER::FckIntN2,
229            2 => ICFILTER::FckIntN4,
230            3 => ICFILTER::FckIntN8,
231            4 => ICFILTER::FdtsDiv2N6,
232            5 => ICFILTER::FdtsDiv2N8,
233            6 => ICFILTER::FdtsDiv4N6,
234            7 => ICFILTER::FdtsDiv4N8,
235            8 => ICFILTER::FdtsDiv8N6,
236            9 => ICFILTER::FdtsDiv8N8,
237            10 => ICFILTER::FdtsDiv16N5,
238            11 => ICFILTER::FdtsDiv16N6,
239            12 => ICFILTER::FdtsDiv16N8,
240            13 => ICFILTER::FdtsDiv32N5,
241            14 => ICFILTER::FdtsDiv32N6,
242            15 => ICFILTER::FdtsDiv32N8,
243            _ => unreachable!(),
244        }
245    }
246    ///No filter, sampling is done at fDTS
247    #[inline(always)]
248    pub fn is_no_filter(&self) -> bool {
249        *self == ICFILTER::NoFilter
250    }
251    ///fSAMPLING=fCK_INT, N=2
252    #[inline(always)]
253    pub fn is_fck_int_n2(&self) -> bool {
254        *self == ICFILTER::FckIntN2
255    }
256    ///fSAMPLING=fCK_INT, N=4
257    #[inline(always)]
258    pub fn is_fck_int_n4(&self) -> bool {
259        *self == ICFILTER::FckIntN4
260    }
261    ///fSAMPLING=fCK_INT, N=8
262    #[inline(always)]
263    pub fn is_fck_int_n8(&self) -> bool {
264        *self == ICFILTER::FckIntN8
265    }
266    ///fSAMPLING=fDTS/2, N=6
267    #[inline(always)]
268    pub fn is_fdts_div2_n6(&self) -> bool {
269        *self == ICFILTER::FdtsDiv2N6
270    }
271    ///fSAMPLING=fDTS/2, N=8
272    #[inline(always)]
273    pub fn is_fdts_div2_n8(&self) -> bool {
274        *self == ICFILTER::FdtsDiv2N8
275    }
276    ///fSAMPLING=fDTS/4, N=6
277    #[inline(always)]
278    pub fn is_fdts_div4_n6(&self) -> bool {
279        *self == ICFILTER::FdtsDiv4N6
280    }
281    ///fSAMPLING=fDTS/4, N=8
282    #[inline(always)]
283    pub fn is_fdts_div4_n8(&self) -> bool {
284        *self == ICFILTER::FdtsDiv4N8
285    }
286    ///fSAMPLING=fDTS/8, N=6
287    #[inline(always)]
288    pub fn is_fdts_div8_n6(&self) -> bool {
289        *self == ICFILTER::FdtsDiv8N6
290    }
291    ///fSAMPLING=fDTS/8, N=8
292    #[inline(always)]
293    pub fn is_fdts_div8_n8(&self) -> bool {
294        *self == ICFILTER::FdtsDiv8N8
295    }
296    ///fSAMPLING=fDTS/16, N=5
297    #[inline(always)]
298    pub fn is_fdts_div16_n5(&self) -> bool {
299        *self == ICFILTER::FdtsDiv16N5
300    }
301    ///fSAMPLING=fDTS/16, N=6
302    #[inline(always)]
303    pub fn is_fdts_div16_n6(&self) -> bool {
304        *self == ICFILTER::FdtsDiv16N6
305    }
306    ///fSAMPLING=fDTS/16, N=8
307    #[inline(always)]
308    pub fn is_fdts_div16_n8(&self) -> bool {
309        *self == ICFILTER::FdtsDiv16N8
310    }
311    ///fSAMPLING=fDTS/32, N=5
312    #[inline(always)]
313    pub fn is_fdts_div32_n5(&self) -> bool {
314        *self == ICFILTER::FdtsDiv32N5
315    }
316    ///fSAMPLING=fDTS/32, N=6
317    #[inline(always)]
318    pub fn is_fdts_div32_n6(&self) -> bool {
319        *self == ICFILTER::FdtsDiv32N6
320    }
321    ///fSAMPLING=fDTS/32, N=8
322    #[inline(always)]
323    pub fn is_fdts_div32_n8(&self) -> bool {
324        *self == ICFILTER::FdtsDiv32N8
325    }
326}
327///Field `ICF(1-2)` writer - Input capture %s filter
328pub type ICF_W<'a, REG> = crate::FieldWriter<'a, REG, 4, ICFILTER, crate::Safe>;
329impl<'a, REG> ICF_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332    REG::Ux: From<u8>,
333{
334    ///No filter, sampling is done at fDTS
335    #[inline(always)]
336    pub fn no_filter(self) -> &'a mut crate::W<REG> {
337        self.variant(ICFILTER::NoFilter)
338    }
339    ///fSAMPLING=fCK_INT, N=2
340    #[inline(always)]
341    pub fn fck_int_n2(self) -> &'a mut crate::W<REG> {
342        self.variant(ICFILTER::FckIntN2)
343    }
344    ///fSAMPLING=fCK_INT, N=4
345    #[inline(always)]
346    pub fn fck_int_n4(self) -> &'a mut crate::W<REG> {
347        self.variant(ICFILTER::FckIntN4)
348    }
349    ///fSAMPLING=fCK_INT, N=8
350    #[inline(always)]
351    pub fn fck_int_n8(self) -> &'a mut crate::W<REG> {
352        self.variant(ICFILTER::FckIntN8)
353    }
354    ///fSAMPLING=fDTS/2, N=6
355    #[inline(always)]
356    pub fn fdts_div2_n6(self) -> &'a mut crate::W<REG> {
357        self.variant(ICFILTER::FdtsDiv2N6)
358    }
359    ///fSAMPLING=fDTS/2, N=8
360    #[inline(always)]
361    pub fn fdts_div2_n8(self) -> &'a mut crate::W<REG> {
362        self.variant(ICFILTER::FdtsDiv2N8)
363    }
364    ///fSAMPLING=fDTS/4, N=6
365    #[inline(always)]
366    pub fn fdts_div4_n6(self) -> &'a mut crate::W<REG> {
367        self.variant(ICFILTER::FdtsDiv4N6)
368    }
369    ///fSAMPLING=fDTS/4, N=8
370    #[inline(always)]
371    pub fn fdts_div4_n8(self) -> &'a mut crate::W<REG> {
372        self.variant(ICFILTER::FdtsDiv4N8)
373    }
374    ///fSAMPLING=fDTS/8, N=6
375    #[inline(always)]
376    pub fn fdts_div8_n6(self) -> &'a mut crate::W<REG> {
377        self.variant(ICFILTER::FdtsDiv8N6)
378    }
379    ///fSAMPLING=fDTS/8, N=8
380    #[inline(always)]
381    pub fn fdts_div8_n8(self) -> &'a mut crate::W<REG> {
382        self.variant(ICFILTER::FdtsDiv8N8)
383    }
384    ///fSAMPLING=fDTS/16, N=5
385    #[inline(always)]
386    pub fn fdts_div16_n5(self) -> &'a mut crate::W<REG> {
387        self.variant(ICFILTER::FdtsDiv16N5)
388    }
389    ///fSAMPLING=fDTS/16, N=6
390    #[inline(always)]
391    pub fn fdts_div16_n6(self) -> &'a mut crate::W<REG> {
392        self.variant(ICFILTER::FdtsDiv16N6)
393    }
394    ///fSAMPLING=fDTS/16, N=8
395    #[inline(always)]
396    pub fn fdts_div16_n8(self) -> &'a mut crate::W<REG> {
397        self.variant(ICFILTER::FdtsDiv16N8)
398    }
399    ///fSAMPLING=fDTS/32, N=5
400    #[inline(always)]
401    pub fn fdts_div32_n5(self) -> &'a mut crate::W<REG> {
402        self.variant(ICFILTER::FdtsDiv32N5)
403    }
404    ///fSAMPLING=fDTS/32, N=6
405    #[inline(always)]
406    pub fn fdts_div32_n6(self) -> &'a mut crate::W<REG> {
407        self.variant(ICFILTER::FdtsDiv32N6)
408    }
409    ///fSAMPLING=fDTS/32, N=8
410    #[inline(always)]
411    pub fn fdts_div32_n8(self) -> &'a mut crate::W<REG> {
412        self.variant(ICFILTER::FdtsDiv32N8)
413    }
414}
415/**Capture/Compare 2 selection
416
417Value on reset: 0*/
418#[cfg_attr(feature = "defmt", derive(defmt::Format))]
419#[derive(Clone, Copy, Debug, PartialEq, Eq)]
420#[repr(u8)]
421pub enum CC2S {
422    ///1: CC2 channel is configured as input, IC2 is mapped on TI2
423    Ti2 = 1,
424    ///2: CC2 channel is configured as input, IC2 is mapped on TI1
425    Ti1 = 2,
426    ///3: CC2 channel is configured as input, IC2 is mapped on TRC
427    Trc = 3,
428}
429impl From<CC2S> for u8 {
430    #[inline(always)]
431    fn from(variant: CC2S) -> Self {
432        variant as _
433    }
434}
435impl crate::FieldSpec for CC2S {
436    type Ux = u8;
437}
438impl crate::IsEnum for CC2S {}
439///Field `CC2S` reader - Capture/Compare 2 selection
440pub type CC2S_R = crate::FieldReader<CC2S>;
441impl CC2S_R {
442    ///Get enumerated values variant
443    #[inline(always)]
444    pub const fn variant(&self) -> Option<CC2S> {
445        match self.bits {
446            1 => Some(CC2S::Ti2),
447            2 => Some(CC2S::Ti1),
448            3 => Some(CC2S::Trc),
449            _ => None,
450        }
451    }
452    ///CC2 channel is configured as input, IC2 is mapped on TI2
453    #[inline(always)]
454    pub fn is_ti2(&self) -> bool {
455        *self == CC2S::Ti2
456    }
457    ///CC2 channel is configured as input, IC2 is mapped on TI1
458    #[inline(always)]
459    pub fn is_ti1(&self) -> bool {
460        *self == CC2S::Ti1
461    }
462    ///CC2 channel is configured as input, IC2 is mapped on TRC
463    #[inline(always)]
464    pub fn is_trc(&self) -> bool {
465        *self == CC2S::Trc
466    }
467}
468///Field `CC2S` writer - Capture/Compare 2 selection
469pub type CC2S_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC2S>;
470impl<'a, REG> CC2S_W<'a, REG>
471where
472    REG: crate::Writable + crate::RegisterSpec,
473    REG::Ux: From<u8>,
474{
475    ///CC2 channel is configured as input, IC2 is mapped on TI2
476    #[inline(always)]
477    pub fn ti2(self) -> &'a mut crate::W<REG> {
478        self.variant(CC2S::Ti2)
479    }
480    ///CC2 channel is configured as input, IC2 is mapped on TI1
481    #[inline(always)]
482    pub fn ti1(self) -> &'a mut crate::W<REG> {
483        self.variant(CC2S::Ti1)
484    }
485    ///CC2 channel is configured as input, IC2 is mapped on TRC
486    #[inline(always)]
487    pub fn trc(self) -> &'a mut crate::W<REG> {
488        self.variant(CC2S::Trc)
489    }
490}
491impl R {
492    ///Bits 0:1 - Capture/Compare 1 selection
493    #[inline(always)]
494    pub fn cc1s(&self) -> CC1S_R {
495        CC1S_R::new((self.bits & 3) as u8)
496    }
497    ///Input capture (1-2) prescaler
498    ///
499    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1PSC` field.</div>
500    #[inline(always)]
501    pub fn icpsc(&self, n: u8) -> ICPSC_R {
502        #[allow(clippy::no_effect)]
503        [(); 2][n as usize];
504        ICPSC_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8)
505    }
506    ///Iterator for array of:
507    ///Input capture (1-2) prescaler
508    #[inline(always)]
509    pub fn icpsc_iter(&self) -> impl Iterator<Item = ICPSC_R> + '_ {
510        (0..2).map(move |n| ICPSC_R::new(((self.bits >> (n * 8 + 2)) & 3) as u8))
511    }
512    ///Bits 2:3 - Input capture 1 prescaler
513    #[inline(always)]
514    pub fn ic1psc(&self) -> ICPSC_R {
515        ICPSC_R::new(((self.bits >> 2) & 3) as u8)
516    }
517    ///Bits 10:11 - Input capture 2 prescaler
518    #[inline(always)]
519    pub fn ic2psc(&self) -> ICPSC_R {
520        ICPSC_R::new(((self.bits >> 10) & 3) as u8)
521    }
522    ///Input capture (1-2) filter
523    ///
524    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1F` field.</div>
525    #[inline(always)]
526    pub fn icf(&self, n: u8) -> ICF_R {
527        #[allow(clippy::no_effect)]
528        [(); 2][n as usize];
529        ICF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8)
530    }
531    ///Iterator for array of:
532    ///Input capture (1-2) filter
533    #[inline(always)]
534    pub fn icf_iter(&self) -> impl Iterator<Item = ICF_R> + '_ {
535        (0..2).map(move |n| ICF_R::new(((self.bits >> (n * 8 + 4)) & 0x0f) as u8))
536    }
537    ///Bits 4:7 - Input capture 1 filter
538    #[inline(always)]
539    pub fn ic1f(&self) -> ICF_R {
540        ICF_R::new(((self.bits >> 4) & 0x0f) as u8)
541    }
542    ///Bits 12:15 - Input capture 2 filter
543    #[inline(always)]
544    pub fn ic2f(&self) -> ICF_R {
545        ICF_R::new(((self.bits >> 12) & 0x0f) as u8)
546    }
547    ///Bits 8:9 - Capture/Compare 2 selection
548    #[inline(always)]
549    pub fn cc2s(&self) -> CC2S_R {
550        CC2S_R::new(((self.bits >> 8) & 3) as u8)
551    }
552}
553impl core::fmt::Debug for R {
554    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
555        f.debug_struct("CCMR1_Input")
556            .field("ic1f", &self.ic1f())
557            .field("ic2f", &self.ic2f())
558            .field("ic1psc", &self.ic1psc())
559            .field("ic2psc", &self.ic2psc())
560            .field("cc2s", &self.cc2s())
561            .field("cc1s", &self.cc1s())
562            .finish()
563    }
564}
565impl W {
566    ///Bits 0:1 - Capture/Compare 1 selection
567    #[inline(always)]
568    pub fn cc1s(&mut self) -> CC1S_W<CCMR1_INPUTrs> {
569        CC1S_W::new(self, 0)
570    }
571    ///Input capture (1-2) prescaler
572    ///
573    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1PSC` field.</div>
574    #[inline(always)]
575    pub fn icpsc(&mut self, n: u8) -> ICPSC_W<CCMR1_INPUTrs> {
576        #[allow(clippy::no_effect)]
577        [(); 2][n as usize];
578        ICPSC_W::new(self, n * 8 + 2)
579    }
580    ///Bits 2:3 - Input capture 1 prescaler
581    #[inline(always)]
582    pub fn ic1psc(&mut self) -> ICPSC_W<CCMR1_INPUTrs> {
583        ICPSC_W::new(self, 2)
584    }
585    ///Bits 10:11 - Input capture 2 prescaler
586    #[inline(always)]
587    pub fn ic2psc(&mut self) -> ICPSC_W<CCMR1_INPUTrs> {
588        ICPSC_W::new(self, 10)
589    }
590    ///Input capture (1-2) filter
591    ///
592    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `IC1F` field.</div>
593    #[inline(always)]
594    pub fn icf(&mut self, n: u8) -> ICF_W<CCMR1_INPUTrs> {
595        #[allow(clippy::no_effect)]
596        [(); 2][n as usize];
597        ICF_W::new(self, n * 8 + 4)
598    }
599    ///Bits 4:7 - Input capture 1 filter
600    #[inline(always)]
601    pub fn ic1f(&mut self) -> ICF_W<CCMR1_INPUTrs> {
602        ICF_W::new(self, 4)
603    }
604    ///Bits 12:15 - Input capture 2 filter
605    #[inline(always)]
606    pub fn ic2f(&mut self) -> ICF_W<CCMR1_INPUTrs> {
607        ICF_W::new(self, 12)
608    }
609    ///Bits 8:9 - Capture/Compare 2 selection
610    #[inline(always)]
611    pub fn cc2s(&mut self) -> CC2S_W<CCMR1_INPUTrs> {
612        CC2S_W::new(self, 8)
613    }
614}
615/**capture/compare mode register 1 (input mode)
616
617You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
618
619See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM1:CCMR1_Input)*/
620pub struct CCMR1_INPUTrs;
621impl crate::RegisterSpec for CCMR1_INPUTrs {
622    type Ux = u32;
623}
624///`read()` method returns [`ccmr1_input::R`](R) reader structure
625impl crate::Readable for CCMR1_INPUTrs {}
626///`write(|w| ..)` method takes [`ccmr1_input::W`](W) writer structure
627impl crate::Writable for CCMR1_INPUTrs {
628    type Safety = crate::Unsafe;
629}
630///`reset()` method sets CCMR1_Input to value 0
631impl crate::Resettable for CCMR1_INPUTrs {}
stm32f4/stm32f401/tim1/ccmr1_input.rs

stm32f4/stm32f401/tim1/
ccmr1_input.rs
