#[doc = r"Value read from the register"]
pub struct R {
    bits: u32,
}
#[doc = r"Value to write to the register"]
pub struct W {
    bits: u32,
}
impl super::BTR {
    #[doc = r"Modifies the contents of the register"]
    #[inline(always)]
    pub fn modify<F>(&self, f: F)
    where
        for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W,
    {
        let bits = self.register.get();
        self.register.set(f(&R { bits }, &mut W { bits }).bits);
    }
    #[doc = r"Reads the contents of the register"]
    #[inline(always)]
    pub fn read(&self) -> R {
        R {
            bits: self.register.get(),
        }
    }
    #[doc = r"Writes to the register"]
    #[inline(always)]
    pub fn write<F>(&self, f: F)
    where
        F: FnOnce(&mut W) -> &mut W,
    {
        self.register.set(
            f(&mut W {
                bits: Self::reset_value(),
            })
            .bits,
        );
    }
    #[doc = r"Reset value of the register"]
    #[inline(always)]
    pub const fn reset_value() -> u32 {
        0
    }
    #[doc = r"Writes the reset value to the register"]
    #[inline(always)]
    pub fn reset(&self) {
        self.register.set(Self::reset_value())
    }
}
#[doc = "Possible values of the field `ACCMOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACCMODR {
    #[doc = "Access mode A"]
    A,
    #[doc = "Access mode B"]
    B,
    #[doc = "Access mode C"]
    C,
    #[doc = "Access mode D"]
    D,
}
impl ACCMODR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        match *self {
            ACCMODR::A => 0,
            ACCMODR::B => 0x01,
            ACCMODR::C => 0x02,
            ACCMODR::D => 0x03,
        }
    }
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _from(value: u8) -> ACCMODR {
        match value {
            0 => ACCMODR::A,
            1 => ACCMODR::B,
            2 => ACCMODR::C,
            3 => ACCMODR::D,
            _ => unreachable!(),
        }
    }
    #[doc = "Checks if the value of the field is `A`"]
    #[inline(always)]
    pub fn is_a(&self) -> bool {
        *self == ACCMODR::A
    }
    #[doc = "Checks if the value of the field is `B`"]
    #[inline(always)]
    pub fn is_b(&self) -> bool {
        *self == ACCMODR::B
    }
    #[doc = "Checks if the value of the field is `C`"]
    #[inline(always)]
    pub fn is_c(&self) -> bool {
        *self == ACCMODR::C
    }
    #[doc = "Checks if the value of the field is `D`"]
    #[inline(always)]
    pub fn is_d(&self) -> bool {
        *self == ACCMODR::D
    }
}
#[doc = "Values that can be written to the field `ACCMOD`"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum ACCMODW {
    #[doc = "Access mode A"]
    A,
    #[doc = "Access mode B"]
    B,
    #[doc = "Access mode C"]
    C,
    #[doc = "Access mode D"]
    D,
}
impl ACCMODW {
    #[allow(missing_docs)]
    #[doc(hidden)]
    #[inline(always)]
    pub fn _bits(&self) -> u8 {
        match *self {
            ACCMODW::A => 0,
            ACCMODW::B => 1,
            ACCMODW::C => 2,
            ACCMODW::D => 3,
        }
    }
}
#[doc = r"Proxy"]
pub struct _ACCMODW<'a> {
    w: &'a mut W,
}
impl<'a> _ACCMODW<'a> {
    #[doc = r"Writes `variant` to the field"]
    #[inline(always)]
    pub fn variant(self, variant: ACCMODW) -> &'a mut W {
        {
            self.bits(variant._bits())
        }
    }
    #[doc = "Access mode A"]
    #[inline(always)]
    pub fn a(self) -> &'a mut W {
        self.variant(ACCMODW::A)
    }
    #[doc = "Access mode B"]
    #[inline(always)]
    pub fn b(self) -> &'a mut W {
        self.variant(ACCMODW::B)
    }
    #[doc = "Access mode C"]
    #[inline(always)]
    pub fn c(self) -> &'a mut W {
        self.variant(ACCMODW::C)
    }
    #[doc = "Access mode D"]
    #[inline(always)]
    pub fn d(self) -> &'a mut W {
        self.variant(ACCMODW::D)
    }
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x03 << 28);
        self.w.bits |= ((value as u32) & 0x03) << 28;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct BUSTURNR {
    bits: u8,
}
impl BUSTURNR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _BUSTURNW<'a> {
    w: &'a mut W,
}
impl<'a> _BUSTURNW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 16);
        self.w.bits |= ((value as u32) & 0x0f) << 16;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct DATASTR {
    bits: u8,
}
impl DATASTR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _DATASTW<'a> {
    w: &'a mut W,
}
impl<'a> _DATASTW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0xff << 8);
        self.w.bits |= ((value as u32) & 0xff) << 8;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct ADDHLDR {
    bits: u8,
}
impl ADDHLDR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _ADDHLDW<'a> {
    w: &'a mut W,
}
impl<'a> _ADDHLDW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 4);
        self.w.bits |= ((value as u32) & 0x0f) << 4;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct ADDSETR {
    bits: u8,
}
impl ADDSETR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _ADDSETW<'a> {
    w: &'a mut W,
}
impl<'a> _ADDSETW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 0);
        self.w.bits |= ((value as u32) & 0x0f) << 0;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct CLKDIVR {
    bits: u8,
}
impl CLKDIVR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _CLKDIVW<'a> {
    w: &'a mut W,
}
impl<'a> _CLKDIVW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 20);
        self.w.bits |= ((value as u32) & 0x0f) << 20;
        self.w
    }
}
#[doc = r"Value of the field"]
pub struct DATLATR {
    bits: u8,
}
impl DATLATR {
    #[doc = r"Value of the field as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u8 {
        self.bits
    }
}
#[doc = r"Proxy"]
pub struct _DATLATW<'a> {
    w: &'a mut W,
}
impl<'a> _DATLATW<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bits(self, value: u8) -> &'a mut W {
        self.w.bits &= !(0x0f << 24);
        self.w.bits |= ((value as u32) & 0x0f) << 24;
        self.w
    }
}
impl R {
    #[doc = r"Value of the register as raw bits"]
    #[inline(always)]
    pub fn bits(&self) -> u32 {
        self.bits
    }
    #[doc = "Bits 28:29 - Access mode"]
    #[inline(always)]
    pub fn accmod(&self) -> ACCMODR {
        ACCMODR::_from(((self.bits >> 28) & 0x03) as u8)
    }
    #[doc = "Bits 16:19 - Bus turnaround phase duration"]
    #[inline(always)]
    pub fn busturn(&self) -> BUSTURNR {
        let bits = ((self.bits >> 16) & 0x0f) as u8;
        BUSTURNR { bits }
    }
    #[doc = "Bits 8:15 - Data-phase duration"]
    #[inline(always)]
    pub fn datast(&self) -> DATASTR {
        let bits = ((self.bits >> 8) & 0xff) as u8;
        DATASTR { bits }
    }
    #[doc = "Bits 4:7 - Address-hold phase duration"]
    #[inline(always)]
    pub fn addhld(&self) -> ADDHLDR {
        let bits = ((self.bits >> 4) & 0x0f) as u8;
        ADDHLDR { bits }
    }
    #[doc = "Bits 0:3 - Address setup phase duration"]
    #[inline(always)]
    pub fn addset(&self) -> ADDSETR {
        let bits = ((self.bits >> 0) & 0x0f) as u8;
        ADDSETR { bits }
    }
    #[doc = "Bits 20:23 - Clock divide ratio"]
    #[inline(always)]
    pub fn clkdiv(&self) -> CLKDIVR {
        let bits = ((self.bits >> 20) & 0x0f) as u8;
        CLKDIVR { bits }
    }
    #[doc = "Bits 24:27 - Data latency"]
    #[inline(always)]
    pub fn datlat(&self) -> DATLATR {
        let bits = ((self.bits >> 24) & 0x0f) as u8;
        DATLATR { bits }
    }
}
impl W {
    #[doc = r"Writes raw bits to the register"]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.bits = bits;
        self
    }
    #[doc = "Bits 28:29 - Access mode"]
    #[inline(always)]
    pub fn accmod(&mut self) -> _ACCMODW {
        _ACCMODW { w: self }
    }
    #[doc = "Bits 16:19 - Bus turnaround phase duration"]
    #[inline(always)]
    pub fn busturn(&mut self) -> _BUSTURNW {
        _BUSTURNW { w: self }
    }
    #[doc = "Bits 8:15 - Data-phase duration"]
    #[inline(always)]
    pub fn datast(&mut self) -> _DATASTW {
        _DATASTW { w: self }
    }
    #[doc = "Bits 4:7 - Address-hold phase duration"]
    #[inline(always)]
    pub fn addhld(&mut self) -> _ADDHLDW {
        _ADDHLDW { w: self }
    }
    #[doc = "Bits 0:3 - Address setup phase duration"]
    #[inline(always)]
    pub fn addset(&mut self) -> _ADDSETW {
        _ADDSETW { w: self }
    }
    #[doc = "Bits 20:23 - Clock divide ratio"]
    #[inline(always)]
    pub fn clkdiv(&mut self) -> _CLKDIVW {
        _CLKDIVW { w: self }
    }
    #[doc = "Bits 24:27 - Data latency"]
    #[inline(always)]
    pub fn datlat(&mut self) -> _DATLATW {
        _DATLATW { w: self }
    }
}