stm32f4/stm32f469/rcc/
ahb3enr.rs

1///Register `AHB3ENR` reader
2pub type R = crate::R<AHB3ENRrs>;
3///Register `AHB3ENR` writer
4pub type W = crate::W<AHB3ENRrs>;
5/**Flexible memory controller module clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum FMCEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<FMCEN> for bool {
17    #[inline(always)]
18    fn from(variant: FMCEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `FMCEN` reader - Flexible memory controller module clock enable
23pub type FMCEN_R = crate::BitReader<FMCEN>;
24impl FMCEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> FMCEN {
28        match self.bits {
29            false => FMCEN::Disabled,
30            true => FMCEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == FMCEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == FMCEN::Enabled
42    }
43}
44///Field `FMCEN` writer - Flexible memory controller module clock enable
45pub type FMCEN_W<'a, REG> = crate::BitWriter<'a, REG, FMCEN>;
46impl<'a, REG> FMCEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(FMCEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(FMCEN::Enabled)
59    }
60}
61///Field `QSPIEN` reader - QUADSPI memory controller module clock enable
62pub use FMCEN_R as QSPIEN_R;
63///Field `QSPIEN` writer - QUADSPI memory controller module clock enable
64pub use FMCEN_W as QSPIEN_W;
65impl R {
66    ///Bit 0 - Flexible memory controller module clock enable
67    #[inline(always)]
68    pub fn fmcen(&self) -> FMCEN_R {
69        FMCEN_R::new((self.bits & 1) != 0)
70    }
71    ///Bit 1 - QUADSPI memory controller module clock enable
72    #[inline(always)]
73    pub fn qspien(&self) -> QSPIEN_R {
74        QSPIEN_R::new(((self.bits >> 1) & 1) != 0)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("AHB3ENR")
80            .field("fmcen", &self.fmcen())
81            .field("qspien", &self.qspien())
82            .finish()
83    }
84}
85impl W {
86    ///Bit 0 - Flexible memory controller module clock enable
87    #[inline(always)]
88    pub fn fmcen(&mut self) -> FMCEN_W<AHB3ENRrs> {
89        FMCEN_W::new(self, 0)
90    }
91    ///Bit 1 - QUADSPI memory controller module clock enable
92    #[inline(always)]
93    pub fn qspien(&mut self) -> QSPIEN_W<AHB3ENRrs> {
94        QSPIEN_W::new(self, 1)
95    }
96}
97/**AHB3 peripheral clock enable register
98
99You can [`read`](crate::Reg::read) this register and get [`ahb3enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ahb3enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#RCC:AHB3ENR)*/
102pub struct AHB3ENRrs;
103impl crate::RegisterSpec for AHB3ENRrs {
104    type Ux = u32;
105}
106///`read()` method returns [`ahb3enr::R`](R) reader structure
107impl crate::Readable for AHB3ENRrs {}
108///`write(|w| ..)` method takes [`ahb3enr::W`](W) writer structure
109impl crate::Writable for AHB3ENRrs {
110    type Safety = crate::Unsafe;
111}
112///`reset()` method sets AHB3ENR to value 0
113impl crate::Resettable for AHB3ENRrs {}
stm32f4/stm32f469/rcc/ahb3enr.rs

stm32f4/stm32f469/rcc/
ahb3enr.rs
