stm32f4/stm32f407/cryp/
misr.rs

1///Register `MISR` reader
2pub type R = crate::R<MISRrs>;
3///Field `INMIS` reader - Input FIFO service masked interrupt status
4pub type INMIS_R = crate::BitReader;
5///Field `OUTMIS` reader - Output FIFO service masked interrupt status
6pub type OUTMIS_R = crate::BitReader;
7impl R {
8    ///Bit 0 - Input FIFO service masked interrupt status
9    #[inline(always)]
10    pub fn inmis(&self) -> INMIS_R {
11        INMIS_R::new((self.bits & 1) != 0)
12    }
13    ///Bit 1 - Output FIFO service masked interrupt status
14    #[inline(always)]
15    pub fn outmis(&self) -> OUTMIS_R {
16        OUTMIS_R::new(((self.bits >> 1) & 1) != 0)
17    }
18}
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("MISR")
22            .field("outmis", &self.outmis())
23            .field("inmis", &self.inmis())
24            .finish()
25    }
26}
27/**masked interrupt status register
28
29You can [`read`](crate::Reg::read) this register and get [`misr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
30
31See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#CRYP:MISR)*/
32pub struct MISRrs;
33impl crate::RegisterSpec for MISRrs {
34    type Ux = u32;
35}
36///`read()` method returns [`misr::R`](R) reader structure
37impl crate::Readable for MISRrs {}
38///`reset()` method sets MISR to value 0
39impl crate::Resettable for MISRrs {}
stm32f4/stm32f407/cryp/misr.rs

stm32f4/stm32f407/cryp/
misr.rs
