stm32f4/stm32f407/adc1/
sqr3.rs

1///Register `SQR3` reader
2pub type R = crate::R<SQR3rs>;
3///Register `SQR3` writer
4pub type W = crate::W<SQR3rs>;
5///Field `SQ(1-6)` reader - %s conversion in regular sequence
6pub type SQ_R = crate::FieldReader;
7///Field `SQ(1-6)` writer - %s conversion in regular sequence
8pub type SQ_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9impl R {
10    ///(1-6) conversion in regular sequence
11    ///
12    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
13    #[inline(always)]
14    pub fn sq(&self, n: u8) -> SQ_R {
15        #[allow(clippy::no_effect)]
16        [(); 6][n as usize];
17        SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8)
18    }
19    ///Iterator for array of:
20    ///(1-6) conversion in regular sequence
21    #[inline(always)]
22    pub fn sq_iter(&self) -> impl Iterator<Item = SQ_R> + '_ {
23        (0..6).map(move |n| SQ_R::new(((self.bits >> (n * 5)) & 0x1f) as u8))
24    }
25    ///Bits 0:4 - 1 conversion in regular sequence
26    #[inline(always)]
27    pub fn sq1(&self) -> SQ_R {
28        SQ_R::new((self.bits & 0x1f) as u8)
29    }
30    ///Bits 5:9 - 2 conversion in regular sequence
31    #[inline(always)]
32    pub fn sq2(&self) -> SQ_R {
33        SQ_R::new(((self.bits >> 5) & 0x1f) as u8)
34    }
35    ///Bits 10:14 - 3 conversion in regular sequence
36    #[inline(always)]
37    pub fn sq3(&self) -> SQ_R {
38        SQ_R::new(((self.bits >> 10) & 0x1f) as u8)
39    }
40    ///Bits 15:19 - 4 conversion in regular sequence
41    #[inline(always)]
42    pub fn sq4(&self) -> SQ_R {
43        SQ_R::new(((self.bits >> 15) & 0x1f) as u8)
44    }
45    ///Bits 20:24 - 5 conversion in regular sequence
46    #[inline(always)]
47    pub fn sq5(&self) -> SQ_R {
48        SQ_R::new(((self.bits >> 20) & 0x1f) as u8)
49    }
50    ///Bits 25:29 - 6 conversion in regular sequence
51    #[inline(always)]
52    pub fn sq6(&self) -> SQ_R {
53        SQ_R::new(((self.bits >> 25) & 0x1f) as u8)
54    }
55}
56impl core::fmt::Debug for R {
57    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
58        f.debug_struct("SQR3")
59            .field("sq1", &self.sq1())
60            .field("sq2", &self.sq2())
61            .field("sq3", &self.sq3())
62            .field("sq4", &self.sq4())
63            .field("sq5", &self.sq5())
64            .field("sq6", &self.sq6())
65            .finish()
66    }
67}
68impl W {
69    ///(1-6) conversion in regular sequence
70    ///
71    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `SQ1` field.</div>
72    #[inline(always)]
73    pub fn sq(&mut self, n: u8) -> SQ_W<SQR3rs> {
74        #[allow(clippy::no_effect)]
75        [(); 6][n as usize];
76        SQ_W::new(self, n * 5)
77    }
78    ///Bits 0:4 - 1 conversion in regular sequence
79    #[inline(always)]
80    pub fn sq1(&mut self) -> SQ_W<SQR3rs> {
81        SQ_W::new(self, 0)
82    }
83    ///Bits 5:9 - 2 conversion in regular sequence
84    #[inline(always)]
85    pub fn sq2(&mut self) -> SQ_W<SQR3rs> {
86        SQ_W::new(self, 5)
87    }
88    ///Bits 10:14 - 3 conversion in regular sequence
89    #[inline(always)]
90    pub fn sq3(&mut self) -> SQ_W<SQR3rs> {
91        SQ_W::new(self, 10)
92    }
93    ///Bits 15:19 - 4 conversion in regular sequence
94    #[inline(always)]
95    pub fn sq4(&mut self) -> SQ_W<SQR3rs> {
96        SQ_W::new(self, 15)
97    }
98    ///Bits 20:24 - 5 conversion in regular sequence
99    #[inline(always)]
100    pub fn sq5(&mut self) -> SQ_W<SQR3rs> {
101        SQ_W::new(self, 20)
102    }
103    ///Bits 25:29 - 6 conversion in regular sequence
104    #[inline(always)]
105    pub fn sq6(&mut self) -> SQ_W<SQR3rs> {
106        SQ_W::new(self, 25)
107    }
108}
109/**regular sequence register 3
110
111You can [`read`](crate::Reg::read) this register and get [`sqr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
112
113See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#ADC1:SQR3)*/
114pub struct SQR3rs;
115impl crate::RegisterSpec for SQR3rs {
116    type Ux = u32;
117}
118///`read()` method returns [`sqr3::R`](R) reader structure
119impl crate::Readable for SQR3rs {}
120///`write(|w| ..)` method takes [`sqr3::W`](W) writer structure
121impl crate::Writable for SQR3rs {
122    type Safety = crate::Unsafe;
123}
124///`reset()` method sets SQR3 to value 0
125impl crate::Resettable for SQR3rs {}
stm32f4/stm32f407/adc1/sqr3.rs

stm32f4/stm32f407/adc1/
sqr3.rs
