stm32f4/stm32f401/
mod.rs

1/*!Peripheral access API for STM32F401 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn EXTI16_PVD();
21    fn TAMP_STAMP();
22    fn EXTI22_RTC_WKUP();
23    fn FLASH();
24    fn RCC();
25    fn EXTI0();
26    fn EXTI1();
27    fn EXTI2();
28    fn EXTI3();
29    fn EXTI4();
30    fn DMA1_STREAM0();
31    fn DMA1_STREAM1();
32    fn DMA1_STREAM2();
33    fn DMA1_STREAM3();
34    fn DMA1_STREAM4();
35    fn DMA1_STREAM5();
36    fn DMA1_STREAM6();
37    fn ADC();
38    fn EXTI9_5();
39    fn TIM1_BRK_TIM9();
40    fn TIM1_UP_TIM10();
41    fn TIM1_TRG_COM_TIM11();
42    fn TIM1_CC();
43    fn TIM2();
44    fn TIM3();
45    fn TIM4();
46    fn I2C1_EV();
47    fn I2C1_ER();
48    fn I2C2_EV();
49    fn I2C2_ER();
50    fn SPI1();
51    fn SPI2();
52    fn USART1();
53    fn USART2();
54    fn EXTI15_10();
55    fn EXTI17_RTC_ALARM();
56    fn EXTI18_OTG_FS_WKUP();
57    fn DMA1_STREAM7();
58    fn SDIO();
59    fn TIM5();
60    fn SPI3();
61    fn DMA2_STREAM0();
62    fn DMA2_STREAM1();
63    fn DMA2_STREAM2();
64    fn DMA2_STREAM3();
65    fn DMA2_STREAM4();
66    fn OTG_FS();
67    fn DMA2_STREAM5();
68    fn DMA2_STREAM6();
69    fn DMA2_STREAM7();
70    fn USART6();
71    fn I2C3_EV();
72    fn I2C3_ER();
73    fn FPU();
74    fn SPI4();
75}
76#[doc(hidden)]
77#[repr(C)]
78pub union Vector {
79    _handler: unsafe extern "C" fn(),
80    _reserved: u32,
81}
82#[cfg(feature = "rt")]
83#[doc(hidden)]
84#[link_section = ".vector_table.interrupts"]
85#[no_mangle]
86pub static __INTERRUPTS: [Vector; 85] = [
87    Vector { _reserved: 0 },
88    Vector {
89        _handler: EXTI16_PVD,
90    },
91    Vector {
92        _handler: TAMP_STAMP,
93    },
94    Vector {
95        _handler: EXTI22_RTC_WKUP,
96    },
97    Vector { _handler: FLASH },
98    Vector { _handler: RCC },
99    Vector { _handler: EXTI0 },
100    Vector { _handler: EXTI1 },
101    Vector { _handler: EXTI2 },
102    Vector { _handler: EXTI3 },
103    Vector { _handler: EXTI4 },
104    Vector {
105        _handler: DMA1_STREAM0,
106    },
107    Vector {
108        _handler: DMA1_STREAM1,
109    },
110    Vector {
111        _handler: DMA1_STREAM2,
112    },
113    Vector {
114        _handler: DMA1_STREAM3,
115    },
116    Vector {
117        _handler: DMA1_STREAM4,
118    },
119    Vector {
120        _handler: DMA1_STREAM5,
121    },
122    Vector {
123        _handler: DMA1_STREAM6,
124    },
125    Vector { _handler: ADC },
126    Vector { _reserved: 0 },
127    Vector { _reserved: 0 },
128    Vector { _reserved: 0 },
129    Vector { _reserved: 0 },
130    Vector { _handler: EXTI9_5 },
131    Vector {
132        _handler: TIM1_BRK_TIM9,
133    },
134    Vector {
135        _handler: TIM1_UP_TIM10,
136    },
137    Vector {
138        _handler: TIM1_TRG_COM_TIM11,
139    },
140    Vector { _handler: TIM1_CC },
141    Vector { _handler: TIM2 },
142    Vector { _handler: TIM3 },
143    Vector { _handler: TIM4 },
144    Vector { _handler: I2C1_EV },
145    Vector { _handler: I2C1_ER },
146    Vector { _handler: I2C2_EV },
147    Vector { _handler: I2C2_ER },
148    Vector { _handler: SPI1 },
149    Vector { _handler: SPI2 },
150    Vector { _handler: USART1 },
151    Vector { _handler: USART2 },
152    Vector { _reserved: 0 },
153    Vector {
154        _handler: EXTI15_10,
155    },
156    Vector {
157        _handler: EXTI17_RTC_ALARM,
158    },
159    Vector {
160        _handler: EXTI18_OTG_FS_WKUP,
161    },
162    Vector { _reserved: 0 },
163    Vector { _reserved: 0 },
164    Vector { _reserved: 0 },
165    Vector { _reserved: 0 },
166    Vector {
167        _handler: DMA1_STREAM7,
168    },
169    Vector { _reserved: 0 },
170    Vector { _handler: SDIO },
171    Vector { _handler: TIM5 },
172    Vector { _handler: SPI3 },
173    Vector { _reserved: 0 },
174    Vector { _reserved: 0 },
175    Vector { _reserved: 0 },
176    Vector { _reserved: 0 },
177    Vector {
178        _handler: DMA2_STREAM0,
179    },
180    Vector {
181        _handler: DMA2_STREAM1,
182    },
183    Vector {
184        _handler: DMA2_STREAM2,
185    },
186    Vector {
187        _handler: DMA2_STREAM3,
188    },
189    Vector {
190        _handler: DMA2_STREAM4,
191    },
192    Vector { _reserved: 0 },
193    Vector { _reserved: 0 },
194    Vector { _reserved: 0 },
195    Vector { _reserved: 0 },
196    Vector { _reserved: 0 },
197    Vector { _reserved: 0 },
198    Vector { _handler: OTG_FS },
199    Vector {
200        _handler: DMA2_STREAM5,
201    },
202    Vector {
203        _handler: DMA2_STREAM6,
204    },
205    Vector {
206        _handler: DMA2_STREAM7,
207    },
208    Vector { _handler: USART6 },
209    Vector { _handler: I2C3_EV },
210    Vector { _handler: I2C3_ER },
211    Vector { _reserved: 0 },
212    Vector { _reserved: 0 },
213    Vector { _reserved: 0 },
214    Vector { _reserved: 0 },
215    Vector { _reserved: 0 },
216    Vector { _reserved: 0 },
217    Vector { _reserved: 0 },
218    Vector { _handler: FPU },
219    Vector { _reserved: 0 },
220    Vector { _reserved: 0 },
221    Vector { _handler: SPI4 },
222];
223///Enumeration of all the interrupts.
224#[cfg_attr(feature = "defmt", derive(defmt::Format))]
225#[derive(Copy, Clone, Debug, PartialEq, Eq)]
226#[repr(u16)]
227pub enum Interrupt {
228    ///1 - EXTI Line 16 interrupt /PVD through EXTI line detection interrupt
229    EXTI16_PVD = 1,
230    ///2 - Tamper and TimeStamp interrupts through the EXTI line
231    TAMP_STAMP = 2,
232    ///3 - EXTI Line 22 interrupt /RTC Wakeup interrupt through the EXTI line
233    EXTI22_RTC_WKUP = 3,
234    ///4 - FLASH global interrupt
235    FLASH = 4,
236    ///5 - RCC global interrupt
237    RCC = 5,
238    ///6 - EXTI Line0 interrupt
239    EXTI0 = 6,
240    ///7 - EXTI Line1 interrupt
241    EXTI1 = 7,
242    ///8 - EXTI Line2 interrupt
243    EXTI2 = 8,
244    ///9 - EXTI Line3 interrupt
245    EXTI3 = 9,
246    ///10 - EXTI Line4 interrupt
247    EXTI4 = 10,
248    ///11 - DMA1 Stream0 global interrupt
249    DMA1_STREAM0 = 11,
250    ///12 - DMA1 Stream1 global interrupt
251    DMA1_STREAM1 = 12,
252    ///13 - DMA1 Stream2 global interrupt
253    DMA1_STREAM2 = 13,
254    ///14 - DMA1 Stream3 global interrupt
255    DMA1_STREAM3 = 14,
256    ///15 - DMA1 Stream4 global interrupt
257    DMA1_STREAM4 = 15,
258    ///16 - DMA1 Stream5 global interrupt
259    DMA1_STREAM5 = 16,
260    ///17 - DMA1 Stream6 global interrupt
261    DMA1_STREAM6 = 17,
262    ///18 - ADC1 global interrupt
263    ADC = 18,
264    ///23 - EXTI Line\[9:5\] interrupts
265    EXTI9_5 = 23,
266    ///24 - TIM1 Break interrupt and TIM9 global interrupt
267    TIM1_BRK_TIM9 = 24,
268    ///25 - TIM1 Update interrupt and TIM10 global interrupt
269    TIM1_UP_TIM10 = 25,
270    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
271    TIM1_TRG_COM_TIM11 = 26,
272    ///27 - TIM1 Capture Compare interrupt
273    TIM1_CC = 27,
274    ///28 - TIM2 global interrupt
275    TIM2 = 28,
276    ///29 - TIM3 global interrupt
277    TIM3 = 29,
278    ///30 - TIM4 global interrupt
279    TIM4 = 30,
280    ///31 - I2C1 event interrupt
281    I2C1_EV = 31,
282    ///32 - I2C1 error interrupt
283    I2C1_ER = 32,
284    ///33 - I2C2 event interrupt
285    I2C2_EV = 33,
286    ///34 - I2C2 error interrupt
287    I2C2_ER = 34,
288    ///35 - SPI1 global interrupt
289    SPI1 = 35,
290    ///36 - SPI2 global interrupt
291    SPI2 = 36,
292    ///37 - USART1 global interrupt
293    USART1 = 37,
294    ///38 - USART2 global interrupt
295    USART2 = 38,
296    ///40 - EXTI Line\[15:10\] interrupts
297    EXTI15_10 = 40,
298    ///41 - EXTI Line 17 interrupt / RTC Alarms (A and B) through EXTI line interrupt
299    EXTI17_RTC_ALARM = 41,
300    ///42 - EXTI Line 18 interrupt / USBUSB On-The-Go FS Wakeup through EXTI line interrupt
301    EXTI18_OTG_FS_WKUP = 42,
302    ///47 - DMA1 Stream7 global interrupt
303    DMA1_STREAM7 = 47,
304    ///49 - SDIO global interrupt
305    SDIO = 49,
306    ///50 - TIM5 global interrupt
307    TIM5 = 50,
308    ///51 - SPI3 global interrupt
309    SPI3 = 51,
310    ///56 - DMA2 Stream0 global interrupt
311    DMA2_STREAM0 = 56,
312    ///57 - DMA2 Stream1 global interrupt
313    DMA2_STREAM1 = 57,
314    ///58 - DMA2 Stream2 global interrupt
315    DMA2_STREAM2 = 58,
316    ///59 - DMA2 Stream3 global interrupt
317    DMA2_STREAM3 = 59,
318    ///60 - DMA2 Stream4 global interrupt
319    DMA2_STREAM4 = 60,
320    ///67 - USB On The Go FS global interrupt
321    OTG_FS = 67,
322    ///68 - DMA2 Stream5 global interrupt
323    DMA2_STREAM5 = 68,
324    ///69 - DMA2 Stream6 global interrupt
325    DMA2_STREAM6 = 69,
326    ///70 - DMA2 Stream7 global interrupt
327    DMA2_STREAM7 = 70,
328    ///71 - USART6 global interrupt
329    USART6 = 71,
330    ///72 - I2C3 event interrupt
331    I2C3_EV = 72,
332    ///73 - I2C3 error interrupt
333    I2C3_ER = 73,
334    ///81 - Floating point unit interrupt
335    FPU = 81,
336    ///84 - SPI4 global interrupt
337    SPI4 = 84,
338}
339unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
340    #[inline(always)]
341    fn number(self) -> u16 {
342        self as u16
343    }
344}
345///ADC common registers
346///
347///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#ADC_Common)
348pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
349impl core::fmt::Debug for ADC_COMMON {
350    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
351        f.debug_struct("ADC_COMMON").finish()
352    }
353}
354///ADC common registers
355pub mod adc_common;
356///Analog-to-digital converter
357///
358///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#ADC1)
359pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
360impl core::fmt::Debug for ADC1 {
361    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
362        f.debug_struct("ADC1").finish()
363    }
364}
365///Analog-to-digital converter
366pub mod adc1;
367///Cryptographic processor
368///
369///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#CRC)
370pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
371impl core::fmt::Debug for CRC {
372    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
373        f.debug_struct("CRC").finish()
374    }
375}
376///Cryptographic processor
377pub mod crc;
378///Debug support
379///
380///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#DBGMCU)
381pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
382impl core::fmt::Debug for DBGMCU {
383    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
384        f.debug_struct("DBGMCU").finish()
385    }
386}
387///Debug support
388pub mod dbgmcu;
389///External interrupt/event controller
390///
391///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#EXTI)
392pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
393impl core::fmt::Debug for EXTI {
394    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
395        f.debug_struct("EXTI").finish()
396    }
397}
398///External interrupt/event controller
399pub mod exti;
400///FLASH
401///
402///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#FLASH)
403pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
404impl core::fmt::Debug for FLASH {
405    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
406        f.debug_struct("FLASH").finish()
407    }
408}
409///FLASH
410pub mod flash;
411///Independent watchdog
412///
413///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#IWDG)
414pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
415impl core::fmt::Debug for IWDG {
416    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
417        f.debug_struct("IWDG").finish()
418    }
419}
420///Independent watchdog
421pub mod iwdg;
422///USB on the go full speed
423///
424///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#OTG_FS_DEVICE)
425pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
426impl core::fmt::Debug for OTG_FS_DEVICE {
427    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
428        f.debug_struct("OTG_FS_DEVICE").finish()
429    }
430}
431///USB on the go full speed
432pub mod otg_fs_device;
433///USB on the go full speed
434///
435///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#OTG_FS_GLOBAL)
436pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
437impl core::fmt::Debug for OTG_FS_GLOBAL {
438    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
439        f.debug_struct("OTG_FS_GLOBAL").finish()
440    }
441}
442///USB on the go full speed
443pub mod otg_fs_global;
444///USB on the go full speed
445///
446///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#OTG_FS_HOST)
447pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
448impl core::fmt::Debug for OTG_FS_HOST {
449    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
450        f.debug_struct("OTG_FS_HOST").finish()
451    }
452}
453///USB on the go full speed
454pub mod otg_fs_host;
455///USB on the go full speed
456///
457///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#OTG_FS_PWRCLK)
458pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
459impl core::fmt::Debug for OTG_FS_PWRCLK {
460    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
461        f.debug_struct("OTG_FS_PWRCLK").finish()
462    }
463}
464///USB on the go full speed
465pub mod otg_fs_pwrclk;
466///Power control
467///
468///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#PWR)
469pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
470impl core::fmt::Debug for PWR {
471    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
472        f.debug_struct("PWR").finish()
473    }
474}
475///Power control
476pub mod pwr;
477///Reset and clock control
478///
479///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#RCC)
480pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
481impl core::fmt::Debug for RCC {
482    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483        f.debug_struct("RCC").finish()
484    }
485}
486///Reset and clock control
487pub mod rcc;
488///Real-time clock
489///
490///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#RTC)
491pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
492impl core::fmt::Debug for RTC {
493    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
494        f.debug_struct("RTC").finish()
495    }
496}
497///Real-time clock
498pub mod rtc;
499///Secure digital input/output interface
500///
501///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SDIO)
502pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
503impl core::fmt::Debug for SDIO {
504    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
505        f.debug_struct("SDIO").finish()
506    }
507}
508///Secure digital input/output interface
509pub mod sdio;
510///System configuration controller
511///
512///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SYSCFG)
513pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
514impl core::fmt::Debug for SYSCFG {
515    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
516        f.debug_struct("SYSCFG").finish()
517    }
518}
519///System configuration controller
520pub mod syscfg;
521///Advanced-timers
522///
523///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM1)
524pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
525impl core::fmt::Debug for TIM1 {
526    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
527        f.debug_struct("TIM1").finish()
528    }
529}
530///Advanced-timers
531pub mod tim1;
532///General-purpose-timers
533///
534///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM10)
535pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
536impl core::fmt::Debug for TIM10 {
537    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
538        f.debug_struct("TIM10").finish()
539    }
540}
541///General-purpose-timers
542pub mod tim10;
543///General-purpose-timers
544///
545///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM11)
546pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
547impl core::fmt::Debug for TIM11 {
548    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
549        f.debug_struct("TIM11").finish()
550    }
551}
552///General-purpose-timers
553pub mod tim11;
554///General purpose timers
555///
556///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM2)
557pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
558impl core::fmt::Debug for TIM2 {
559    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
560        f.debug_struct("TIM2").finish()
561    }
562}
563///General purpose timers
564pub mod tim2;
565///General purpose timers
566///
567///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM3)
568pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
569impl core::fmt::Debug for TIM3 {
570    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
571        f.debug_struct("TIM3").finish()
572    }
573}
574///General purpose timers
575pub mod tim3;
576///General purpose timers
577///
578///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM3)
579pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
580impl core::fmt::Debug for TIM4 {
581    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
582        f.debug_struct("TIM4").finish()
583    }
584}
585///General purpose timers
586pub use self::tim3 as tim4;
587///General-purpose-timers
588///
589///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM5)
590pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
591impl core::fmt::Debug for TIM5 {
592    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
593        f.debug_struct("TIM5").finish()
594    }
595}
596///General-purpose-timers
597pub mod tim5;
598///General purpose timers
599///
600///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM9)
601pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
602impl core::fmt::Debug for TIM9 {
603    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
604        f.debug_struct("TIM9").finish()
605    }
606}
607///General purpose timers
608pub mod tim9;
609///Universal synchronous asynchronous receiver transmitter
610///
611///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#USART1)
612pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
613impl core::fmt::Debug for USART1 {
614    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
615        f.debug_struct("USART1").finish()
616    }
617}
618///Universal synchronous asynchronous receiver transmitter
619pub mod usart1;
620///Universal synchronous asynchronous receiver transmitter
621///
622///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#USART1)
623pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
624impl core::fmt::Debug for USART2 {
625    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
626        f.debug_struct("USART2").finish()
627    }
628}
629///Universal synchronous asynchronous receiver transmitter
630pub use self::usart1 as usart2;
631///Universal synchronous asynchronous receiver transmitter
632///
633///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#USART1)
634pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
635impl core::fmt::Debug for USART6 {
636    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
637        f.debug_struct("USART6").finish()
638    }
639}
640///Universal synchronous asynchronous receiver transmitter
641pub use self::usart1 as usart6;
642///Window watchdog
643///
644///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#WWDG)
645pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
646impl core::fmt::Debug for WWDG {
647    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
648        f.debug_struct("WWDG").finish()
649    }
650}
651///Window watchdog
652pub mod wwdg;
653///DMA controller
654///
655///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#DMA2)
656pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
657impl core::fmt::Debug for DMA2 {
658    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
659        f.debug_struct("DMA2").finish()
660    }
661}
662///DMA controller
663pub mod dma2;
664///DMA controller
665///
666///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#DMA2)
667pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
668impl core::fmt::Debug for DMA1 {
669    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
670        f.debug_struct("DMA1").finish()
671    }
672}
673///DMA controller
674pub use self::dma2 as dma1;
675///General-purpose I/Os
676///
677///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOH)
678pub type GPIOH = crate::Periph<gpioh::RegisterBlock, 0x4002_1c00>;
679impl core::fmt::Debug for GPIOH {
680    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
681        f.debug_struct("GPIOH").finish()
682    }
683}
684///General-purpose I/Os
685pub mod gpioh;
686///General-purpose I/Os
687///
688///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOH)
689pub type GPIOE = crate::Periph<gpioh::RegisterBlock, 0x4002_1000>;
690impl core::fmt::Debug for GPIOE {
691    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
692        f.debug_struct("GPIOE").finish()
693    }
694}
695///General-purpose I/Os
696pub use self::gpioh as gpioe;
697///General-purpose I/Os
698///
699///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOH)
700pub type GPIOD = crate::Periph<gpioh::RegisterBlock, 0x4002_0c00>;
701impl core::fmt::Debug for GPIOD {
702    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
703        f.debug_struct("GPIOD").finish()
704    }
705}
706///General-purpose I/Os
707pub use self::gpioh as gpiod;
708///General-purpose I/Os
709///
710///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOH)
711pub type GPIOC = crate::Periph<gpioh::RegisterBlock, 0x4002_0800>;
712impl core::fmt::Debug for GPIOC {
713    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
714        f.debug_struct("GPIOC").finish()
715    }
716}
717///General-purpose I/Os
718pub use self::gpioh as gpioc;
719///General-purpose I/Os
720///
721///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOB)
722pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
723impl core::fmt::Debug for GPIOB {
724    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
725        f.debug_struct("GPIOB").finish()
726    }
727}
728///General-purpose I/Os
729pub mod gpiob;
730///General-purpose I/Os
731///
732///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOA)
733pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
734impl core::fmt::Debug for GPIOA {
735    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
736        f.debug_struct("GPIOA").finish()
737    }
738}
739///General-purpose I/Os
740pub mod gpioa;
741///Inter-integrated circuit
742///
743///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#I2C1)
744pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
745impl core::fmt::Debug for I2C1 {
746    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
747        f.debug_struct("I2C1").finish()
748    }
749}
750///Inter-integrated circuit
751pub mod i2c1;
752///Inter-integrated circuit
753///
754///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#I2C1)
755pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
756impl core::fmt::Debug for I2C3 {
757    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
758        f.debug_struct("I2C3").finish()
759    }
760}
761///Inter-integrated circuit
762pub use self::i2c1 as i2c3;
763///Inter-integrated circuit
764///
765///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#I2C1)
766pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
767impl core::fmt::Debug for I2C2 {
768    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
769        f.debug_struct("I2C2").finish()
770    }
771}
772///Inter-integrated circuit
773pub use self::i2c1 as i2c2;
774///Serial peripheral interface
775///
776///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
777pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
778impl core::fmt::Debug for SPI1 {
779    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
780        f.debug_struct("SPI1").finish()
781    }
782}
783///Serial peripheral interface
784pub mod spi1;
785///Serial peripheral interface
786///
787///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
788pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
789impl core::fmt::Debug for I2S2EXT {
790    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
791        f.debug_struct("I2S2EXT").finish()
792    }
793}
794///Serial peripheral interface
795pub use self::spi1 as i2s2ext;
796///Serial peripheral interface
797///
798///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
799pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
800impl core::fmt::Debug for I2S3EXT {
801    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
802        f.debug_struct("I2S3EXT").finish()
803    }
804}
805///Serial peripheral interface
806pub use self::spi1 as i2s3ext;
807///Serial peripheral interface
808///
809///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
810pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
811impl core::fmt::Debug for SPI2 {
812    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
813        f.debug_struct("SPI2").finish()
814    }
815}
816///Serial peripheral interface
817pub use self::spi1 as spi2;
818///Serial peripheral interface
819///
820///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
821pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
822impl core::fmt::Debug for SPI3 {
823    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824        f.debug_struct("SPI3").finish()
825    }
826}
827///Serial peripheral interface
828pub use self::spi1 as spi3;
829///Serial peripheral interface
830///
831///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#SPI1)
832pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
833impl core::fmt::Debug for SPI4 {
834    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
835        f.debug_struct("SPI4").finish()
836    }
837}
838///Serial peripheral interface
839pub use self::spi1 as spi4;
840#[no_mangle]
841static mut DEVICE_PERIPHERALS: bool = false;
842/// All the peripherals.
843#[allow(non_snake_case)]
844pub struct Peripherals {
845    ///ADC_Common
846    pub ADC_COMMON: ADC_COMMON,
847    ///ADC1
848    pub ADC1: ADC1,
849    ///CRC
850    pub CRC: CRC,
851    ///DBGMCU
852    pub DBGMCU: DBGMCU,
853    ///EXTI
854    pub EXTI: EXTI,
855    ///FLASH
856    pub FLASH: FLASH,
857    ///IWDG
858    pub IWDG: IWDG,
859    ///OTG_FS_DEVICE
860    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
861    ///OTG_FS_GLOBAL
862    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
863    ///OTG_FS_HOST
864    pub OTG_FS_HOST: OTG_FS_HOST,
865    ///OTG_FS_PWRCLK
866    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
867    ///PWR
868    pub PWR: PWR,
869    ///RCC
870    pub RCC: RCC,
871    ///RTC
872    pub RTC: RTC,
873    ///SDIO
874    pub SDIO: SDIO,
875    ///SYSCFG
876    pub SYSCFG: SYSCFG,
877    ///TIM1
878    pub TIM1: TIM1,
879    ///TIM10
880    pub TIM10: TIM10,
881    ///TIM11
882    pub TIM11: TIM11,
883    ///TIM2
884    pub TIM2: TIM2,
885    ///TIM3
886    pub TIM3: TIM3,
887    ///TIM4
888    pub TIM4: TIM4,
889    ///TIM5
890    pub TIM5: TIM5,
891    ///TIM9
892    pub TIM9: TIM9,
893    ///USART1
894    pub USART1: USART1,
895    ///USART2
896    pub USART2: USART2,
897    ///USART6
898    pub USART6: USART6,
899    ///WWDG
900    pub WWDG: WWDG,
901    ///DMA2
902    pub DMA2: DMA2,
903    ///DMA1
904    pub DMA1: DMA1,
905    ///GPIOH
906    pub GPIOH: GPIOH,
907    ///GPIOE
908    pub GPIOE: GPIOE,
909    ///GPIOD
910    pub GPIOD: GPIOD,
911    ///GPIOC
912    pub GPIOC: GPIOC,
913    ///GPIOB
914    pub GPIOB: GPIOB,
915    ///GPIOA
916    pub GPIOA: GPIOA,
917    ///I2C1
918    pub I2C1: I2C1,
919    ///I2C3
920    pub I2C3: I2C3,
921    ///I2C2
922    pub I2C2: I2C2,
923    ///SPI1
924    pub SPI1: SPI1,
925    ///I2S2ext
926    pub I2S2EXT: I2S2EXT,
927    ///I2S3ext
928    pub I2S3EXT: I2S3EXT,
929    ///SPI2
930    pub SPI2: SPI2,
931    ///SPI3
932    pub SPI3: SPI3,
933    ///SPI4
934    pub SPI4: SPI4,
935}
936impl Peripherals {
937    /// Returns all the peripherals *once*.
938    #[cfg(feature = "critical-section")]
939    #[inline]
940    pub fn take() -> Option<Self> {
941        critical_section::with(|_| {
942            if unsafe { DEVICE_PERIPHERALS } {
943                return None;
944            }
945            Some(unsafe { Peripherals::steal() })
946        })
947    }
948    /// Unchecked version of `Peripherals::take`.
949    ///
950    /// # Safety
951    ///
952    /// Each of the returned peripherals must be used at most once.
953    #[inline]
954    pub unsafe fn steal() -> Self {
955        DEVICE_PERIPHERALS = true;
956        Peripherals {
957            ADC_COMMON: ADC_COMMON::steal(),
958            ADC1: ADC1::steal(),
959            CRC: CRC::steal(),
960            DBGMCU: DBGMCU::steal(),
961            EXTI: EXTI::steal(),
962            FLASH: FLASH::steal(),
963            IWDG: IWDG::steal(),
964            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
965            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
966            OTG_FS_HOST: OTG_FS_HOST::steal(),
967            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
968            PWR: PWR::steal(),
969            RCC: RCC::steal(),
970            RTC: RTC::steal(),
971            SDIO: SDIO::steal(),
972            SYSCFG: SYSCFG::steal(),
973            TIM1: TIM1::steal(),
974            TIM10: TIM10::steal(),
975            TIM11: TIM11::steal(),
976            TIM2: TIM2::steal(),
977            TIM3: TIM3::steal(),
978            TIM4: TIM4::steal(),
979            TIM5: TIM5::steal(),
980            TIM9: TIM9::steal(),
981            USART1: USART1::steal(),
982            USART2: USART2::steal(),
983            USART6: USART6::steal(),
984            WWDG: WWDG::steal(),
985            DMA2: DMA2::steal(),
986            DMA1: DMA1::steal(),
987            GPIOH: GPIOH::steal(),
988            GPIOE: GPIOE::steal(),
989            GPIOD: GPIOD::steal(),
990            GPIOC: GPIOC::steal(),
991            GPIOB: GPIOB::steal(),
992            GPIOA: GPIOA::steal(),
993            I2C1: I2C1::steal(),
994            I2C3: I2C3::steal(),
995            I2C2: I2C2::steal(),
996            SPI1: SPI1::steal(),
997            I2S2EXT: I2S2EXT::steal(),
998            I2S3EXT: I2S3EXT::steal(),
999            SPI2: SPI2::steal(),
1000            SPI3: SPI3::steal(),
1001            SPI4: SPI4::steal(),
1002        }
1003    }
1004}
stm32f4/stm32f401/mod.rs

stm32f4/stm32f401/
mod.rs
