stm32f4/stm32f401/sdio/
clkcr.rs

1#[doc = "Register `CLKCR` reader"]
2pub struct R(crate::R<CLKCR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLKCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLKCR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLKCR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CLKCR` writer"]
17pub struct W(crate::W<CLKCR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLKCR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLKCR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLKCR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "HW Flow Control enable\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum HWFC_EN_A {
40    #[doc = "0: HW Flow Control is disabled"]
41    Disabled = 0,
42    #[doc = "1: HW Flow Control is enabled"]
43    Enabled = 1,
44}
45impl From<HWFC_EN_A> for bool {
46    #[inline(always)]
47    fn from(variant: HWFC_EN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `HWFC_EN` reader - HW Flow Control enable"]
52pub type HWFC_EN_R = crate::BitReader<HWFC_EN_A>;
53impl HWFC_EN_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> HWFC_EN_A {
57        match self.bits {
58            false => HWFC_EN_A::Disabled,
59            true => HWFC_EN_A::Enabled,
60        }
61    }
62    #[doc = "Checks if the value of the field is `Disabled`"]
63    #[inline(always)]
64    pub fn is_disabled(&self) -> bool {
65        *self == HWFC_EN_A::Disabled
66    }
67    #[doc = "Checks if the value of the field is `Enabled`"]
68    #[inline(always)]
69    pub fn is_enabled(&self) -> bool {
70        *self == HWFC_EN_A::Enabled
71    }
72}
73#[doc = "Field `HWFC_EN` writer - HW Flow Control enable"]
74pub type HWFC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCR_SPEC, HWFC_EN_A, O>;
75impl<'a, const O: u8> HWFC_EN_W<'a, O> {
76    #[doc = "HW Flow Control is disabled"]
77    #[inline(always)]
78    pub fn disabled(self) -> &'a mut W {
79        self.variant(HWFC_EN_A::Disabled)
80    }
81    #[doc = "HW Flow Control is enabled"]
82    #[inline(always)]
83    pub fn enabled(self) -> &'a mut W {
84        self.variant(HWFC_EN_A::Enabled)
85    }
86}
87#[doc = "SDIO_CK dephasing selection bit\n\nValue on reset: 0"]
88#[derive(Clone, Copy, Debug, PartialEq)]
89pub enum NEGEDGE_A {
90    #[doc = "0: SDIO_CK generated on the rising edge"]
91    Rising = 0,
92    #[doc = "1: SDIO_CK generated on the falling edge"]
93    Falling = 1,
94}
95impl From<NEGEDGE_A> for bool {
96    #[inline(always)]
97    fn from(variant: NEGEDGE_A) -> Self {
98        variant as u8 != 0
99    }
100}
101#[doc = "Field `NEGEDGE` reader - SDIO_CK dephasing selection bit"]
102pub type NEGEDGE_R = crate::BitReader<NEGEDGE_A>;
103impl NEGEDGE_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> NEGEDGE_A {
107        match self.bits {
108            false => NEGEDGE_A::Rising,
109            true => NEGEDGE_A::Falling,
110        }
111    }
112    #[doc = "Checks if the value of the field is `Rising`"]
113    #[inline(always)]
114    pub fn is_rising(&self) -> bool {
115        *self == NEGEDGE_A::Rising
116    }
117    #[doc = "Checks if the value of the field is `Falling`"]
118    #[inline(always)]
119    pub fn is_falling(&self) -> bool {
120        *self == NEGEDGE_A::Falling
121    }
122}
123#[doc = "Field `NEGEDGE` writer - SDIO_CK dephasing selection bit"]
124pub type NEGEDGE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCR_SPEC, NEGEDGE_A, O>;
125impl<'a, const O: u8> NEGEDGE_W<'a, O> {
126    #[doc = "SDIO_CK generated on the rising edge"]
127    #[inline(always)]
128    pub fn rising(self) -> &'a mut W {
129        self.variant(NEGEDGE_A::Rising)
130    }
131    #[doc = "SDIO_CK generated on the falling edge"]
132    #[inline(always)]
133    pub fn falling(self) -> &'a mut W {
134        self.variant(NEGEDGE_A::Falling)
135    }
136}
137#[doc = "Wide bus mode enable bit\n\nValue on reset: 0"]
138#[derive(Clone, Copy, Debug, PartialEq)]
139#[repr(u8)]
140pub enum WIDBUS_A {
141    #[doc = "0: 1 lane wide bus"]
142    BusWidth1 = 0,
143    #[doc = "1: 4 lane wide bus"]
144    BusWidth4 = 1,
145    #[doc = "2: 8 lane wide bus"]
146    BusWidth8 = 2,
147}
148impl From<WIDBUS_A> for u8 {
149    #[inline(always)]
150    fn from(variant: WIDBUS_A) -> Self {
151        variant as _
152    }
153}
154#[doc = "Field `WIDBUS` reader - Wide bus mode enable bit"]
155pub type WIDBUS_R = crate::FieldReader<u8, WIDBUS_A>;
156impl WIDBUS_R {
157    #[doc = "Get enumerated values variant"]
158    #[inline(always)]
159    pub fn variant(&self) -> Option<WIDBUS_A> {
160        match self.bits {
161            0 => Some(WIDBUS_A::BusWidth1),
162            1 => Some(WIDBUS_A::BusWidth4),
163            2 => Some(WIDBUS_A::BusWidth8),
164            _ => None,
165        }
166    }
167    #[doc = "Checks if the value of the field is `BusWidth1`"]
168    #[inline(always)]
169    pub fn is_bus_width1(&self) -> bool {
170        *self == WIDBUS_A::BusWidth1
171    }
172    #[doc = "Checks if the value of the field is `BusWidth4`"]
173    #[inline(always)]
174    pub fn is_bus_width4(&self) -> bool {
175        *self == WIDBUS_A::BusWidth4
176    }
177    #[doc = "Checks if the value of the field is `BusWidth8`"]
178    #[inline(always)]
179    pub fn is_bus_width8(&self) -> bool {
180        *self == WIDBUS_A::BusWidth8
181    }
182}
183#[doc = "Field `WIDBUS` writer - Wide bus mode enable bit"]
184pub type WIDBUS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLKCR_SPEC, u8, WIDBUS_A, 2, O>;
185impl<'a, const O: u8> WIDBUS_W<'a, O> {
186    #[doc = "1 lane wide bus"]
187    #[inline(always)]
188    pub fn bus_width1(self) -> &'a mut W {
189        self.variant(WIDBUS_A::BusWidth1)
190    }
191    #[doc = "4 lane wide bus"]
192    #[inline(always)]
193    pub fn bus_width4(self) -> &'a mut W {
194        self.variant(WIDBUS_A::BusWidth4)
195    }
196    #[doc = "8 lane wide bus"]
197    #[inline(always)]
198    pub fn bus_width8(self) -> &'a mut W {
199        self.variant(WIDBUS_A::BusWidth8)
200    }
201}
202#[doc = "Clock divider bypass enable bit\n\nValue on reset: 0"]
203#[derive(Clone, Copy, Debug, PartialEq)]
204pub enum BYPASS_A {
205    #[doc = "0: SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal."]
206    Disabled = 0,
207    #[doc = "1: SDIOCLK directly drives the SDIO_CK output signal"]
208    Enabled = 1,
209}
210impl From<BYPASS_A> for bool {
211    #[inline(always)]
212    fn from(variant: BYPASS_A) -> Self {
213        variant as u8 != 0
214    }
215}
216#[doc = "Field `BYPASS` reader - Clock divider bypass enable bit"]
217pub type BYPASS_R = crate::BitReader<BYPASS_A>;
218impl BYPASS_R {
219    #[doc = "Get enumerated values variant"]
220    #[inline(always)]
221    pub fn variant(&self) -> BYPASS_A {
222        match self.bits {
223            false => BYPASS_A::Disabled,
224            true => BYPASS_A::Enabled,
225        }
226    }
227    #[doc = "Checks if the value of the field is `Disabled`"]
228    #[inline(always)]
229    pub fn is_disabled(&self) -> bool {
230        *self == BYPASS_A::Disabled
231    }
232    #[doc = "Checks if the value of the field is `Enabled`"]
233    #[inline(always)]
234    pub fn is_enabled(&self) -> bool {
235        *self == BYPASS_A::Enabled
236    }
237}
238#[doc = "Field `BYPASS` writer - Clock divider bypass enable bit"]
239pub type BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCR_SPEC, BYPASS_A, O>;
240impl<'a, const O: u8> BYPASS_W<'a, O> {
241    #[doc = "SDIOCLK is divided according to the CLKDIV value before driving the SDIO_CK output signal."]
242    #[inline(always)]
243    pub fn disabled(self) -> &'a mut W {
244        self.variant(BYPASS_A::Disabled)
245    }
246    #[doc = "SDIOCLK directly drives the SDIO_CK output signal"]
247    #[inline(always)]
248    pub fn enabled(self) -> &'a mut W {
249        self.variant(BYPASS_A::Enabled)
250    }
251}
252#[doc = "Power saving configuration bit\n\nValue on reset: 0"]
253#[derive(Clone, Copy, Debug, PartialEq)]
254pub enum PWRSAV_A {
255    #[doc = "0: SDIO_CK clock is always enabled"]
256    Enabled = 0,
257    #[doc = "1: SDIO_CK is only enabled when the bus is active"]
258    Disabled = 1,
259}
260impl From<PWRSAV_A> for bool {
261    #[inline(always)]
262    fn from(variant: PWRSAV_A) -> Self {
263        variant as u8 != 0
264    }
265}
266#[doc = "Field `PWRSAV` reader - Power saving configuration bit"]
267pub type PWRSAV_R = crate::BitReader<PWRSAV_A>;
268impl PWRSAV_R {
269    #[doc = "Get enumerated values variant"]
270    #[inline(always)]
271    pub fn variant(&self) -> PWRSAV_A {
272        match self.bits {
273            false => PWRSAV_A::Enabled,
274            true => PWRSAV_A::Disabled,
275        }
276    }
277    #[doc = "Checks if the value of the field is `Enabled`"]
278    #[inline(always)]
279    pub fn is_enabled(&self) -> bool {
280        *self == PWRSAV_A::Enabled
281    }
282    #[doc = "Checks if the value of the field is `Disabled`"]
283    #[inline(always)]
284    pub fn is_disabled(&self) -> bool {
285        *self == PWRSAV_A::Disabled
286    }
287}
288#[doc = "Field `PWRSAV` writer - Power saving configuration bit"]
289pub type PWRSAV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCR_SPEC, PWRSAV_A, O>;
290impl<'a, const O: u8> PWRSAV_W<'a, O> {
291    #[doc = "SDIO_CK clock is always enabled"]
292    #[inline(always)]
293    pub fn enabled(self) -> &'a mut W {
294        self.variant(PWRSAV_A::Enabled)
295    }
296    #[doc = "SDIO_CK is only enabled when the bus is active"]
297    #[inline(always)]
298    pub fn disabled(self) -> &'a mut W {
299        self.variant(PWRSAV_A::Disabled)
300    }
301}
302#[doc = "Clock enable bit\n\nValue on reset: 0"]
303#[derive(Clone, Copy, Debug, PartialEq)]
304pub enum CLKEN_A {
305    #[doc = "0: Disable clock"]
306    Disabled = 0,
307    #[doc = "1: Enable clock"]
308    Enabled = 1,
309}
310impl From<CLKEN_A> for bool {
311    #[inline(always)]
312    fn from(variant: CLKEN_A) -> Self {
313        variant as u8 != 0
314    }
315}
316#[doc = "Field `CLKEN` reader - Clock enable bit"]
317pub type CLKEN_R = crate::BitReader<CLKEN_A>;
318impl CLKEN_R {
319    #[doc = "Get enumerated values variant"]
320    #[inline(always)]
321    pub fn variant(&self) -> CLKEN_A {
322        match self.bits {
323            false => CLKEN_A::Disabled,
324            true => CLKEN_A::Enabled,
325        }
326    }
327    #[doc = "Checks if the value of the field is `Disabled`"]
328    #[inline(always)]
329    pub fn is_disabled(&self) -> bool {
330        *self == CLKEN_A::Disabled
331    }
332    #[doc = "Checks if the value of the field is `Enabled`"]
333    #[inline(always)]
334    pub fn is_enabled(&self) -> bool {
335        *self == CLKEN_A::Enabled
336    }
337}
338#[doc = "Field `CLKEN` writer - Clock enable bit"]
339pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLKCR_SPEC, CLKEN_A, O>;
340impl<'a, const O: u8> CLKEN_W<'a, O> {
341    #[doc = "Disable clock"]
342    #[inline(always)]
343    pub fn disabled(self) -> &'a mut W {
344        self.variant(CLKEN_A::Disabled)
345    }
346    #[doc = "Enable clock"]
347    #[inline(always)]
348    pub fn enabled(self) -> &'a mut W {
349        self.variant(CLKEN_A::Enabled)
350    }
351}
352#[doc = "Field `CLKDIV` reader - Clock divide factor"]
353pub type CLKDIV_R = crate::FieldReader<u8, u8>;
354#[doc = "Field `CLKDIV` writer - Clock divide factor"]
355pub type CLKDIV_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u32, CLKCR_SPEC, u8, u8, 8, O>;
356impl R {
357    #[doc = "Bit 14 - HW Flow Control enable"]
358    #[inline(always)]
359    pub fn hwfc_en(&self) -> HWFC_EN_R {
360        HWFC_EN_R::new(((self.bits >> 14) & 1) != 0)
361    }
362    #[doc = "Bit 13 - SDIO_CK dephasing selection bit"]
363    #[inline(always)]
364    pub fn negedge(&self) -> NEGEDGE_R {
365        NEGEDGE_R::new(((self.bits >> 13) & 1) != 0)
366    }
367    #[doc = "Bits 11:12 - Wide bus mode enable bit"]
368    #[inline(always)]
369    pub fn widbus(&self) -> WIDBUS_R {
370        WIDBUS_R::new(((self.bits >> 11) & 3) as u8)
371    }
372    #[doc = "Bit 10 - Clock divider bypass enable bit"]
373    #[inline(always)]
374    pub fn bypass(&self) -> BYPASS_R {
375        BYPASS_R::new(((self.bits >> 10) & 1) != 0)
376    }
377    #[doc = "Bit 9 - Power saving configuration bit"]
378    #[inline(always)]
379    pub fn pwrsav(&self) -> PWRSAV_R {
380        PWRSAV_R::new(((self.bits >> 9) & 1) != 0)
381    }
382    #[doc = "Bit 8 - Clock enable bit"]
383    #[inline(always)]
384    pub fn clken(&self) -> CLKEN_R {
385        CLKEN_R::new(((self.bits >> 8) & 1) != 0)
386    }
387    #[doc = "Bits 0:7 - Clock divide factor"]
388    #[inline(always)]
389    pub fn clkdiv(&self) -> CLKDIV_R {
390        CLKDIV_R::new((self.bits & 0xff) as u8)
391    }
392}
393impl W {
394    #[doc = "Bit 14 - HW Flow Control enable"]
395    #[inline(always)]
396    pub fn hwfc_en(&mut self) -> HWFC_EN_W<14> {
397        HWFC_EN_W::new(self)
398    }
399    #[doc = "Bit 13 - SDIO_CK dephasing selection bit"]
400    #[inline(always)]
401    pub fn negedge(&mut self) -> NEGEDGE_W<13> {
402        NEGEDGE_W::new(self)
403    }
404    #[doc = "Bits 11:12 - Wide bus mode enable bit"]
405    #[inline(always)]
406    pub fn widbus(&mut self) -> WIDBUS_W<11> {
407        WIDBUS_W::new(self)
408    }
409    #[doc = "Bit 10 - Clock divider bypass enable bit"]
410    #[inline(always)]
411    pub fn bypass(&mut self) -> BYPASS_W<10> {
412        BYPASS_W::new(self)
413    }
414    #[doc = "Bit 9 - Power saving configuration bit"]
415    #[inline(always)]
416    pub fn pwrsav(&mut self) -> PWRSAV_W<9> {
417        PWRSAV_W::new(self)
418    }
419    #[doc = "Bit 8 - Clock enable bit"]
420    #[inline(always)]
421    pub fn clken(&mut self) -> CLKEN_W<8> {
422        CLKEN_W::new(self)
423    }
424    #[doc = "Bits 0:7 - Clock divide factor"]
425    #[inline(always)]
426    pub fn clkdiv(&mut self) -> CLKDIV_W<0> {
427        CLKDIV_W::new(self)
428    }
429    #[doc = "Writes raw bits to the register."]
430    #[inline(always)]
431    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
432        self.0.bits(bits);
433        self
434    }
435}
436#[doc = "SDI clock control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkcr](index.html) module"]
437pub struct CLKCR_SPEC;
438impl crate::RegisterSpec for CLKCR_SPEC {
439    type Ux = u32;
440}
441#[doc = "`read()` method returns [clkcr::R](R) reader structure"]
442impl crate::Readable for CLKCR_SPEC {
443    type Reader = R;
444}
445#[doc = "`write(|w| ..)` method takes [clkcr::W](W) writer structure"]
446impl crate::Writable for CLKCR_SPEC {
447    type Writer = W;
448}
449#[doc = "`reset()` method sets CLKCR to value 0"]
450impl crate::Resettable for CLKCR_SPEC {
451    #[inline(always)]
452    fn reset_value() -> Self::Ux {
453        0
454    }
455}
stm32f4/stm32f401/sdio/clkcr.rs

stm32f4/stm32f401/sdio/
clkcr.rs
