[−][src]Type Definition stm32f4::stm32f413::dfsdm2::flt::cr1::W
type W = W<u32, CR1>;
Writer for register CR1
Implementations
impl W
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pub fn awfsel(&mut self) -> AWFSEL_W<'_>
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Bit 30 - Analog watchdog fast mode select
pub fn fast(&mut self) -> FAST_W<'_>
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Bit 29 - Fast conversion mode selection for regular conversions
pub fn rch(&mut self) -> RCH_W<'_>
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Bits 24:26 - Regular channel selection
pub fn rdmaen(&mut self) -> RDMAEN_W<'_>
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Bit 21 - DMA channel enabled to read data for the regular conversion
pub fn rsync(&mut self) -> RSYNC_W<'_>
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Bit 19 - Launch regular conversion synchronously with DFSDM0
pub fn rcont(&mut self) -> RCONT_W<'_>
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Bit 18 - Continuous mode selection for regular conversions
pub fn rswstart(&mut self) -> RSWSTART_W<'_>
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Bit 17 - Software start of a conversion on the regular channel
pub fn jexten(&mut self) -> JEXTEN_W<'_>
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Bits 13:14 - Trigger enable and trigger edge selection for injected conversions
pub fn jextsel(&mut self) -> JEXTSEL_W<'_>
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Bits 8:10 - Trigger signal selection for launching injected conversions
pub fn jdmaen(&mut self) -> JDMAEN_W<'_>
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Bit 5 - DMA channel enabled to read data for the injected channel group
pub fn jscan(&mut self) -> JSCAN_W<'_>
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Bit 4 - Scanning conversion mode for injected conversions
pub fn jsync(&mut self) -> JSYNC_W<'_>
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Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger
pub fn jswstart(&mut self) -> JSWSTART_W<'_>
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Bit 1 - Start a conversion of the injected group of channels
pub fn dfen(&mut self) -> DFEN_W<'_>
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Bit 0 - DFSDM enable