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#[doc = "Reader of register APB1_FZ"] pub type R = crate::R<u32, super::APB1_FZ>; #[doc = "Writer for register APB1_FZ"] pub type W = crate::W<u32, super::APB1_FZ>; #[doc = "Register APB1_FZ `reset()`'s with value 0"] impl crate::ResetValue for super::APB1_FZ { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `DBG_TIM2_STOP`"] pub type DBG_TIM2_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_TIM2_STOP`"] pub struct DBG_TIM2_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_TIM2_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "Reader of field `DBG_TIM3_STOP`"] pub type DBG_TIM3_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_TIM3_STOP`"] pub struct DBG_TIM3_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_TIM3_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } #[doc = "Reader of field `DBG_TIM4_STOP`"] pub type DBG_TIM4_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_TIM4_STOP`"] pub struct DBG_TIM4_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_TIM4_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2); self.w } } #[doc = "Reader of field `DBG_TIM5_STOP`"] pub type DBG_TIM5_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_TIM5_STOP`"] pub struct DBG_TIM5_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_TIM5_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3); self.w } } #[doc = "Reader of field `DBG_RTC_Stop`"] pub type DBG_RTC_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_RTC_Stop`"] pub struct DBG_RTC_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_RTC_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Reader of field `DBG_WWDG_STOP`"] pub type DBG_WWDG_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_WWDG_STOP`"] pub struct DBG_WWDG_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_WWDG_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `DBG_IWDG_STOP`"] pub type DBG_IWDG_STOP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_IWDG_STOP`"] pub struct DBG_IWDG_STOP_W<'a> { w: &'a mut W, } impl<'a> DBG_IWDG_STOP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `DBG_I2C1_SMBUS_TIMEOUT`"] pub type DBG_I2C1_SMBUS_TIMEOUT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_I2C1_SMBUS_TIMEOUT`"] pub struct DBG_I2C1_SMBUS_TIMEOUT_W<'a> { w: &'a mut W, } impl<'a> DBG_I2C1_SMBUS_TIMEOUT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21); self.w } } #[doc = "Reader of field `DBG_I2C2_SMBUS_TIMEOUT`"] pub type DBG_I2C2_SMBUS_TIMEOUT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_I2C2_SMBUS_TIMEOUT`"] pub struct DBG_I2C2_SMBUS_TIMEOUT_W<'a> { w: &'a mut W, } impl<'a> DBG_I2C2_SMBUS_TIMEOUT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22); self.w } } #[doc = "Reader of field `DBG_I2C3SMBUS_TIMEOUT`"] pub type DBG_I2C3SMBUS_TIMEOUT_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DBG_I2C3SMBUS_TIMEOUT`"] pub struct DBG_I2C3SMBUS_TIMEOUT_W<'a> { w: &'a mut W, } impl<'a> DBG_I2C3SMBUS_TIMEOUT_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 23)) | (((value as u32) & 0x01) << 23); self.w } } impl R { #[doc = "Bit 0 - DBG_TIM2_STOP"] #[inline(always)] pub fn dbg_tim2_stop(&self) -> DBG_TIM2_STOP_R { DBG_TIM2_STOP_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - DBG_TIM3 _STOP"] #[inline(always)] pub fn dbg_tim3_stop(&self) -> DBG_TIM3_STOP_R { DBG_TIM3_STOP_R::new(((self.bits >> 1) & 0x01) != 0) } #[doc = "Bit 2 - DBG_TIM4_STOP"] #[inline(always)] pub fn dbg_tim4_stop(&self) -> DBG_TIM4_STOP_R { DBG_TIM4_STOP_R::new(((self.bits >> 2) & 0x01) != 0) } #[doc = "Bit 3 - DBG_TIM5_STOP"] #[inline(always)] pub fn dbg_tim5_stop(&self) -> DBG_TIM5_STOP_R { DBG_TIM5_STOP_R::new(((self.bits >> 3) & 0x01) != 0) } #[doc = "Bit 10 - RTC stopped when Core is halted"] #[inline(always)] pub fn dbg_rtc_stop(&self) -> DBG_RTC_STOP_R { DBG_RTC_STOP_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 11 - DBG_WWDG_STOP"] #[inline(always)] pub fn dbg_wwdg_stop(&self) -> DBG_WWDG_STOP_R { DBG_WWDG_STOP_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 12 - DBG_IWDEG_STOP"] #[inline(always)] pub fn dbg_iwdg_stop(&self) -> DBG_IWDG_STOP_R { DBG_IWDG_STOP_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c1_smbus_timeout(&self) -> DBG_I2C1_SMBUS_TIMEOUT_R { DBG_I2C1_SMBUS_TIMEOUT_R::new(((self.bits >> 21) & 0x01) != 0) } #[doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c2_smbus_timeout(&self) -> DBG_I2C2_SMBUS_TIMEOUT_R { DBG_I2C2_SMBUS_TIMEOUT_R::new(((self.bits >> 22) & 0x01) != 0) } #[doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c3smbus_timeout(&self) -> DBG_I2C3SMBUS_TIMEOUT_R { DBG_I2C3SMBUS_TIMEOUT_R::new(((self.bits >> 23) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - DBG_TIM2_STOP"] #[inline(always)] pub fn dbg_tim2_stop(&mut self) -> DBG_TIM2_STOP_W { DBG_TIM2_STOP_W { w: self } } #[doc = "Bit 1 - DBG_TIM3 _STOP"] #[inline(always)] pub fn dbg_tim3_stop(&mut self) -> DBG_TIM3_STOP_W { DBG_TIM3_STOP_W { w: self } } #[doc = "Bit 2 - DBG_TIM4_STOP"] #[inline(always)] pub fn dbg_tim4_stop(&mut self) -> DBG_TIM4_STOP_W { DBG_TIM4_STOP_W { w: self } } #[doc = "Bit 3 - DBG_TIM5_STOP"] #[inline(always)] pub fn dbg_tim5_stop(&mut self) -> DBG_TIM5_STOP_W { DBG_TIM5_STOP_W { w: self } } #[doc = "Bit 10 - RTC stopped when Core is halted"] #[inline(always)] pub fn dbg_rtc_stop(&mut self) -> DBG_RTC_STOP_W { DBG_RTC_STOP_W { w: self } } #[doc = "Bit 11 - DBG_WWDG_STOP"] #[inline(always)] pub fn dbg_wwdg_stop(&mut self) -> DBG_WWDG_STOP_W { DBG_WWDG_STOP_W { w: self } } #[doc = "Bit 12 - DBG_IWDEG_STOP"] #[inline(always)] pub fn dbg_iwdg_stop(&mut self) -> DBG_IWDG_STOP_W { DBG_IWDG_STOP_W { w: self } } #[doc = "Bit 21 - DBG_J2C1_SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c1_smbus_timeout(&mut self) -> DBG_I2C1_SMBUS_TIMEOUT_W { DBG_I2C1_SMBUS_TIMEOUT_W { w: self } } #[doc = "Bit 22 - DBG_J2C2_SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c2_smbus_timeout(&mut self) -> DBG_I2C2_SMBUS_TIMEOUT_W { DBG_I2C2_SMBUS_TIMEOUT_W { w: self } } #[doc = "Bit 23 - DBG_J2C3SMBUS_TIMEOUT"] #[inline(always)] pub fn dbg_i2c3smbus_timeout(&mut self) -> DBG_I2C3SMBUS_TIMEOUT_W { DBG_I2C3SMBUS_TIMEOUT_W { w: self } } }