#[doc = "Reader of register AHB1LPENR"]
pub type R = crate::R<u32, super::AHB1LPENR>;
#[doc = "Writer for register AHB1LPENR"]
pub type W = crate::W<u32, super::AHB1LPENR>;
#[doc = "Register AHB1LPENR `reset()`'s with value 0x7e67_91ff"]
impl crate::ResetValue for super::AHB1LPENR {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0x7e67_91ff
}
}
#[doc = "USB OTG HS ULPI clock enable during Sleep mode\n\nValue on reset: 1"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum OTGHSULPILPEN_A {
#[doc = "0: Selected module is disabled during Sleep mode"]
DISABLEDINSLEEP = 0,
#[doc = "1: Selected module is enabled during Sleep mode"]
ENABLEDINSLEEP = 1,
}
impl From<OTGHSULPILPEN_A> for bool {
#[inline(always)]
fn from(variant: OTGHSULPILPEN_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `OTGHSULPILPEN`"]
pub type OTGHSULPILPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
impl OTGHSULPILPEN_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> OTGHSULPILPEN_A {
match self.bits {
false => OTGHSULPILPEN_A::DISABLEDINSLEEP,
true => OTGHSULPILPEN_A::ENABLEDINSLEEP,
}
}
#[doc = "Checks if the value of the field is `DISABLEDINSLEEP`"]
#[inline(always)]
pub fn is_disabled_in_sleep(&self) -> bool {
*self == OTGHSULPILPEN_A::DISABLEDINSLEEP
}
#[doc = "Checks if the value of the field is `ENABLEDINSLEEP`"]
#[inline(always)]
pub fn is_enabled_in_sleep(&self) -> bool {
*self == OTGHSULPILPEN_A::ENABLEDINSLEEP
}
}
#[doc = "Write proxy for field `OTGHSULPILPEN`"]
pub struct OTGHSULPILPEN_W<'a> {
w: &'a mut W,
}
impl<'a> OTGHSULPILPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OTGHSULPILPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30);
self.w
}
}
#[doc = "USB OTG HS clock enable during Sleep mode"]
pub type OTGHSLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `OTGHSLPEN`"]
pub type OTGHSLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `OTGHSLPEN`"]
pub struct OTGHSLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> OTGHSLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: OTGHSLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29);
self.w
}
}
#[doc = "Ethernet PTP clock enable during Sleep mode"]
pub type ETHMACPTPLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `ETHMACPTPLPEN`"]
pub type ETHMACPTPLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `ETHMACPTPLPEN`"]
pub struct ETHMACPTPLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> ETHMACPTPLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ETHMACPTPLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28);
self.w
}
}
#[doc = "Ethernet reception clock enable during Sleep mode"]
pub type ETHMACRXLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `ETHMACRXLPEN`"]
pub type ETHMACRXLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `ETHMACRXLPEN`"]
pub struct ETHMACRXLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> ETHMACRXLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ETHMACRXLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 27)) | (((value as u32) & 0x01) << 27);
self.w
}
}
#[doc = "Ethernet transmission clock enable during Sleep mode"]
pub type ETHMACTXLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `ETHMACTXLPEN`"]
pub type ETHMACTXLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `ETHMACTXLPEN`"]
pub struct ETHMACTXLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> ETHMACTXLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ETHMACTXLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26);
self.w
}
}
#[doc = "Ethernet MAC clock enable during Sleep mode"]
pub type ETHMACLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `ETHMACLPEN`"]
pub type ETHMACLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `ETHMACLPEN`"]
pub struct ETHMACLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> ETHMACLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: ETHMACLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
#[doc = "DMA2 clock enable during Sleep mode"]
pub type DMA2LPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `DMA2LPEN`"]
pub type DMA2LPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `DMA2LPEN`"]
pub struct DMA2LPEN_W<'a> {
w: &'a mut W,
}
impl<'a> DMA2LPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMA2LPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 22)) | (((value as u32) & 0x01) << 22);
self.w
}
}
#[doc = "DMA1 clock enable during Sleep mode"]
pub type DMA1LPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `DMA1LPEN`"]
pub type DMA1LPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `DMA1LPEN`"]
pub struct DMA1LPEN_W<'a> {
w: &'a mut W,
}
impl<'a> DMA1LPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: DMA1LPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 21)) | (((value as u32) & 0x01) << 21);
self.w
}
}
#[doc = "Backup SRAM interface clock enable during Sleep mode"]
pub type BKPSRAMLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `BKPSRAMLPEN`"]
pub type BKPSRAMLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `BKPSRAMLPEN`"]
pub struct BKPSRAMLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> BKPSRAMLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: BKPSRAMLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 18)) | (((value as u32) & 0x01) << 18);
self.w
}
}
#[doc = "SRAM 2 interface clock enable during Sleep mode"]
pub type SRAM2LPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `SRAM2LPEN`"]
pub type SRAM2LPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `SRAM2LPEN`"]
pub struct SRAM2LPEN_W<'a> {
w: &'a mut W,
}
impl<'a> SRAM2LPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SRAM2LPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17);
self.w
}
}
#[doc = "SRAM 1interface clock enable during Sleep mode"]
pub type SRAM1LPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `SRAM1LPEN`"]
pub type SRAM1LPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `SRAM1LPEN`"]
pub struct SRAM1LPEN_W<'a> {
w: &'a mut W,
}
impl<'a> SRAM1LPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: SRAM1LPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16);
self.w
}
}
#[doc = "Flash interface clock enable during Sleep mode"]
pub type FLITFLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `FLITFLPEN`"]
pub type FLITFLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `FLITFLPEN`"]
pub struct FLITFLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> FLITFLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: FLITFLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
self.w
}
}
#[doc = "CRC clock enable during Sleep mode"]
pub type CRCLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `CRCLPEN`"]
pub type CRCLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `CRCLPEN`"]
pub struct CRCLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> CRCLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: CRCLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12);
self.w
}
}
#[doc = "IO port I clock enable during Sleep mode"]
pub type GPIOILPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOILPEN`"]
pub type GPIOILPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOILPEN`"]
pub struct GPIOILPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOILPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOILPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w
}
}
#[doc = "IO port H clock enable during Sleep mode"]
pub type GPIOHLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOHLPEN`"]
pub type GPIOHLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOHLPEN`"]
pub struct GPIOHLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOHLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOHLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7);
self.w
}
}
#[doc = "IO port G clock enable during Sleep mode"]
pub type GPIOGLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOGLPEN`"]
pub type GPIOGLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOGLPEN`"]
pub struct GPIOGLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOGLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOGLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "IO port F clock enable during Sleep mode"]
pub type GPIOFLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOFLPEN`"]
pub type GPIOFLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOFLPEN`"]
pub struct GPIOFLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOFLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOFLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
self.w
}
}
#[doc = "IO port E clock enable during Sleep mode"]
pub type GPIOELPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOELPEN`"]
pub type GPIOELPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOELPEN`"]
pub struct GPIOELPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOELPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOELPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
self.w
}
}
#[doc = "IO port D clock enable during Sleep mode"]
pub type GPIODLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIODLPEN`"]
pub type GPIODLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIODLPEN`"]
pub struct GPIODLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIODLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIODLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 3)) | (((value as u32) & 0x01) << 3);
self.w
}
}
#[doc = "IO port C clock enable during Sleep mode"]
pub type GPIOCLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOCLPEN`"]
pub type GPIOCLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOCLPEN`"]
pub struct GPIOCLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOCLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOCLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 2)) | (((value as u32) & 0x01) << 2);
self.w
}
}
#[doc = "IO port B clock enable during Sleep mode"]
pub type GPIOBLPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOBLPEN`"]
pub type GPIOBLPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOBLPEN`"]
pub struct GPIOBLPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOBLPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOBLPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1);
self.w
}
}
#[doc = "IO port A clock enable during sleep mode"]
pub type GPIOALPEN_A = OTGHSULPILPEN_A;
#[doc = "Reader of field `GPIOALPEN`"]
pub type GPIOALPEN_R = crate::R<bool, OTGHSULPILPEN_A>;
#[doc = "Write proxy for field `GPIOALPEN`"]
pub struct GPIOALPEN_W<'a> {
w: &'a mut W,
}
impl<'a> GPIOALPEN_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: GPIOALPEN_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "Selected module is disabled during Sleep mode"]
#[inline(always)]
pub fn disabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::DISABLEDINSLEEP)
}
#[doc = "Selected module is enabled during Sleep mode"]
#[inline(always)]
pub fn enabled_in_sleep(self) -> &'a mut W {
self.variant(OTGHSULPILPEN_A::ENABLEDINSLEEP)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01);
self.w
}
}
impl R {
#[doc = "Bit 30 - USB OTG HS ULPI clock enable during Sleep mode"]
#[inline(always)]
pub fn otghsulpilpen(&self) -> OTGHSULPILPEN_R {
OTGHSULPILPEN_R::new(((self.bits >> 30) & 0x01) != 0)
}
#[doc = "Bit 29 - USB OTG HS clock enable during Sleep mode"]
#[inline(always)]
pub fn otghslpen(&self) -> OTGHSLPEN_R {
OTGHSLPEN_R::new(((self.bits >> 29) & 0x01) != 0)
}
#[doc = "Bit 28 - Ethernet PTP clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmacptplpen(&self) -> ETHMACPTPLPEN_R {
ETHMACPTPLPEN_R::new(((self.bits >> 28) & 0x01) != 0)
}
#[doc = "Bit 27 - Ethernet reception clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmacrxlpen(&self) -> ETHMACRXLPEN_R {
ETHMACRXLPEN_R::new(((self.bits >> 27) & 0x01) != 0)
}
#[doc = "Bit 26 - Ethernet transmission clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmactxlpen(&self) -> ETHMACTXLPEN_R {
ETHMACTXLPEN_R::new(((self.bits >> 26) & 0x01) != 0)
}
#[doc = "Bit 25 - Ethernet MAC clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmaclpen(&self) -> ETHMACLPEN_R {
ETHMACLPEN_R::new(((self.bits >> 25) & 0x01) != 0)
}
#[doc = "Bit 22 - DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub fn dma2lpen(&self) -> DMA2LPEN_R {
DMA2LPEN_R::new(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 21 - DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub fn dma1lpen(&self) -> DMA1LPEN_R {
DMA1LPEN_R::new(((self.bits >> 21) & 0x01) != 0)
}
#[doc = "Bit 18 - Backup SRAM interface clock enable during Sleep mode"]
#[inline(always)]
pub fn bkpsramlpen(&self) -> BKPSRAMLPEN_R {
BKPSRAMLPEN_R::new(((self.bits >> 18) & 0x01) != 0)
}
#[doc = "Bit 17 - SRAM 2 interface clock enable during Sleep mode"]
#[inline(always)]
pub fn sram2lpen(&self) -> SRAM2LPEN_R {
SRAM2LPEN_R::new(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 16 - SRAM 1interface clock enable during Sleep mode"]
#[inline(always)]
pub fn sram1lpen(&self) -> SRAM1LPEN_R {
SRAM1LPEN_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 15 - Flash interface clock enable during Sleep mode"]
#[inline(always)]
pub fn flitflpen(&self) -> FLITFLPEN_R {
FLITFLPEN_R::new(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 12 - CRC clock enable during Sleep mode"]
#[inline(always)]
pub fn crclpen(&self) -> CRCLPEN_R {
CRCLPEN_R::new(((self.bits >> 12) & 0x01) != 0)
}
#[doc = "Bit 8 - IO port I clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioilpen(&self) -> GPIOILPEN_R {
GPIOILPEN_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 7 - IO port H clock enable during Sleep mode"]
#[inline(always)]
pub fn gpiohlpen(&self) -> GPIOHLPEN_R {
GPIOHLPEN_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bit 6 - IO port G clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioglpen(&self) -> GPIOGLPEN_R {
GPIOGLPEN_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 5 - IO port F clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioflpen(&self) -> GPIOFLPEN_R {
GPIOFLPEN_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 4 - IO port E clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioelpen(&self) -> GPIOELPEN_R {
GPIOELPEN_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 3 - IO port D clock enable during Sleep mode"]
#[inline(always)]
pub fn gpiodlpen(&self) -> GPIODLPEN_R {
GPIODLPEN_R::new(((self.bits >> 3) & 0x01) != 0)
}
#[doc = "Bit 2 - IO port C clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioclpen(&self) -> GPIOCLPEN_R {
GPIOCLPEN_R::new(((self.bits >> 2) & 0x01) != 0)
}
#[doc = "Bit 1 - IO port B clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioblpen(&self) -> GPIOBLPEN_R {
GPIOBLPEN_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 0 - IO port A clock enable during sleep mode"]
#[inline(always)]
pub fn gpioalpen(&self) -> GPIOALPEN_R {
GPIOALPEN_R::new((self.bits & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 30 - USB OTG HS ULPI clock enable during Sleep mode"]
#[inline(always)]
pub fn otghsulpilpen(&mut self) -> OTGHSULPILPEN_W {
OTGHSULPILPEN_W { w: self }
}
#[doc = "Bit 29 - USB OTG HS clock enable during Sleep mode"]
#[inline(always)]
pub fn otghslpen(&mut self) -> OTGHSLPEN_W {
OTGHSLPEN_W { w: self }
}
#[doc = "Bit 28 - Ethernet PTP clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmacptplpen(&mut self) -> ETHMACPTPLPEN_W {
ETHMACPTPLPEN_W { w: self }
}
#[doc = "Bit 27 - Ethernet reception clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmacrxlpen(&mut self) -> ETHMACRXLPEN_W {
ETHMACRXLPEN_W { w: self }
}
#[doc = "Bit 26 - Ethernet transmission clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmactxlpen(&mut self) -> ETHMACTXLPEN_W {
ETHMACTXLPEN_W { w: self }
}
#[doc = "Bit 25 - Ethernet MAC clock enable during Sleep mode"]
#[inline(always)]
pub fn ethmaclpen(&mut self) -> ETHMACLPEN_W {
ETHMACLPEN_W { w: self }
}
#[doc = "Bit 22 - DMA2 clock enable during Sleep mode"]
#[inline(always)]
pub fn dma2lpen(&mut self) -> DMA2LPEN_W {
DMA2LPEN_W { w: self }
}
#[doc = "Bit 21 - DMA1 clock enable during Sleep mode"]
#[inline(always)]
pub fn dma1lpen(&mut self) -> DMA1LPEN_W {
DMA1LPEN_W { w: self }
}
#[doc = "Bit 18 - Backup SRAM interface clock enable during Sleep mode"]
#[inline(always)]
pub fn bkpsramlpen(&mut self) -> BKPSRAMLPEN_W {
BKPSRAMLPEN_W { w: self }
}
#[doc = "Bit 17 - SRAM 2 interface clock enable during Sleep mode"]
#[inline(always)]
pub fn sram2lpen(&mut self) -> SRAM2LPEN_W {
SRAM2LPEN_W { w: self }
}
#[doc = "Bit 16 - SRAM 1interface clock enable during Sleep mode"]
#[inline(always)]
pub fn sram1lpen(&mut self) -> SRAM1LPEN_W {
SRAM1LPEN_W { w: self }
}
#[doc = "Bit 15 - Flash interface clock enable during Sleep mode"]
#[inline(always)]
pub fn flitflpen(&mut self) -> FLITFLPEN_W {
FLITFLPEN_W { w: self }
}
#[doc = "Bit 12 - CRC clock enable during Sleep mode"]
#[inline(always)]
pub fn crclpen(&mut self) -> CRCLPEN_W {
CRCLPEN_W { w: self }
}
#[doc = "Bit 8 - IO port I clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioilpen(&mut self) -> GPIOILPEN_W {
GPIOILPEN_W { w: self }
}
#[doc = "Bit 7 - IO port H clock enable during Sleep mode"]
#[inline(always)]
pub fn gpiohlpen(&mut self) -> GPIOHLPEN_W {
GPIOHLPEN_W { w: self }
}
#[doc = "Bit 6 - IO port G clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioglpen(&mut self) -> GPIOGLPEN_W {
GPIOGLPEN_W { w: self }
}
#[doc = "Bit 5 - IO port F clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioflpen(&mut self) -> GPIOFLPEN_W {
GPIOFLPEN_W { w: self }
}
#[doc = "Bit 4 - IO port E clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioelpen(&mut self) -> GPIOELPEN_W {
GPIOELPEN_W { w: self }
}
#[doc = "Bit 3 - IO port D clock enable during Sleep mode"]
#[inline(always)]
pub fn gpiodlpen(&mut self) -> GPIODLPEN_W {
GPIODLPEN_W { w: self }
}
#[doc = "Bit 2 - IO port C clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioclpen(&mut self) -> GPIOCLPEN_W {
GPIOCLPEN_W { w: self }
}
#[doc = "Bit 1 - IO port B clock enable during Sleep mode"]
#[inline(always)]
pub fn gpioblpen(&mut self) -> GPIOBLPEN_W {
GPIOBLPEN_W { w: self }
}
#[doc = "Bit 0 - IO port A clock enable during sleep mode"]
#[inline(always)]
pub fn gpioalpen(&mut self) -> GPIOALPEN_W {
GPIOALPEN_W { w: self }
}
}