1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101
#[doc = "Reader of register DCKCFGR"] pub type R = crate::R<u32, super::DCKCFGR>; #[doc = "Writer for register DCKCFGR"] pub type W = crate::W<u32, super::DCKCFGR>; #[doc = "Register DCKCFGR `reset()`'s with value 0"] impl crate::ResetValue for super::DCKCFGR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Timers clocks prescalers selection\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum TIMPRE_A { #[doc = "0: If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx"] MUL2 = 0, #[doc = "1: If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx"] MUL4 = 1, } impl From<TIMPRE_A> for bool { #[inline(always)] fn from(variant: TIMPRE_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `TIMPRE`"] pub type TIMPRE_R = crate::R<bool, TIMPRE_A>; impl TIMPRE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> TIMPRE_A { match self.bits { false => TIMPRE_A::MUL2, true => TIMPRE_A::MUL4, } } #[doc = "Checks if the value of the field is `MUL2`"] #[inline(always)] pub fn is_mul2(&self) -> bool { *self == TIMPRE_A::MUL2 } #[doc = "Checks if the value of the field is `MUL4`"] #[inline(always)] pub fn is_mul4(&self) -> bool { *self == TIMPRE_A::MUL4 } } #[doc = "Write proxy for field `TIMPRE`"] pub struct TIMPRE_W<'a> { w: &'a mut W, } impl<'a> TIMPRE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: TIMPRE_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx"] #[inline(always)] pub fn mul2(self) -> &'a mut W { self.variant(TIMPRE_A::MUL2) } #[doc = "If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx"] #[inline(always)] pub fn mul4(self) -> &'a mut W { self.variant(TIMPRE_A::MUL4) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } impl R { #[doc = "Bit 24 - Timers clocks prescalers selection"] #[inline(always)] pub fn timpre(&self) -> TIMPRE_R { TIMPRE_R::new(((self.bits >> 24) & 0x01) != 0) } } impl W { #[doc = "Bit 24 - Timers clocks prescalers selection"] #[inline(always)] pub fn timpre(&mut self) -> TIMPRE_W { TIMPRE_W { w: self } } }