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#[doc = "Reader of register HCCHAR2"] pub type R = crate::R<u32, super::HCCHAR2>; #[doc = "Writer for register HCCHAR2"] pub type W = crate::W<u32, super::HCCHAR2>; #[doc = "Register HCCHAR2 `reset()`'s with value 0"] impl crate::ResetValue for super::HCCHAR2 { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MPSIZ`"] pub type MPSIZ_R = crate::R<u16, u16>; #[doc = "Write proxy for field `MPSIZ`"] pub struct MPSIZ_W<'a> { w: &'a mut W, } impl<'a> MPSIZ_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x07ff) | ((value as u32) & 0x07ff); self.w } } #[doc = "Reader of field `EPNUM`"] pub type EPNUM_R = crate::R<u8, u8>; #[doc = "Write proxy for field `EPNUM`"] pub struct EPNUM_W<'a> { w: &'a mut W, } impl<'a> EPNUM_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 11)) | (((value as u32) & 0x0f) << 11); self.w } } #[doc = "Reader of field `EPDIR`"] pub type EPDIR_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EPDIR`"] pub struct EPDIR_W<'a> { w: &'a mut W, } impl<'a> EPDIR_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `LSDEV`"] pub type LSDEV_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LSDEV`"] pub struct LSDEV_W<'a> { w: &'a mut W, } impl<'a> LSDEV_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `EPTYP`"] pub type EPTYP_R = crate::R<u8, u8>; #[doc = "Write proxy for field `EPTYP`"] pub struct EPTYP_W<'a> { w: &'a mut W, } impl<'a> EPTYP_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18); self.w } } #[doc = "Reader of field `MCNT`"] pub type MCNT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MCNT`"] pub struct MCNT_W<'a> { w: &'a mut W, } impl<'a> MCNT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20); self.w } } #[doc = "Reader of field `DAD`"] pub type DAD_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DAD`"] pub struct DAD_W<'a> { w: &'a mut W, } impl<'a> DAD_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 22)) | (((value as u32) & 0x7f) << 22); self.w } } #[doc = "Reader of field `ODDFRM`"] pub type ODDFRM_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ODDFRM`"] pub struct ODDFRM_W<'a> { w: &'a mut W, } impl<'a> ODDFRM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Reader of field `CHDIS`"] pub type CHDIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHDIS`"] pub struct CHDIS_W<'a> { w: &'a mut W, } impl<'a> CHDIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `CHENA`"] pub type CHENA_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHENA`"] pub struct CHENA_W<'a> { w: &'a mut W, } impl<'a> CHENA_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] pub fn mpsiz(&self) -> MPSIZ_R { MPSIZ_R::new((self.bits & 0x07ff) as u16) } #[doc = "Bits 11:14 - Endpoint number"] #[inline(always)] pub fn epnum(&self) -> EPNUM_R { EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8) } #[doc = "Bit 15 - Endpoint direction"] #[inline(always)] pub fn epdir(&self) -> EPDIR_R { EPDIR_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 17 - Low-speed device"] #[inline(always)] pub fn lsdev(&self) -> LSDEV_R { LSDEV_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] pub fn eptyp(&self) -> EPTYP_R { EPTYP_R::new(((self.bits >> 18) & 0x03) as u8) } #[doc = "Bits 20:21 - Multicount"] #[inline(always)] pub fn mcnt(&self) -> MCNT_R { MCNT_R::new(((self.bits >> 20) & 0x03) as u8) } #[doc = "Bits 22:28 - Device address"] #[inline(always)] pub fn dad(&self) -> DAD_R { DAD_R::new(((self.bits >> 22) & 0x7f) as u8) } #[doc = "Bit 29 - Odd frame"] #[inline(always)] pub fn oddfrm(&self) -> ODDFRM_R { ODDFRM_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 30 - Channel disable"] #[inline(always)] pub fn chdis(&self) -> CHDIS_R { CHDIS_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - Channel enable"] #[inline(always)] pub fn chena(&self) -> CHENA_R { CHENA_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:10 - Maximum packet size"] #[inline(always)] pub fn mpsiz(&mut self) -> MPSIZ_W { MPSIZ_W { w: self } } #[doc = "Bits 11:14 - Endpoint number"] #[inline(always)] pub fn epnum(&mut self) -> EPNUM_W { EPNUM_W { w: self } } #[doc = "Bit 15 - Endpoint direction"] #[inline(always)] pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W { w: self } } #[doc = "Bit 17 - Low-speed device"] #[inline(always)] pub fn lsdev(&mut self) -> LSDEV_W { LSDEV_W { w: self } } #[doc = "Bits 18:19 - Endpoint type"] #[inline(always)] pub fn eptyp(&mut self) -> EPTYP_W { EPTYP_W { w: self } } #[doc = "Bits 20:21 - Multicount"] #[inline(always)] pub fn mcnt(&mut self) -> MCNT_W { MCNT_W { w: self } } #[doc = "Bits 22:28 - Device address"] #[inline(always)] pub fn dad(&mut self) -> DAD_W { DAD_W { w: self } } #[doc = "Bit 29 - Odd frame"] #[inline(always)] pub fn oddfrm(&mut self) -> ODDFRM_W { ODDFRM_W { w: self } } #[doc = "Bit 30 - Channel disable"] #[inline(always)] pub fn chdis(&mut self) -> CHDIS_W { CHDIS_W { w: self } } #[doc = "Bit 31 - Channel enable"] #[inline(always)] pub fn chena(&mut self) -> CHENA_W { CHENA_W { w: self } } }