Type Definition stm32f4::stm32f469::dsihost::dsi_wpcr1::W

type W = W<u32, DSI_WPCR1>;

Writer for register DSI_WPCR1

Methods

impl W

pub fn tclkposten(&mut self) -> TCLKPOSTEN_W

Bit 27 - custom time for tCLK-POST Enable

pub fn tlpxcen(&mut self) -> TLPXCEN_W

Bit 26 - custom time for tLPX for Clock lane Enable

pub fn thsexiten(&mut self) -> THSEXITEN_W

Bit 25 - custom time for tHS-EXIT Enable

pub fn tlpxden(&mut self) -> TLPXDEN_W

Bit 24 - custom time for tLPX for Data lanes Enable

pub fn thszeroen(&mut self) -> THSZEROEN_W

Bit 23 - custom time for tHS-ZERO Enable

pub fn thstrailen(&mut self) -> THSTRAILEN_W

Bit 22 - custom time for tHS-TRAIL Enable

pub fn thsprepen(&mut self) -> THSPREPEN_W

Bit 21 - custom time for tHS-PREPARE Enable

pub fn tclkzeroen(&mut self) -> TCLKZEROEN_W

Bit 20 - custom time for tCLK-ZERO Enable

pub fn tclkprepen(&mut self) -> TCLKPREPEN_W

Bit 19 - custom time for tCLK-PREPARE Enable

pub fn pden(&mut self) -> PDEN_W

Bit 18 - Pull-Down Enable

pub fn tddl(&mut self) -> TDDL_W

Bit 16 - Turn Disable Data Lanes

pub fn cdoffdl(&mut self) -> CDOFFDL_W

Bit 14 - Contention Detection OFF on Data Lanes

pub fn ftxsmdl(&mut self) -> FTXSMDL_W

Bit 13 - Force in TX Stop Mode the Data Lanes

pub fn ftxsmcl(&mut self) -> FTXSMCL_W

Bit 12 - Force in TX Stop Mode the Clock Lane

pub fn hsidl1(&mut self) -> HSIDL1_W

Bit 11 - Invert the High-Speed data signal on Data Lane 1

pub fn hsidl0(&mut self) -> HSIDL0_W

Bit 10 - Invert the Hight-Speed data signal on Data Lane 0

pub fn hsicl(&mut self) -> HSICL_W

Bit 9 - Invert Hight-Speed data signal on Clock Lane

pub fn swdl1(&mut self) -> SWDL1_W

Bit 8 - Swap Data Lane 1 pins

pub fn swdl0(&mut self) -> SWDL0_W

Bit 7 - Swap Data Lane 0 pins

pub fn swcl(&mut self) -> SWCL_W

Bit 6 - Swap Clock Lane pins

pub fn uix4(&mut self) -> UIX4_W

Bits 0:5 - Unit Interval multiplied by 4