[][src]Type Definition stm32f4::stm32f413::dfsdm2::flt::cr1::W

type W = W<u32, CR1>;

Writer for register CR1

Methods

impl W[src]

pub fn awfsel(&mut self) -> AWFSEL_W[src]

Bit 30 - Analog watchdog fast mode select

pub fn fast(&mut self) -> FAST_W[src]

Bit 29 - Fast conversion mode selection for regular conversions

pub fn rch(&mut self) -> RCH_W[src]

Bits 24:26 - Regular channel selection

pub fn rdmaen(&mut self) -> RDMAEN_W[src]

Bit 21 - DMA channel enabled to read data for the regular conversion

pub fn rsync(&mut self) -> RSYNC_W[src]

Bit 19 - Launch regular conversion synchronously with DFSDM0

pub fn rcont(&mut self) -> RCONT_W[src]

Bit 18 - Continuous mode selection for regular conversions

pub fn rswstart(&mut self) -> RSWSTART_W[src]

Bit 17 - Software start of a conversion on the regular channel

pub fn jexten(&mut self) -> JEXTEN_W[src]

Bits 13:14 - Trigger enable and trigger edge selection for injected conversions

pub fn jextsel(&mut self) -> JEXTSEL_W[src]

Bits 8:10 - Trigger signal selection for launching injected conversions

pub fn jdmaen(&mut self) -> JDMAEN_W[src]

Bit 5 - DMA channel enabled to read data for the injected channel group

pub fn jscan(&mut self) -> JSCAN_W[src]

Bit 4 - Scanning conversion mode for injected conversions

pub fn jsync(&mut self) -> JSYNC_W[src]

Bit 3 - Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger

pub fn jswstart(&mut self) -> JSWSTART_W[src]

Bit 1 - Start a conversion of the injected group of channels

pub fn dfen(&mut self) -> DFEN_W[src]

Bit 0 - DFSDM enable