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#[doc = "Reader of register AHB3ENR"] pub type R = crate::R<u32, super::AHB3ENR>; #[doc = "Writer for register AHB3ENR"] pub type W = crate::W<u32, super::AHB3ENR>; #[doc = "Register AHB3ENR `reset()`'s with value 0"] impl crate::ResetValue for super::AHB3ENR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Flexible memory controller module clock enable\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum FSMCEN_A { #[doc = "0: The selected clock is disabled"] DISABLED = 0, #[doc = "1: The selected clock is enabled"] ENABLED = 1, } impl From<FSMCEN_A> for bool { #[inline(always)] fn from(variant: FSMCEN_A) -> Self { variant as u8 != 0 } } #[doc = "Reader of field `FSMCEN`"] pub type FSMCEN_R = crate::R<bool, FSMCEN_A>; impl FSMCEN_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> FSMCEN_A { match self.bits { false => FSMCEN_A::DISABLED, true => FSMCEN_A::ENABLED, } } #[doc = "Checks if the value of the field is `DISABLED`"] #[inline(always)] pub fn is_disabled(&self) -> bool { *self == FSMCEN_A::DISABLED } #[doc = "Checks if the value of the field is `ENABLED`"] #[inline(always)] pub fn is_enabled(&self) -> bool { *self == FSMCEN_A::ENABLED } } #[doc = "Write proxy for field `FSMCEN`"] pub struct FSMCEN_W<'a> { w: &'a mut W, } impl<'a> FSMCEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: FSMCEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "The selected clock is disabled"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(FSMCEN_A::DISABLED) } #[doc = "The selected clock is enabled"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(FSMCEN_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !0x01) | ((value as u32) & 0x01); self.w } } #[doc = "QUADSPI memory controller module clock enable"] pub type QSPIEN_A = FSMCEN_A; #[doc = "Reader of field `QSPIEN`"] pub type QSPIEN_R = crate::R<bool, FSMCEN_A>; #[doc = "Write proxy for field `QSPIEN`"] pub struct QSPIEN_W<'a> { w: &'a mut W, } impl<'a> QSPIEN_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: QSPIEN_A) -> &'a mut W { { self.bit(variant.into()) } } #[doc = "The selected clock is disabled"] #[inline(always)] pub fn disabled(self) -> &'a mut W { self.variant(FSMCEN_A::DISABLED) } #[doc = "The selected clock is enabled"] #[inline(always)] pub fn enabled(self) -> &'a mut W { self.variant(FSMCEN_A::ENABLED) } #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 1)) | (((value as u32) & 0x01) << 1); self.w } } impl R { #[doc = "Bit 0 - Flexible memory controller module clock enable"] #[inline(always)] pub fn fsmcen(&self) -> FSMCEN_R { FSMCEN_R::new((self.bits & 0x01) != 0) } #[doc = "Bit 1 - QUADSPI memory controller module clock enable"] #[inline(always)] pub fn qspien(&self) -> QSPIEN_R { QSPIEN_R::new(((self.bits >> 1) & 0x01) != 0) } } impl W { #[doc = "Bit 0 - Flexible memory controller module clock enable"] #[inline(always)] pub fn fsmcen(&mut self) -> FSMCEN_W { FSMCEN_W { w: self } } #[doc = "Bit 1 - QUADSPI memory controller module clock enable"] #[inline(always)] pub fn qspien(&mut self) -> QSPIEN_W { QSPIEN_W { w: self } } }