stm32f4_staging/stm32f469/rng/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Random number generator enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum RNGEN {
11    ///0: Random number generator is disabled
12    Disabled = 0,
13    ///1: Random number generator is enabled
14    Enabled = 1,
15}
16impl From<RNGEN> for bool {
17    #[inline(always)]
18    fn from(variant: RNGEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `RNGEN` reader - Random number generator enable
23pub type RNGEN_R = crate::BitReader<RNGEN>;
24impl RNGEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> RNGEN {
28        match self.bits {
29            false => RNGEN::Disabled,
30            true => RNGEN::Enabled,
31        }
32    }
33    ///Random number generator is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == RNGEN::Disabled
37    }
38    ///Random number generator is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == RNGEN::Enabled
42    }
43}
44///Field `RNGEN` writer - Random number generator enable
45pub type RNGEN_W<'a, REG> = crate::BitWriter<'a, REG, RNGEN>;
46impl<'a, REG> RNGEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Random number generator is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(RNGEN::Disabled)
54    }
55    ///Random number generator is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(RNGEN::Enabled)
59    }
60}
61/**Interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum IE {
67    ///0: RNG interrupt is disabled
68    Disabled = 0,
69    ///1: RNG interrupt is enabled
70    Enabled = 1,
71}
72impl From<IE> for bool {
73    #[inline(always)]
74    fn from(variant: IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `IE` reader - Interrupt enable
79pub type IE_R = crate::BitReader<IE>;
80impl IE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> IE {
84        match self.bits {
85            false => IE::Disabled,
86            true => IE::Enabled,
87        }
88    }
89    ///RNG interrupt is disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == IE::Disabled
93    }
94    ///RNG interrupt is enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == IE::Enabled
98    }
99}
100///Field `IE` writer - Interrupt enable
101pub type IE_W<'a, REG> = crate::BitWriter<'a, REG, IE>;
102impl<'a, REG> IE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///RNG interrupt is disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(IE::Disabled)
110    }
111    ///RNG interrupt is enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(IE::Enabled)
115    }
116}
117/**Clock error detection
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CED {
123    ///0: Clock error detection is enabled
124    Enabled = 0,
125    ///1: Clock error detection is disabled
126    Disabled = 1,
127}
128impl From<CED> for bool {
129    #[inline(always)]
130    fn from(variant: CED) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CED` reader - Clock error detection
135pub type CED_R = crate::BitReader<CED>;
136impl CED_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CED {
140        match self.bits {
141            false => CED::Enabled,
142            true => CED::Disabled,
143        }
144    }
145    ///Clock error detection is enabled
146    #[inline(always)]
147    pub fn is_enabled(&self) -> bool {
148        *self == CED::Enabled
149    }
150    ///Clock error detection is disabled
151    #[inline(always)]
152    pub fn is_disabled(&self) -> bool {
153        *self == CED::Disabled
154    }
155}
156///Field `CED` writer - Clock error detection
157pub type CED_W<'a, REG> = crate::BitWriter<'a, REG, CED>;
158impl<'a, REG> CED_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Clock error detection is enabled
163    #[inline(always)]
164    pub fn enabled(self) -> &'a mut crate::W<REG> {
165        self.variant(CED::Enabled)
166    }
167    ///Clock error detection is disabled
168    #[inline(always)]
169    pub fn disabled(self) -> &'a mut crate::W<REG> {
170        self.variant(CED::Disabled)
171    }
172}
173impl R {
174    ///Bit 2 - Random number generator enable
175    #[inline(always)]
176    pub fn rngen(&self) -> RNGEN_R {
177        RNGEN_R::new(((self.bits >> 2) & 1) != 0)
178    }
179    ///Bit 3 - Interrupt enable
180    #[inline(always)]
181    pub fn ie(&self) -> IE_R {
182        IE_R::new(((self.bits >> 3) & 1) != 0)
183    }
184    ///Bit 5 - Clock error detection
185    #[inline(always)]
186    pub fn ced(&self) -> CED_R {
187        CED_R::new(((self.bits >> 5) & 1) != 0)
188    }
189}
190impl core::fmt::Debug for R {
191    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
192        f.debug_struct("CR")
193            .field("ie", &self.ie())
194            .field("rngen", &self.rngen())
195            .field("ced", &self.ced())
196            .finish()
197    }
198}
199impl W {
200    ///Bit 2 - Random number generator enable
201    #[inline(always)]
202    pub fn rngen(&mut self) -> RNGEN_W<CRrs> {
203        RNGEN_W::new(self, 2)
204    }
205    ///Bit 3 - Interrupt enable
206    #[inline(always)]
207    pub fn ie(&mut self) -> IE_W<CRrs> {
208        IE_W::new(self, 3)
209    }
210    ///Bit 5 - Clock error detection
211    #[inline(always)]
212    pub fn ced(&mut self) -> CED_W<CRrs> {
213        CED_W::new(self, 5)
214    }
215}
216/**control register
217
218You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
219
220See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#RNG:CR)*/
221pub struct CRrs;
222impl crate::RegisterSpec for CRrs {
223    type Ux = u32;
224}
225///`read()` method returns [`cr::R`](R) reader structure
226impl crate::Readable for CRrs {}
227///`write(|w| ..)` method takes [`cr::W`](W) writer structure
228impl crate::Writable for CRrs {
229    type Safety = crate::Unsafe;
230}
231///`reset()` method sets CR to value 0
232impl crate::Resettable for CRrs {}
stm32f4_staging/stm32f469/rng/cr.rs

stm32f4_staging/stm32f469/rng/
cr.rs
