stm32f4_staging/stm32f469/
mod.rs

1/*!Peripheral access API for STM32F469 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMP_STAMP();
23    fn RTC_WKUP();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_STREAM0();
32    fn DMA1_STREAM1();
33    fn DMA1_STREAM2();
34    fn DMA1_STREAM3();
35    fn DMA1_STREAM4();
36    fn DMA1_STREAM5();
37    fn DMA1_STREAM6();
38    fn ADC();
39    fn CAN1_TX();
40    fn CAN1_RX0();
41    fn CAN1_RX1();
42    fn CAN1_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK_TIM9();
45    fn TIM1_UP_TIM10();
46    fn TIM1_TRG_COM_TIM11();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTC_ALARM();
62    fn OTG_FS_WKUP();
63    fn TIM8_BRK_TIM12();
64    fn TIM8_UP_TIM13();
65    fn TIM8_TRG_COM_TIM14();
66    fn TIM8_CC();
67    fn DMA1_STREAM7();
68    fn FMC();
69    fn SDIO();
70    fn TIM5();
71    fn SPI3();
72    fn UART4();
73    fn UART5();
74    fn TIM6_DAC();
75    fn TIM7();
76    fn DMA2_STREAM0();
77    fn DMA2_STREAM1();
78    fn DMA2_STREAM2();
79    fn DMA2_STREAM3();
80    fn DMA2_STREAM4();
81    fn ETH();
82    fn ETH_WKUP();
83    fn CAN2_TX();
84    fn CAN2_RX0();
85    fn CAN2_RX1();
86    fn CAN2_SCE();
87    fn OTG_FS();
88    fn DMA2_STREAM5();
89    fn DMA2_STREAM6();
90    fn DMA2_STREAM7();
91    fn USART6();
92    fn I2C3_EV();
93    fn I2C3_ER();
94    fn OTG_HS_EP1_OUT();
95    fn OTG_HS_EP1_IN();
96    fn OTG_HS_WKUP();
97    fn OTG_HS();
98    fn DCMI();
99    fn CRYP();
100    fn HASH_RNG();
101    fn FPU();
102    fn UART7();
103    fn UART8();
104    fn SPI4();
105    fn SPI5();
106    fn SPI6();
107    fn SAI1();
108    fn LCD_TFT();
109    fn LCD_TFT_1();
110    fn DMA2D();
111    fn QUADSPI();
112    fn DSIHOST();
113}
114#[doc(hidden)]
115#[repr(C)]
116pub union Vector {
117    _handler: unsafe extern "C" fn(),
118    _reserved: u32,
119}
120#[cfg(feature = "rt")]
121#[doc(hidden)]
122#[link_section = ".vector_table.interrupts"]
123#[no_mangle]
124pub static __INTERRUPTS: [Vector; 93] = [
125    Vector { _handler: WWDG },
126    Vector { _handler: PVD },
127    Vector {
128        _handler: TAMP_STAMP,
129    },
130    Vector { _handler: RTC_WKUP },
131    Vector { _handler: FLASH },
132    Vector { _handler: RCC },
133    Vector { _handler: EXTI0 },
134    Vector { _handler: EXTI1 },
135    Vector { _handler: EXTI2 },
136    Vector { _handler: EXTI3 },
137    Vector { _handler: EXTI4 },
138    Vector {
139        _handler: DMA1_STREAM0,
140    },
141    Vector {
142        _handler: DMA1_STREAM1,
143    },
144    Vector {
145        _handler: DMA1_STREAM2,
146    },
147    Vector {
148        _handler: DMA1_STREAM3,
149    },
150    Vector {
151        _handler: DMA1_STREAM4,
152    },
153    Vector {
154        _handler: DMA1_STREAM5,
155    },
156    Vector {
157        _handler: DMA1_STREAM6,
158    },
159    Vector { _handler: ADC },
160    Vector { _handler: CAN1_TX },
161    Vector { _handler: CAN1_RX0 },
162    Vector { _handler: CAN1_RX1 },
163    Vector { _handler: CAN1_SCE },
164    Vector { _handler: EXTI9_5 },
165    Vector {
166        _handler: TIM1_BRK_TIM9,
167    },
168    Vector {
169        _handler: TIM1_UP_TIM10,
170    },
171    Vector {
172        _handler: TIM1_TRG_COM_TIM11,
173    },
174    Vector { _handler: TIM1_CC },
175    Vector { _handler: TIM2 },
176    Vector { _handler: TIM3 },
177    Vector { _handler: TIM4 },
178    Vector { _handler: I2C1_EV },
179    Vector { _handler: I2C1_ER },
180    Vector { _handler: I2C2_EV },
181    Vector { _handler: I2C2_ER },
182    Vector { _handler: SPI1 },
183    Vector { _handler: SPI2 },
184    Vector { _handler: USART1 },
185    Vector { _handler: USART2 },
186    Vector { _handler: USART3 },
187    Vector {
188        _handler: EXTI15_10,
189    },
190    Vector {
191        _handler: RTC_ALARM,
192    },
193    Vector {
194        _handler: OTG_FS_WKUP,
195    },
196    Vector {
197        _handler: TIM8_BRK_TIM12,
198    },
199    Vector {
200        _handler: TIM8_UP_TIM13,
201    },
202    Vector {
203        _handler: TIM8_TRG_COM_TIM14,
204    },
205    Vector { _handler: TIM8_CC },
206    Vector {
207        _handler: DMA1_STREAM7,
208    },
209    Vector { _handler: FMC },
210    Vector { _handler: SDIO },
211    Vector { _handler: TIM5 },
212    Vector { _handler: SPI3 },
213    Vector { _handler: UART4 },
214    Vector { _handler: UART5 },
215    Vector { _handler: TIM6_DAC },
216    Vector { _handler: TIM7 },
217    Vector {
218        _handler: DMA2_STREAM0,
219    },
220    Vector {
221        _handler: DMA2_STREAM1,
222    },
223    Vector {
224        _handler: DMA2_STREAM2,
225    },
226    Vector {
227        _handler: DMA2_STREAM3,
228    },
229    Vector {
230        _handler: DMA2_STREAM4,
231    },
232    Vector { _handler: ETH },
233    Vector { _handler: ETH_WKUP },
234    Vector { _handler: CAN2_TX },
235    Vector { _handler: CAN2_RX0 },
236    Vector { _handler: CAN2_RX1 },
237    Vector { _handler: CAN2_SCE },
238    Vector { _handler: OTG_FS },
239    Vector {
240        _handler: DMA2_STREAM5,
241    },
242    Vector {
243        _handler: DMA2_STREAM6,
244    },
245    Vector {
246        _handler: DMA2_STREAM7,
247    },
248    Vector { _handler: USART6 },
249    Vector { _handler: I2C3_EV },
250    Vector { _handler: I2C3_ER },
251    Vector {
252        _handler: OTG_HS_EP1_OUT,
253    },
254    Vector {
255        _handler: OTG_HS_EP1_IN,
256    },
257    Vector {
258        _handler: OTG_HS_WKUP,
259    },
260    Vector { _handler: OTG_HS },
261    Vector { _handler: DCMI },
262    Vector { _handler: CRYP },
263    Vector { _handler: HASH_RNG },
264    Vector { _handler: FPU },
265    Vector { _handler: UART7 },
266    Vector { _handler: UART8 },
267    Vector { _handler: SPI4 },
268    Vector { _handler: SPI5 },
269    Vector { _handler: SPI6 },
270    Vector { _handler: SAI1 },
271    Vector { _handler: LCD_TFT },
272    Vector {
273        _handler: LCD_TFT_1,
274    },
275    Vector { _handler: DMA2D },
276    Vector { _handler: QUADSPI },
277    Vector { _handler: DSIHOST },
278];
279///Enumeration of all the interrupts.
280#[cfg_attr(feature = "defmt", derive(defmt::Format))]
281#[derive(Copy, Clone, Debug, PartialEq, Eq)]
282#[repr(u16)]
283pub enum Interrupt {
284    ///0 - Window Watchdog interrupt
285    WWDG = 0,
286    ///1 - PVD through EXTI line detection interrupt
287    PVD = 1,
288    ///2 - Tamper and TimeStamp interrupts through the EXTI line
289    TAMP_STAMP = 2,
290    ///3 - RTC Wakeup interrupt through the EXTI line
291    RTC_WKUP = 3,
292    ///4 - Flash global interrupt
293    FLASH = 4,
294    ///5 - RCC global interrupt
295    RCC = 5,
296    ///6 - EXTI Line0 interrupt
297    EXTI0 = 6,
298    ///7 - EXTI Line1 interrupt
299    EXTI1 = 7,
300    ///8 - EXTI Line2 interrupt
301    EXTI2 = 8,
302    ///9 - EXTI Line3 interrupt
303    EXTI3 = 9,
304    ///10 - EXTI Line4 interrupt
305    EXTI4 = 10,
306    ///11 - DMA1 Stream0 global interrupt
307    DMA1_STREAM0 = 11,
308    ///12 - DMA1 Stream1 global interrupt
309    DMA1_STREAM1 = 12,
310    ///13 - DMA1 Stream2 global interrupt
311    DMA1_STREAM2 = 13,
312    ///14 - DMA1 Stream3 global interrupt
313    DMA1_STREAM3 = 14,
314    ///15 - DMA1 Stream4 global interrupt
315    DMA1_STREAM4 = 15,
316    ///16 - DMA1 Stream5 global interrupt
317    DMA1_STREAM5 = 16,
318    ///17 - DMA1 Stream6 global interrupt
319    DMA1_STREAM6 = 17,
320    ///18 - ADC1 global interrupt
321    ADC = 18,
322    ///19 - CAN1 TX interrupts
323    CAN1_TX = 19,
324    ///20 - CAN1 RX0 interrupts
325    CAN1_RX0 = 20,
326    ///21 - CAN1 RX1 interrupts
327    CAN1_RX1 = 21,
328    ///22 - CAN1 SCE interrupt
329    CAN1_SCE = 22,
330    ///23 - EXTI Line\[9:5\] interrupts
331    EXTI9_5 = 23,
332    ///24 - TIM1 Break interrupt and TIM9 global interrupt
333    TIM1_BRK_TIM9 = 24,
334    ///25 - TIM1 Update interrupt and TIM10 global interrupt
335    TIM1_UP_TIM10 = 25,
336    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
337    TIM1_TRG_COM_TIM11 = 26,
338    ///27 - TIM1 Capture Compare interrupt
339    TIM1_CC = 27,
340    ///28 - TIM2 global interrupt
341    TIM2 = 28,
342    ///29 - TIM3 global interrupt
343    TIM3 = 29,
344    ///30 - TIM4 global interrupt
345    TIM4 = 30,
346    ///31 - I2C1 event interrupt
347    I2C1_EV = 31,
348    ///32 - I2C1 error interrupt
349    I2C1_ER = 32,
350    ///33 - I2C2 event interrupt
351    I2C2_EV = 33,
352    ///34 - I2C2 error interrupt
353    I2C2_ER = 34,
354    ///35 - SPI1 global interrupt
355    SPI1 = 35,
356    ///36 - SPI2 global interrupt
357    SPI2 = 36,
358    ///37 - USART1 global interrupt
359    USART1 = 37,
360    ///38 - USART2 global interrupt
361    USART2 = 38,
362    ///39 - USART3 global interrupt
363    USART3 = 39,
364    ///40 - EXTI Line\[15:10\] interrupts
365    EXTI15_10 = 40,
366    ///41 - RTC Alarms (A and B) through EXTI line interrupt
367    RTC_ALARM = 41,
368    ///42 - USB On-The-Go FS Wakeup through EXTI line interrupt
369    OTG_FS_WKUP = 42,
370    ///43 - TIM8 Break interrupt and TIM12 global interrupt
371    TIM8_BRK_TIM12 = 43,
372    ///44 - TIM8 Update interrupt and TIM13 global interrupt
373    TIM8_UP_TIM13 = 44,
374    ///45 - TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
375    TIM8_TRG_COM_TIM14 = 45,
376    ///46 - TIM8 Capture Compare interrupt
377    TIM8_CC = 46,
378    ///47 - DMA1 Stream7 global interrupt
379    DMA1_STREAM7 = 47,
380    ///48 - FMC global interrupt
381    FMC = 48,
382    ///49 - SDIO global interrupt
383    SDIO = 49,
384    ///50 - TIM5 global interrupt
385    TIM5 = 50,
386    ///51 - SPI3 global interrupt
387    SPI3 = 51,
388    ///52 - UART4 global interrupt
389    UART4 = 52,
390    ///53 - UART5 global interrupt
391    UART5 = 53,
392    ///54 - TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
393    TIM6_DAC = 54,
394    ///55 - TIM7 global interrupt
395    TIM7 = 55,
396    ///56 - DMA2 Stream0 global interrupt
397    DMA2_STREAM0 = 56,
398    ///57 - DMA2 Stream1 global interrupt
399    DMA2_STREAM1 = 57,
400    ///58 - DMA2 Stream2 global interrupt
401    DMA2_STREAM2 = 58,
402    ///59 - DMA2 Stream3 global interrupt
403    DMA2_STREAM3 = 59,
404    ///60 - DMA2 Stream4 global interrupt
405    DMA2_STREAM4 = 60,
406    ///61 - Ethernet global interrupt
407    ETH = 61,
408    ///62 - Ethernet Wakeup through EXTI line interrupt
409    ETH_WKUP = 62,
410    ///63 - CAN2 TX interrupts
411    CAN2_TX = 63,
412    ///64 - CAN2 RX0 interrupts
413    CAN2_RX0 = 64,
414    ///65 - CAN2 RX1 interrupts
415    CAN2_RX1 = 65,
416    ///66 - CAN2 SCE interrupt
417    CAN2_SCE = 66,
418    ///67 - USB On The Go FS global interrupt
419    OTG_FS = 67,
420    ///68 - DMA2 Stream5 global interrupt
421    DMA2_STREAM5 = 68,
422    ///69 - DMA2 Stream6 global interrupt
423    DMA2_STREAM6 = 69,
424    ///70 - DMA2 Stream7 global interrupt
425    DMA2_STREAM7 = 70,
426    ///71 - USART6 global interrupt
427    USART6 = 71,
428    ///72 - I2C3 event interrupt
429    I2C3_EV = 72,
430    ///73 - I2C3 error interrupt
431    I2C3_ER = 73,
432    ///74 - USB On The Go HS End Point 1 Out global interrupt
433    OTG_HS_EP1_OUT = 74,
434    ///75 - USB On The Go HS End Point 1 In global interrupt
435    OTG_HS_EP1_IN = 75,
436    ///76 - USB On The Go HS Wakeup through EXTI interrupt
437    OTG_HS_WKUP = 76,
438    ///77 - USB On The Go HS global interrupt
439    OTG_HS = 77,
440    ///78 - DCMI global interrupt
441    DCMI = 78,
442    ///79 - CRYP crypto global interrupt
443    CRYP = 79,
444    ///80 - Hash and Rng global interrupt
445    HASH_RNG = 80,
446    ///81 - Floating point unit interrupt
447    FPU = 81,
448    ///82 - UART 7 global interrupt
449    UART7 = 82,
450    ///83 - UART 8 global interrupt
451    UART8 = 83,
452    ///84 - SPI 4 global interrupt
453    SPI4 = 84,
454    ///85 - SPI 5 global interrupt
455    SPI5 = 85,
456    ///86 - SPI 6 global interrupt
457    SPI6 = 86,
458    ///87 - SAI1 global interrupt
459    SAI1 = 87,
460    ///88 - LTDC global interrupt
461    LCD_TFT = 88,
462    ///89 - LTDC global error interrupt
463    LCD_TFT_1 = 89,
464    ///90 - DMA2D global interrupt
465    DMA2D = 90,
466    ///91 - QuadSPI global interrupt
467    QUADSPI = 91,
468    ///92 - DSI host global interrupt
469    DSIHOST = 92,
470}
471unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
472    #[inline(always)]
473    fn number(self) -> u16 {
474        self as u16
475    }
476}
477///Random number generator
478///
479///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#RNG)
480pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
481impl core::fmt::Debug for RNG {
482    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
483        f.debug_struct("RNG").finish()
484    }
485}
486///Random number generator
487pub mod rng;
488///Hash processor
489///
490///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#HASH)
491pub type HASH = crate::Periph<hash::RegisterBlock, 0x5006_0400>;
492impl core::fmt::Debug for HASH {
493    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
494        f.debug_struct("HASH").finish()
495    }
496}
497///Hash processor
498pub mod hash;
499///Cryptographic processor
500///
501///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#CRYP)
502pub type CRYP = crate::Periph<cryp::RegisterBlock, 0x5006_0000>;
503impl core::fmt::Debug for CRYP {
504    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
505        f.debug_struct("CRYP").finish()
506    }
507}
508///Cryptographic processor
509pub mod cryp;
510///Digital camera interface
511///
512///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DCMI)
513pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x5005_0000>;
514impl core::fmt::Debug for DCMI {
515    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
516        f.debug_struct("DCMI").finish()
517    }
518}
519///Digital camera interface
520pub mod dcmi;
521///Flexible memory controller
522///
523///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#FMC)
524pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0000>;
525impl core::fmt::Debug for FMC {
526    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
527        f.debug_struct("FMC").finish()
528    }
529}
530///Flexible memory controller
531pub mod fmc;
532///Debug support
533///
534///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DBGMCU)
535pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
536impl core::fmt::Debug for DBGMCU {
537    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
538        f.debug_struct("DBGMCU").finish()
539    }
540}
541///Debug support
542pub mod dbgmcu;
543///DMA controller
544///
545///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DMA2)
546pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
547impl core::fmt::Debug for DMA2 {
548    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
549        f.debug_struct("DMA2").finish()
550    }
551}
552///DMA controller
553pub mod dma2;
554///DMA controller
555///
556///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DMA2)
557pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
558impl core::fmt::Debug for DMA1 {
559    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
560        f.debug_struct("DMA1").finish()
561    }
562}
563///DMA controller
564pub use self::dma2 as dma1;
565///Reset and clock control
566///
567///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#RCC)
568pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
569impl core::fmt::Debug for RCC {
570    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
571        f.debug_struct("RCC").finish()
572    }
573}
574///Reset and clock control
575pub mod rcc;
576///General-purpose I/Os
577///
578///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
579pub type GPIOK = crate::Periph<gpiok::RegisterBlock, 0x4002_2800>;
580impl core::fmt::Debug for GPIOK {
581    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
582        f.debug_struct("GPIOK").finish()
583    }
584}
585///General-purpose I/Os
586pub mod gpiok;
587///General-purpose I/Os
588///
589///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
590pub type GPIOJ = crate::Periph<gpiok::RegisterBlock, 0x4002_2400>;
591impl core::fmt::Debug for GPIOJ {
592    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
593        f.debug_struct("GPIOJ").finish()
594    }
595}
596///General-purpose I/Os
597pub use self::gpiok as gpioj;
598///General-purpose I/Os
599///
600///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
601pub type GPIOI = crate::Periph<gpiok::RegisterBlock, 0x4002_2000>;
602impl core::fmt::Debug for GPIOI {
603    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
604        f.debug_struct("GPIOI").finish()
605    }
606}
607///General-purpose I/Os
608pub use self::gpiok as gpioi;
609///General-purpose I/Os
610///
611///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
612pub type GPIOH = crate::Periph<gpiok::RegisterBlock, 0x4002_1c00>;
613impl core::fmt::Debug for GPIOH {
614    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
615        f.debug_struct("GPIOH").finish()
616    }
617}
618///General-purpose I/Os
619pub use self::gpiok as gpioh;
620///General-purpose I/Os
621///
622///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
623pub type GPIOG = crate::Periph<gpiok::RegisterBlock, 0x4002_1800>;
624impl core::fmt::Debug for GPIOG {
625    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
626        f.debug_struct("GPIOG").finish()
627    }
628}
629///General-purpose I/Os
630pub use self::gpiok as gpiog;
631///General-purpose I/Os
632///
633///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
634pub type GPIOF = crate::Periph<gpiok::RegisterBlock, 0x4002_1400>;
635impl core::fmt::Debug for GPIOF {
636    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
637        f.debug_struct("GPIOF").finish()
638    }
639}
640///General-purpose I/Os
641pub use self::gpiok as gpiof;
642///General-purpose I/Os
643///
644///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
645pub type GPIOE = crate::Periph<gpiok::RegisterBlock, 0x4002_1000>;
646impl core::fmt::Debug for GPIOE {
647    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
648        f.debug_struct("GPIOE").finish()
649    }
650}
651///General-purpose I/Os
652pub use self::gpiok as gpioe;
653///General-purpose I/Os
654///
655///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
656pub type GPIOD = crate::Periph<gpiok::RegisterBlock, 0x4002_0c00>;
657impl core::fmt::Debug for GPIOD {
658    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
659        f.debug_struct("GPIOD").finish()
660    }
661}
662///General-purpose I/Os
663pub use self::gpiok as gpiod;
664///General-purpose I/Os
665///
666///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOK)
667pub type GPIOC = crate::Periph<gpiok::RegisterBlock, 0x4002_0800>;
668impl core::fmt::Debug for GPIOC {
669    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
670        f.debug_struct("GPIOC").finish()
671    }
672}
673///General-purpose I/Os
674pub use self::gpiok as gpioc;
675///General-purpose I/Os
676///
677///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOB)
678pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
679impl core::fmt::Debug for GPIOB {
680    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
681        f.debug_struct("GPIOB").finish()
682    }
683}
684///General-purpose I/Os
685pub mod gpiob;
686///General-purpose I/Os
687///
688///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#GPIOA)
689pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
690impl core::fmt::Debug for GPIOA {
691    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
692        f.debug_struct("GPIOA").finish()
693    }
694}
695///General-purpose I/Os
696pub mod gpioa;
697///System configuration controller
698///
699///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SYSCFG)
700pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
701impl core::fmt::Debug for SYSCFG {
702    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
703        f.debug_struct("SYSCFG").finish()
704    }
705}
706///System configuration controller
707pub mod syscfg;
708///Serial peripheral interface
709///
710///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
711pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
712impl core::fmt::Debug for SPI1 {
713    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
714        f.debug_struct("SPI1").finish()
715    }
716}
717///Serial peripheral interface
718pub mod spi1;
719///Serial peripheral interface
720///
721///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
722pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
723impl core::fmt::Debug for SPI2 {
724    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
725        f.debug_struct("SPI2").finish()
726    }
727}
728///Serial peripheral interface
729pub use self::spi1 as spi2;
730///Serial peripheral interface
731///
732///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
733pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
734impl core::fmt::Debug for SPI3 {
735    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
736        f.debug_struct("SPI3").finish()
737    }
738}
739///Serial peripheral interface
740pub use self::spi1 as spi3;
741///Serial peripheral interface
742///
743///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
744pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
745impl core::fmt::Debug for I2S2EXT {
746    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
747        f.debug_struct("I2S2EXT").finish()
748    }
749}
750///Serial peripheral interface
751pub use self::spi1 as i2s2ext;
752///Serial peripheral interface
753///
754///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
755pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
756impl core::fmt::Debug for I2S3EXT {
757    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
758        f.debug_struct("I2S3EXT").finish()
759    }
760}
761///Serial peripheral interface
762pub use self::spi1 as i2s3ext;
763///Serial peripheral interface
764///
765///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
766pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
767impl core::fmt::Debug for SPI4 {
768    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
769        f.debug_struct("SPI4").finish()
770    }
771}
772///Serial peripheral interface
773pub use self::spi1 as spi4;
774///Serial peripheral interface
775///
776///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
777pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4001_5000>;
778impl core::fmt::Debug for SPI5 {
779    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
780        f.debug_struct("SPI5").finish()
781    }
782}
783///Serial peripheral interface
784pub use self::spi1 as spi5;
785///Serial peripheral interface
786///
787///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SPI1)
788pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x4001_5400>;
789impl core::fmt::Debug for SPI6 {
790    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
791        f.debug_struct("SPI6").finish()
792    }
793}
794///Serial peripheral interface
795pub use self::spi1 as spi6;
796///Secure digital input/output interface
797///
798///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SDIO)
799pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
800impl core::fmt::Debug for SDIO {
801    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
802        f.debug_struct("SDIO").finish()
803    }
804}
805///Secure digital input/output interface
806pub mod sdio;
807///Analog-to-digital converter
808///
809///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#ADC1)
810pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
811impl core::fmt::Debug for ADC1 {
812    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
813        f.debug_struct("ADC1").finish()
814    }
815}
816///Analog-to-digital converter
817pub mod adc1;
818///Analog-to-digital converter
819///
820///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#ADC1)
821pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x4001_2100>;
822impl core::fmt::Debug for ADC2 {
823    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
824        f.debug_struct("ADC2").finish()
825    }
826}
827///Analog-to-digital converter
828pub use self::adc1 as adc2;
829///Analog-to-digital converter
830///
831///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#ADC1)
832pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x4001_2200>;
833impl core::fmt::Debug for ADC3 {
834    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
835        f.debug_struct("ADC3").finish()
836    }
837}
838///Analog-to-digital converter
839pub use self::adc1 as adc3;
840///Universal synchronous asynchronous receiver transmitter
841///
842///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#USART1)
843pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
844impl core::fmt::Debug for USART1 {
845    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
846        f.debug_struct("USART1").finish()
847    }
848}
849///Universal synchronous asynchronous receiver transmitter
850pub mod usart1;
851///Universal synchronous asynchronous receiver transmitter
852///
853///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#USART1)
854pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
855impl core::fmt::Debug for USART6 {
856    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
857        f.debug_struct("USART6").finish()
858    }
859}
860///Universal synchronous asynchronous receiver transmitter
861pub use self::usart1 as usart6;
862///Universal synchronous asynchronous receiver transmitter
863///
864///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#USART1)
865pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
866impl core::fmt::Debug for USART2 {
867    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
868        f.debug_struct("USART2").finish()
869    }
870}
871///Universal synchronous asynchronous receiver transmitter
872pub use self::usart1 as usart2;
873///Universal synchronous asynchronous receiver transmitter
874///
875///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#USART1)
876pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
877impl core::fmt::Debug for USART3 {
878    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
879        f.debug_struct("USART3").finish()
880    }
881}
882///Universal synchronous asynchronous receiver transmitter
883pub use self::usart1 as usart3;
884///Universal synchronous asynchronous receiver transmitter
885///
886///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#UART4)
887pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
888impl core::fmt::Debug for UART4 {
889    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
890        f.debug_struct("UART4").finish()
891    }
892}
893///Universal synchronous asynchronous receiver transmitter
894pub mod uart4;
895///Universal synchronous asynchronous receiver transmitter
896///
897///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#UART4)
898pub type UART7 = crate::Periph<uart4::RegisterBlock, 0x4000_7800>;
899impl core::fmt::Debug for UART7 {
900    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
901        f.debug_struct("UART7").finish()
902    }
903}
904///Universal synchronous asynchronous receiver transmitter
905pub use self::uart4 as uart7;
906///Universal synchronous asynchronous receiver transmitter
907///
908///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#UART4)
909pub type UART8 = crate::Periph<uart4::RegisterBlock, 0x4000_7c00>;
910impl core::fmt::Debug for UART8 {
911    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
912        f.debug_struct("UART8").finish()
913    }
914}
915///Universal synchronous asynchronous receiver transmitter
916pub use self::uart4 as uart8;
917///Digital-to-analog converter
918///
919///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DAC)
920pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
921impl core::fmt::Debug for DAC {
922    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
923        f.debug_struct("DAC").finish()
924    }
925}
926///Digital-to-analog converter
927pub mod dac;
928///Power control
929///
930///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#PWR)
931pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
932impl core::fmt::Debug for PWR {
933    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
934        f.debug_struct("PWR").finish()
935    }
936}
937///Power control
938pub mod pwr;
939///Independent watchdog
940///
941///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#IWDG)
942pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
943impl core::fmt::Debug for IWDG {
944    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
945        f.debug_struct("IWDG").finish()
946    }
947}
948///Independent watchdog
949pub mod iwdg;
950///Window watchdog
951///
952///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#WWDG)
953pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
954impl core::fmt::Debug for WWDG {
955    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
956        f.debug_struct("WWDG").finish()
957    }
958}
959///Window watchdog
960pub mod wwdg;
961///Real-time clock
962///
963///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#RTC)
964pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
965impl core::fmt::Debug for RTC {
966    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
967        f.debug_struct("RTC").finish()
968    }
969}
970///Real-time clock
971pub mod rtc;
972///Universal synchronous asynchronous receiver transmitter
973///
974///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#UART4)
975pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
976impl core::fmt::Debug for UART5 {
977    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
978        f.debug_struct("UART5").finish()
979    }
980}
981///Universal synchronous asynchronous receiver transmitter
982pub use self::uart4 as uart5;
983///Common ADC registers
984///
985///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#ADC_Common)
986pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
987impl core::fmt::Debug for ADC_COMMON {
988    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
989        f.debug_struct("ADC_COMMON").finish()
990    }
991}
992///Common ADC registers
993pub mod adc_common;
994///Advanced-timers
995///
996///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM1)
997pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
998impl core::fmt::Debug for TIM1 {
999    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1000        f.debug_struct("TIM1").finish()
1001    }
1002}
1003///Advanced-timers
1004pub mod tim1;
1005///Advanced-timers
1006///
1007///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM1)
1008pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
1009impl core::fmt::Debug for TIM8 {
1010    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1011        f.debug_struct("TIM8").finish()
1012    }
1013}
1014///Advanced-timers
1015pub use self::tim1 as tim8;
1016///General purpose timers
1017///
1018///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM2)
1019pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
1020impl core::fmt::Debug for TIM2 {
1021    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1022        f.debug_struct("TIM2").finish()
1023    }
1024}
1025///General purpose timers
1026pub mod tim2;
1027///General purpose timers
1028///
1029///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM3)
1030pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
1031impl core::fmt::Debug for TIM3 {
1032    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1033        f.debug_struct("TIM3").finish()
1034    }
1035}
1036///General purpose timers
1037pub mod tim3;
1038///General purpose timers
1039///
1040///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM3)
1041pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
1042impl core::fmt::Debug for TIM4 {
1043    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1044        f.debug_struct("TIM4").finish()
1045    }
1046}
1047///General purpose timers
1048pub use self::tim3 as tim4;
1049///General-purpose-timers
1050///
1051///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM5)
1052pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
1053impl core::fmt::Debug for TIM5 {
1054    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1055        f.debug_struct("TIM5").finish()
1056    }
1057}
1058///General-purpose-timers
1059pub mod tim5;
1060///General purpose timers
1061///
1062///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM9)
1063pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
1064impl core::fmt::Debug for TIM9 {
1065    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1066        f.debug_struct("TIM9").finish()
1067    }
1068}
1069///General purpose timers
1070pub mod tim9;
1071///General purpose timers
1072///
1073///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM9)
1074pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
1075impl core::fmt::Debug for TIM12 {
1076    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1077        f.debug_struct("TIM12").finish()
1078    }
1079}
1080///General purpose timers
1081pub use self::tim9 as tim12;
1082///General-purpose-timers
1083///
1084///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM10)
1085pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
1086impl core::fmt::Debug for TIM10 {
1087    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1088        f.debug_struct("TIM10").finish()
1089    }
1090}
1091///General-purpose-timers
1092pub mod tim10;
1093///General-purpose-timers
1094///
1095///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM10)
1096pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
1097impl core::fmt::Debug for TIM13 {
1098    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1099        f.debug_struct("TIM13").finish()
1100    }
1101}
1102///General-purpose-timers
1103pub use self::tim10 as tim13;
1104///General-purpose-timers
1105///
1106///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM10)
1107pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
1108impl core::fmt::Debug for TIM14 {
1109    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1110        f.debug_struct("TIM14").finish()
1111    }
1112}
1113///General-purpose-timers
1114pub use self::tim10 as tim14;
1115///General-purpose-timers
1116///
1117///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM11)
1118pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
1119impl core::fmt::Debug for TIM11 {
1120    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1121        f.debug_struct("TIM11").finish()
1122    }
1123}
1124///General-purpose-timers
1125pub mod tim11;
1126///Basic timers
1127///
1128///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM6)
1129pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
1130impl core::fmt::Debug for TIM6 {
1131    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1132        f.debug_struct("TIM6").finish()
1133    }
1134}
1135///Basic timers
1136pub mod tim6;
1137///Basic timers
1138///
1139///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#TIM6)
1140pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
1141impl core::fmt::Debug for TIM7 {
1142    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1143        f.debug_struct("TIM7").finish()
1144    }
1145}
1146///Basic timers
1147pub use self::tim6 as tim7;
1148///Ethernet: media access control (MAC)
1149///
1150///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#Ethernet_MAC)
1151pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
1152impl core::fmt::Debug for ETHERNET_MAC {
1153    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1154        f.debug_struct("ETHERNET_MAC").finish()
1155    }
1156}
1157///Ethernet: media access control (MAC)
1158pub mod ethernet_mac;
1159///Ethernet: MAC management counters
1160///
1161///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#Ethernet_MMC)
1162pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
1163impl core::fmt::Debug for ETHERNET_MMC {
1164    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1165        f.debug_struct("ETHERNET_MMC").finish()
1166    }
1167}
1168///Ethernet: MAC management counters
1169pub mod ethernet_mmc;
1170///Ethernet: Precision time protocol
1171///
1172///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#Ethernet_PTP)
1173pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
1174impl core::fmt::Debug for ETHERNET_PTP {
1175    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1176        f.debug_struct("ETHERNET_PTP").finish()
1177    }
1178}
1179///Ethernet: Precision time protocol
1180pub mod ethernet_ptp;
1181///Ethernet: DMA controller operation
1182///
1183///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#Ethernet_DMA)
1184pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
1185impl core::fmt::Debug for ETHERNET_DMA {
1186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1187        f.debug_struct("ETHERNET_DMA").finish()
1188    }
1189}
1190///Ethernet: DMA controller operation
1191pub mod ethernet_dma;
1192///Cryptographic processor
1193///
1194///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#CRC)
1195pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
1196impl core::fmt::Debug for CRC {
1197    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1198        f.debug_struct("CRC").finish()
1199    }
1200}
1201///Cryptographic processor
1202pub mod crc;
1203///USB on the go full speed
1204///
1205///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_FS_GLOBAL)
1206pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
1207impl core::fmt::Debug for OTG_FS_GLOBAL {
1208    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1209        f.debug_struct("OTG_FS_GLOBAL").finish()
1210    }
1211}
1212///USB on the go full speed
1213pub mod otg_fs_global;
1214///USB on the go full speed
1215///
1216///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_FS_HOST)
1217pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
1218impl core::fmt::Debug for OTG_FS_HOST {
1219    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1220        f.debug_struct("OTG_FS_HOST").finish()
1221    }
1222}
1223///USB on the go full speed
1224pub mod otg_fs_host;
1225///USB on the go full speed
1226///
1227///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_FS_DEVICE)
1228pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
1229impl core::fmt::Debug for OTG_FS_DEVICE {
1230    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1231        f.debug_struct("OTG_FS_DEVICE").finish()
1232    }
1233}
1234///USB on the go full speed
1235pub mod otg_fs_device;
1236///USB on the go full speed
1237///
1238///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_FS_PWRCLK)
1239pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
1240impl core::fmt::Debug for OTG_FS_PWRCLK {
1241    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1242        f.debug_struct("OTG_FS_PWRCLK").finish()
1243    }
1244}
1245///USB on the go full speed
1246pub mod otg_fs_pwrclk;
1247///Controller area network
1248///
1249///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#CAN1)
1250pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
1251impl core::fmt::Debug for CAN1 {
1252    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1253        f.debug_struct("CAN1").finish()
1254    }
1255}
1256///Controller area network
1257pub mod can1;
1258///Controller area network
1259///
1260///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#CAN1)
1261pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
1262impl core::fmt::Debug for CAN2 {
1263    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1264        f.debug_struct("CAN2").finish()
1265    }
1266}
1267///Controller area network
1268pub use self::can1 as can2;
1269///FLASH
1270///
1271///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#FLASH)
1272pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
1273impl core::fmt::Debug for FLASH {
1274    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1275        f.debug_struct("FLASH").finish()
1276    }
1277}
1278///FLASH
1279pub mod flash;
1280///External interrupt/event controller
1281///
1282///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#EXTI)
1283pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
1284impl core::fmt::Debug for EXTI {
1285    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1286        f.debug_struct("EXTI").finish()
1287    }
1288}
1289///External interrupt/event controller
1290pub mod exti;
1291///USB on the go high speed
1292///
1293///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_HS_GLOBAL)
1294pub type OTG_HS_GLOBAL = crate::Periph<otg_hs_global::RegisterBlock, 0x4004_0000>;
1295impl core::fmt::Debug for OTG_HS_GLOBAL {
1296    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1297        f.debug_struct("OTG_HS_GLOBAL").finish()
1298    }
1299}
1300///USB on the go high speed
1301pub mod otg_hs_global;
1302///USB on the go high speed
1303///
1304///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_HS_HOST)
1305pub type OTG_HS_HOST = crate::Periph<otg_hs_host::RegisterBlock, 0x4004_0400>;
1306impl core::fmt::Debug for OTG_HS_HOST {
1307    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1308        f.debug_struct("OTG_HS_HOST").finish()
1309    }
1310}
1311///USB on the go high speed
1312pub mod otg_hs_host;
1313///USB on the go high speed
1314///
1315///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_HS_DEVICE)
1316pub type OTG_HS_DEVICE = crate::Periph<otg_hs_device::RegisterBlock, 0x4004_0800>;
1317impl core::fmt::Debug for OTG_HS_DEVICE {
1318    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1319        f.debug_struct("OTG_HS_DEVICE").finish()
1320    }
1321}
1322///USB on the go high speed
1323pub mod otg_hs_device;
1324///USB on the go high speed
1325///
1326///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#OTG_HS_PWRCLK)
1327pub type OTG_HS_PWRCLK = crate::Periph<otg_hs_pwrclk::RegisterBlock, 0x4004_0e00>;
1328impl core::fmt::Debug for OTG_HS_PWRCLK {
1329    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1330        f.debug_struct("OTG_HS_PWRCLK").finish()
1331    }
1332}
1333///USB on the go high speed
1334pub mod otg_hs_pwrclk;
1335///LCD-TFT Controller
1336///
1337///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#LTDC)
1338pub type LTDC = crate::Periph<ltdc::RegisterBlock, 0x4001_6800>;
1339impl core::fmt::Debug for LTDC {
1340    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1341        f.debug_struct("LTDC").finish()
1342    }
1343}
1344///LCD-TFT Controller
1345pub mod ltdc;
1346///Serial audio interface
1347///
1348///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#SAI)
1349pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5800>;
1350impl core::fmt::Debug for SAI {
1351    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1352        f.debug_struct("SAI").finish()
1353    }
1354}
1355///Serial audio interface
1356pub mod sai;
1357///DMA2D controller
1358///
1359///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DMA2D)
1360pub type DMA2D = crate::Periph<dma2d::RegisterBlock, 0x4002_b000>;
1361impl core::fmt::Debug for DMA2D {
1362    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1363        f.debug_struct("DMA2D").finish()
1364    }
1365}
1366///DMA2D controller
1367pub mod dma2d;
1368///Inter-integrated circuit
1369///
1370///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#I2C1)
1371pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
1372impl core::fmt::Debug for I2C1 {
1373    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1374        f.debug_struct("I2C1").finish()
1375    }
1376}
1377///Inter-integrated circuit
1378pub mod i2c1;
1379///Inter-integrated circuit
1380///
1381///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#I2C1)
1382pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
1383impl core::fmt::Debug for I2C3 {
1384    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1385        f.debug_struct("I2C3").finish()
1386    }
1387}
1388///Inter-integrated circuit
1389pub use self::i2c1 as i2c3;
1390///Inter-integrated circuit
1391///
1392///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#I2C1)
1393pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
1394impl core::fmt::Debug for I2C2 {
1395    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1396        f.debug_struct("I2C2").finish()
1397    }
1398}
1399///Inter-integrated circuit
1400pub use self::i2c1 as i2c2;
1401///DSI Host
1402///
1403///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI)
1404pub type DSI = crate::Periph<dsi::RegisterBlock, 0x4001_6c00>;
1405impl core::fmt::Debug for DSI {
1406    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1407        f.debug_struct("DSI").finish()
1408    }
1409}
1410///DSI Host
1411pub mod dsi;
1412///QuadSPI interface
1413///
1414///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#QUADSPI)
1415pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
1416impl core::fmt::Debug for QUADSPI {
1417    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1418        f.debug_struct("QUADSPI").finish()
1419    }
1420}
1421///QuadSPI interface
1422pub mod quadspi;
1423#[no_mangle]
1424static mut DEVICE_PERIPHERALS: bool = false;
1425/// All the peripherals.
1426#[allow(non_snake_case)]
1427pub struct Peripherals {
1428    ///RNG
1429    pub RNG: RNG,
1430    ///HASH
1431    pub HASH: HASH,
1432    ///CRYP
1433    pub CRYP: CRYP,
1434    ///DCMI
1435    pub DCMI: DCMI,
1436    ///FMC
1437    pub FMC: FMC,
1438    ///DBGMCU
1439    pub DBGMCU: DBGMCU,
1440    ///DMA2
1441    pub DMA2: DMA2,
1442    ///DMA1
1443    pub DMA1: DMA1,
1444    ///RCC
1445    pub RCC: RCC,
1446    ///GPIOK
1447    pub GPIOK: GPIOK,
1448    ///GPIOJ
1449    pub GPIOJ: GPIOJ,
1450    ///GPIOI
1451    pub GPIOI: GPIOI,
1452    ///GPIOH
1453    pub GPIOH: GPIOH,
1454    ///GPIOG
1455    pub GPIOG: GPIOG,
1456    ///GPIOF
1457    pub GPIOF: GPIOF,
1458    ///GPIOE
1459    pub GPIOE: GPIOE,
1460    ///GPIOD
1461    pub GPIOD: GPIOD,
1462    ///GPIOC
1463    pub GPIOC: GPIOC,
1464    ///GPIOB
1465    pub GPIOB: GPIOB,
1466    ///GPIOA
1467    pub GPIOA: GPIOA,
1468    ///SYSCFG
1469    pub SYSCFG: SYSCFG,
1470    ///SPI1
1471    pub SPI1: SPI1,
1472    ///SPI2
1473    pub SPI2: SPI2,
1474    ///SPI3
1475    pub SPI3: SPI3,
1476    ///I2S2ext
1477    pub I2S2EXT: I2S2EXT,
1478    ///I2S3ext
1479    pub I2S3EXT: I2S3EXT,
1480    ///SPI4
1481    pub SPI4: SPI4,
1482    ///SPI5
1483    pub SPI5: SPI5,
1484    ///SPI6
1485    pub SPI6: SPI6,
1486    ///SDIO
1487    pub SDIO: SDIO,
1488    ///ADC1
1489    pub ADC1: ADC1,
1490    ///ADC2
1491    pub ADC2: ADC2,
1492    ///ADC3
1493    pub ADC3: ADC3,
1494    ///USART1
1495    pub USART1: USART1,
1496    ///USART6
1497    pub USART6: USART6,
1498    ///USART2
1499    pub USART2: USART2,
1500    ///USART3
1501    pub USART3: USART3,
1502    ///UART4
1503    pub UART4: UART4,
1504    ///UART7
1505    pub UART7: UART7,
1506    ///UART8
1507    pub UART8: UART8,
1508    ///DAC
1509    pub DAC: DAC,
1510    ///PWR
1511    pub PWR: PWR,
1512    ///IWDG
1513    pub IWDG: IWDG,
1514    ///WWDG
1515    pub WWDG: WWDG,
1516    ///RTC
1517    pub RTC: RTC,
1518    ///UART5
1519    pub UART5: UART5,
1520    ///ADC_Common
1521    pub ADC_COMMON: ADC_COMMON,
1522    ///TIM1
1523    pub TIM1: TIM1,
1524    ///TIM8
1525    pub TIM8: TIM8,
1526    ///TIM2
1527    pub TIM2: TIM2,
1528    ///TIM3
1529    pub TIM3: TIM3,
1530    ///TIM4
1531    pub TIM4: TIM4,
1532    ///TIM5
1533    pub TIM5: TIM5,
1534    ///TIM9
1535    pub TIM9: TIM9,
1536    ///TIM12
1537    pub TIM12: TIM12,
1538    ///TIM10
1539    pub TIM10: TIM10,
1540    ///TIM13
1541    pub TIM13: TIM13,
1542    ///TIM14
1543    pub TIM14: TIM14,
1544    ///TIM11
1545    pub TIM11: TIM11,
1546    ///TIM6
1547    pub TIM6: TIM6,
1548    ///TIM7
1549    pub TIM7: TIM7,
1550    ///Ethernet_MAC
1551    pub ETHERNET_MAC: ETHERNET_MAC,
1552    ///Ethernet_MMC
1553    pub ETHERNET_MMC: ETHERNET_MMC,
1554    ///Ethernet_PTP
1555    pub ETHERNET_PTP: ETHERNET_PTP,
1556    ///Ethernet_DMA
1557    pub ETHERNET_DMA: ETHERNET_DMA,
1558    ///CRC
1559    pub CRC: CRC,
1560    ///OTG_FS_GLOBAL
1561    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1562    ///OTG_FS_HOST
1563    pub OTG_FS_HOST: OTG_FS_HOST,
1564    ///OTG_FS_DEVICE
1565    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1566    ///OTG_FS_PWRCLK
1567    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1568    ///CAN1
1569    pub CAN1: CAN1,
1570    ///CAN2
1571    pub CAN2: CAN2,
1572    ///FLASH
1573    pub FLASH: FLASH,
1574    ///EXTI
1575    pub EXTI: EXTI,
1576    ///OTG_HS_GLOBAL
1577    pub OTG_HS_GLOBAL: OTG_HS_GLOBAL,
1578    ///OTG_HS_HOST
1579    pub OTG_HS_HOST: OTG_HS_HOST,
1580    ///OTG_HS_DEVICE
1581    pub OTG_HS_DEVICE: OTG_HS_DEVICE,
1582    ///OTG_HS_PWRCLK
1583    pub OTG_HS_PWRCLK: OTG_HS_PWRCLK,
1584    ///LTDC
1585    pub LTDC: LTDC,
1586    ///SAI
1587    pub SAI: SAI,
1588    ///DMA2D
1589    pub DMA2D: DMA2D,
1590    ///I2C1
1591    pub I2C1: I2C1,
1592    ///I2C3
1593    pub I2C3: I2C3,
1594    ///I2C2
1595    pub I2C2: I2C2,
1596    ///DSI
1597    pub DSI: DSI,
1598    ///QUADSPI
1599    pub QUADSPI: QUADSPI,
1600}
1601impl Peripherals {
1602    /// Returns all the peripherals *once*.
1603    #[cfg(feature = "critical-section")]
1604    #[inline]
1605    pub fn take() -> Option<Self> {
1606        critical_section::with(|_| {
1607            if unsafe { DEVICE_PERIPHERALS } {
1608                return None;
1609            }
1610            Some(unsafe { Peripherals::steal() })
1611        })
1612    }
1613    /// Unchecked version of `Peripherals::take`.
1614    ///
1615    /// # Safety
1616    ///
1617    /// Each of the returned peripherals must be used at most once.
1618    #[inline]
1619    pub unsafe fn steal() -> Self {
1620        DEVICE_PERIPHERALS = true;
1621        Peripherals {
1622            RNG: RNG::steal(),
1623            HASH: HASH::steal(),
1624            CRYP: CRYP::steal(),
1625            DCMI: DCMI::steal(),
1626            FMC: FMC::steal(),
1627            DBGMCU: DBGMCU::steal(),
1628            DMA2: DMA2::steal(),
1629            DMA1: DMA1::steal(),
1630            RCC: RCC::steal(),
1631            GPIOK: GPIOK::steal(),
1632            GPIOJ: GPIOJ::steal(),
1633            GPIOI: GPIOI::steal(),
1634            GPIOH: GPIOH::steal(),
1635            GPIOG: GPIOG::steal(),
1636            GPIOF: GPIOF::steal(),
1637            GPIOE: GPIOE::steal(),
1638            GPIOD: GPIOD::steal(),
1639            GPIOC: GPIOC::steal(),
1640            GPIOB: GPIOB::steal(),
1641            GPIOA: GPIOA::steal(),
1642            SYSCFG: SYSCFG::steal(),
1643            SPI1: SPI1::steal(),
1644            SPI2: SPI2::steal(),
1645            SPI3: SPI3::steal(),
1646            I2S2EXT: I2S2EXT::steal(),
1647            I2S3EXT: I2S3EXT::steal(),
1648            SPI4: SPI4::steal(),
1649            SPI5: SPI5::steal(),
1650            SPI6: SPI6::steal(),
1651            SDIO: SDIO::steal(),
1652            ADC1: ADC1::steal(),
1653            ADC2: ADC2::steal(),
1654            ADC3: ADC3::steal(),
1655            USART1: USART1::steal(),
1656            USART6: USART6::steal(),
1657            USART2: USART2::steal(),
1658            USART3: USART3::steal(),
1659            UART4: UART4::steal(),
1660            UART7: UART7::steal(),
1661            UART8: UART8::steal(),
1662            DAC: DAC::steal(),
1663            PWR: PWR::steal(),
1664            IWDG: IWDG::steal(),
1665            WWDG: WWDG::steal(),
1666            RTC: RTC::steal(),
1667            UART5: UART5::steal(),
1668            ADC_COMMON: ADC_COMMON::steal(),
1669            TIM1: TIM1::steal(),
1670            TIM8: TIM8::steal(),
1671            TIM2: TIM2::steal(),
1672            TIM3: TIM3::steal(),
1673            TIM4: TIM4::steal(),
1674            TIM5: TIM5::steal(),
1675            TIM9: TIM9::steal(),
1676            TIM12: TIM12::steal(),
1677            TIM10: TIM10::steal(),
1678            TIM13: TIM13::steal(),
1679            TIM14: TIM14::steal(),
1680            TIM11: TIM11::steal(),
1681            TIM6: TIM6::steal(),
1682            TIM7: TIM7::steal(),
1683            ETHERNET_MAC: ETHERNET_MAC::steal(),
1684            ETHERNET_MMC: ETHERNET_MMC::steal(),
1685            ETHERNET_PTP: ETHERNET_PTP::steal(),
1686            ETHERNET_DMA: ETHERNET_DMA::steal(),
1687            CRC: CRC::steal(),
1688            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1689            OTG_FS_HOST: OTG_FS_HOST::steal(),
1690            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1691            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1692            CAN1: CAN1::steal(),
1693            CAN2: CAN2::steal(),
1694            FLASH: FLASH::steal(),
1695            EXTI: EXTI::steal(),
1696            OTG_HS_GLOBAL: OTG_HS_GLOBAL::steal(),
1697            OTG_HS_HOST: OTG_HS_HOST::steal(),
1698            OTG_HS_DEVICE: OTG_HS_DEVICE::steal(),
1699            OTG_HS_PWRCLK: OTG_HS_PWRCLK::steal(),
1700            LTDC: LTDC::steal(),
1701            SAI: SAI::steal(),
1702            DMA2D: DMA2D::steal(),
1703            I2C1: I2C1::steal(),
1704            I2C3: I2C3::steal(),
1705            I2C2: I2C2::steal(),
1706            DSI: DSI::steal(),
1707            QUADSPI: QUADSPI::steal(),
1708        }
1709    }
1710}
stm32f4_staging/stm32f469/mod.rs

stm32f4_staging/stm32f469/
mod.rs
