stm32f4_staging/stm32f469/dsi/wpcr3.rs
1///Register `WPCR3` reader
2pub type R = crate::R<WPCR3rs>;
3///Register `WPCR3` writer
4pub type W = crate::W<WPCR3rs>;
5///Field `THSZERO` reader - t<sub>HS-ZERO</sub> This field defines the t<sub>HS-ZERO</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. THSZERO = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSZEROEN bit of the DSI_WPCR1 is reset is 175, (175ns).
6pub type THSZERO_R = crate::FieldReader;
7///Field `THSZERO` writer - t<sub>HS-ZERO</sub> This field defines the t<sub>HS-ZERO</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. THSZERO = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSZEROEN bit of the DSI_WPCR1 is reset is 175, (175ns).
8pub type THSZERO_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9///Field `TLPXD` reader - t<sub>LPX</sub> for data lanes This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. TLPXD = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXDEN bit of the DSI_WPCR1 is reset is 100 (50ns).
10pub type TLPXD_R = crate::FieldReader;
11///Field `TLPXD` writer - t<sub>LPX</sub> for data lanes This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. TLPXD = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXDEN bit of the DSI_WPCR1 is reset is 100 (50ns).
12pub type TLPXD_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13///Field `THSEXIT` reader - t<sub>HSEXIT</sub> This field defines the t<sub>HS-EXHigh-SpeedIT</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. THSEXIT = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSEXITEN bit of the DSI_WPCR1 is reset is 100 (100ns).
14pub type THSEXIT_R = crate::FieldReader;
15///Field `THSEXIT` writer - t<sub>HSEXIT</sub> This field defines the t<sub>HS-EXHigh-SpeedIT</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. THSEXIT = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSEXITEN bit of the DSI_WPCR1 is reset is 100 (100ns).
16pub type THSEXIT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17///Field `TLPXC` reader - t<sub>LPXC</sub> for clock lane This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. TLPXC = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXCEN bit of the DSI_WPCR1 is reset is 100 (50ns).
18pub type TLPXC_R = crate::FieldReader;
19///Field `TLPXC` writer - t<sub>LPXC</sub> for clock lane This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. TLPXC = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXCEN bit of the DSI_WPCR1 is reset is 100 (50ns).
20pub type TLPXC_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22 ///Bits 0:7 - t<sub>HS-ZERO</sub> This field defines the t<sub>HS-ZERO</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. THSZERO = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSZEROEN bit of the DSI_WPCR1 is reset is 175, (175ns).
23 #[inline(always)]
24 pub fn thszero(&self) -> THSZERO_R {
25 THSZERO_R::new((self.bits & 0xff) as u8)
26 }
27 ///Bits 8:15 - t<sub>LPX</sub> for data lanes This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. TLPXD = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXDEN bit of the DSI_WPCR1 is reset is 100 (50ns).
28 #[inline(always)]
29 pub fn tlpxd(&self) -> TLPXD_R {
30 TLPXD_R::new(((self.bits >> 8) & 0xff) as u8)
31 }
32 ///Bits 16:23 - t<sub>HSEXIT</sub> This field defines the t<sub>HS-EXHigh-SpeedIT</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. THSEXIT = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSEXITEN bit of the DSI_WPCR1 is reset is 100 (100ns).
33 #[inline(always)]
34 pub fn thsexit(&self) -> THSEXIT_R {
35 THSEXIT_R::new(((self.bits >> 16) & 0xff) as u8)
36 }
37 ///Bits 24:31 - t<sub>LPXC</sub> for clock lane This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. TLPXC = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXCEN bit of the DSI_WPCR1 is reset is 100 (50ns).
38 #[inline(always)]
39 pub fn tlpxc(&self) -> TLPXC_R {
40 TLPXC_R::new(((self.bits >> 24) & 0xff) as u8)
41 }
42}
43impl core::fmt::Debug for R {
44 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
45 f.debug_struct("WPCR3")
46 .field("thszero", &self.thszero())
47 .field("tlpxd", &self.tlpxd())
48 .field("thsexit", &self.thsexit())
49 .field("tlpxc", &self.tlpxc())
50 .finish()
51 }
52}
53impl W {
54 ///Bits 0:7 - t<sub>HS-ZERO</sub> This field defines the t<sub>HS-ZERO</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSZEROEN bit of the DSI_WPCR1 is set. THSZERO = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSZEROEN bit of the DSI_WPCR1 is reset is 175, (175ns).
55 #[inline(always)]
56 pub fn thszero(&mut self) -> THSZERO_W<WPCR3rs> {
57 THSZERO_W::new(self, 0)
58 }
59 ///Bits 8:15 - t<sub>LPX</sub> for data lanes This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the data lanes. This value is used by the D-PHY when the TLPXDEN bit of the DSI_WPCR1 is set. TLPXD = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXDEN bit of the DSI_WPCR1 is reset is 100 (50ns).
60 #[inline(always)]
61 pub fn tlpxd(&mut self) -> TLPXD_W<WPCR3rs> {
62 TLPXD_W::new(self, 8)
63 }
64 ///Bits 16:23 - t<sub>HSEXIT</sub> This field defines the t<sub>HS-EXHigh-SpeedIT</sub> has specified in the MIPI<sup></sup> D-PHY specification. This value is used by the D-PHY when the THSEXITEN bit of the DSI_WPCR1 is set. THSEXIT = t<sub>HS-ZERO</sub> expressed in ns.The default value used by the D-PHY when THSEXITEN bit of the DSI_WPCR1 is reset is 100 (100ns).
65 #[inline(always)]
66 pub fn thsexit(&mut self) -> THSEXIT_W<WPCR3rs> {
67 THSEXIT_W::new(self, 16)
68 }
69 ///Bits 24:31 - t<sub>LPXC</sub> for clock lane This field defines the t<sub>LPX</sub> has specified in the MIPI<sup></sup> D-PHY specification for the clock lane. This value is used by the D-PHY when the TLPXCEN bit of the DSI_WPCR1 is set. TLPXC = 2 x t<sub>LPX</sub> expressed in ns.The default value used by the D-PHY when TLPXCEN bit of the DSI_WPCR1 is reset is 100 (50ns).
70 #[inline(always)]
71 pub fn tlpxc(&mut self) -> TLPXC_W<WPCR3rs> {
72 TLPXC_W::new(self, 24)
73 }
74}
75/**DSI Wrapper PHY configuration register 3
76
77You can [`read`](crate::Reg::read) this register and get [`wpcr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wpcr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
78
79See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI:WPCR3)*/
80pub struct WPCR3rs;
81impl crate::RegisterSpec for WPCR3rs {
82 type Ux = u32;
83}
84///`read()` method returns [`wpcr3::R`](R) reader structure
85impl crate::Readable for WPCR3rs {}
86///`write(|w| ..)` method takes [`wpcr3::W`](W) writer structure
87impl crate::Writable for WPCR3rs {
88 type Safety = crate::Unsafe;
89}
90///`reset()` method sets WPCR3 to value 0
91impl crate::Resettable for WPCR3rs {}