stm32f4_staging/stm32f469/dsi/
wcfgr.rs

1///Register `WCFGR` reader
2pub type R = crate::R<WCFGRrs>;
3///Register `WCFGR` writer
4pub type W = crate::W<WCFGRrs>;
5/**DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DSIM {
11    ///0: Video mode
12    B0x0 = 0,
13    ///1: Adapted command mode
14    B0x1 = 1,
15}
16impl From<DSIM> for bool {
17    #[inline(always)]
18    fn from(variant: DSIM) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DSIM` reader - DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
23pub type DSIM_R = crate::BitReader<DSIM>;
24impl DSIM_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DSIM {
28        match self.bits {
29            false => DSIM::B0x0,
30            true => DSIM::B0x1,
31        }
32    }
33    ///Video mode
34    #[inline(always)]
35    pub fn is_b_0x0(&self) -> bool {
36        *self == DSIM::B0x0
37    }
38    ///Adapted command mode
39    #[inline(always)]
40    pub fn is_b_0x1(&self) -> bool {
41        *self == DSIM::B0x1
42    }
43}
44///Field `DSIM` writer - DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
45pub type DSIM_W<'a, REG> = crate::BitWriter<'a, REG, DSIM>;
46impl<'a, REG> DSIM_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Video mode
51    #[inline(always)]
52    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
53        self.variant(DSIM::B0x0)
54    }
55    ///Adapted command mode
56    #[inline(always)]
57    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
58        self.variant(DSIM::B0x1)
59    }
60}
61/**Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66#[repr(u8)]
67pub enum COLMUX {
68    ///0: 16-bit configuration 1
69    B0x0 = 0,
70    ///1: 16-bit configuration 2
71    B0x1 = 1,
72    ///2: 16-bit configuration 3
73    B0x2 = 2,
74    ///3: 18-bit configuration 1
75    B0x3 = 3,
76    ///4: 18-bit configuration 2
77    B0x4 = 4,
78    ///5: 24-bit
79    B0x5 = 5,
80}
81impl From<COLMUX> for u8 {
82    #[inline(always)]
83    fn from(variant: COLMUX) -> Self {
84        variant as _
85    }
86}
87impl crate::FieldSpec for COLMUX {
88    type Ux = u8;
89}
90impl crate::IsEnum for COLMUX {}
91///Field `COLMUX` reader - Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
92pub type COLMUX_R = crate::FieldReader<COLMUX>;
93impl COLMUX_R {
94    ///Get enumerated values variant
95    #[inline(always)]
96    pub const fn variant(&self) -> Option<COLMUX> {
97        match self.bits {
98            0 => Some(COLMUX::B0x0),
99            1 => Some(COLMUX::B0x1),
100            2 => Some(COLMUX::B0x2),
101            3 => Some(COLMUX::B0x3),
102            4 => Some(COLMUX::B0x4),
103            5 => Some(COLMUX::B0x5),
104            _ => None,
105        }
106    }
107    ///16-bit configuration 1
108    #[inline(always)]
109    pub fn is_b_0x0(&self) -> bool {
110        *self == COLMUX::B0x0
111    }
112    ///16-bit configuration 2
113    #[inline(always)]
114    pub fn is_b_0x1(&self) -> bool {
115        *self == COLMUX::B0x1
116    }
117    ///16-bit configuration 3
118    #[inline(always)]
119    pub fn is_b_0x2(&self) -> bool {
120        *self == COLMUX::B0x2
121    }
122    ///18-bit configuration 1
123    #[inline(always)]
124    pub fn is_b_0x3(&self) -> bool {
125        *self == COLMUX::B0x3
126    }
127    ///18-bit configuration 2
128    #[inline(always)]
129    pub fn is_b_0x4(&self) -> bool {
130        *self == COLMUX::B0x4
131    }
132    ///24-bit
133    #[inline(always)]
134    pub fn is_b_0x5(&self) -> bool {
135        *self == COLMUX::B0x5
136    }
137}
138///Field `COLMUX` writer - Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
139pub type COLMUX_W<'a, REG> = crate::FieldWriter<'a, REG, 3, COLMUX>;
140impl<'a, REG> COLMUX_W<'a, REG>
141where
142    REG: crate::Writable + crate::RegisterSpec,
143    REG::Ux: From<u8>,
144{
145    ///16-bit configuration 1
146    #[inline(always)]
147    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
148        self.variant(COLMUX::B0x0)
149    }
150    ///16-bit configuration 2
151    #[inline(always)]
152    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
153        self.variant(COLMUX::B0x1)
154    }
155    ///16-bit configuration 3
156    #[inline(always)]
157    pub fn b_0x2(self) -> &'a mut crate::W<REG> {
158        self.variant(COLMUX::B0x2)
159    }
160    ///18-bit configuration 1
161    #[inline(always)]
162    pub fn b_0x3(self) -> &'a mut crate::W<REG> {
163        self.variant(COLMUX::B0x3)
164    }
165    ///18-bit configuration 2
166    #[inline(always)]
167    pub fn b_0x4(self) -> &'a mut crate::W<REG> {
168        self.variant(COLMUX::B0x4)
169    }
170    ///24-bit
171    #[inline(always)]
172    pub fn b_0x5(self) -> &'a mut crate::W<REG> {
173        self.variant(COLMUX::B0x5)
174    }
175}
176/**TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
177
178Value on reset: 0*/
179#[cfg_attr(feature = "defmt", derive(defmt::Format))]
180#[derive(Clone, Copy, Debug, PartialEq, Eq)]
181pub enum TESRC {
182    ///0: DSI Link
183    B0x0 = 0,
184    ///1: External pin
185    B0x1 = 1,
186}
187impl From<TESRC> for bool {
188    #[inline(always)]
189    fn from(variant: TESRC) -> Self {
190        variant as u8 != 0
191    }
192}
193///Field `TESRC` reader - TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
194pub type TESRC_R = crate::BitReader<TESRC>;
195impl TESRC_R {
196    ///Get enumerated values variant
197    #[inline(always)]
198    pub const fn variant(&self) -> TESRC {
199        match self.bits {
200            false => TESRC::B0x0,
201            true => TESRC::B0x1,
202        }
203    }
204    ///DSI Link
205    #[inline(always)]
206    pub fn is_b_0x0(&self) -> bool {
207        *self == TESRC::B0x0
208    }
209    ///External pin
210    #[inline(always)]
211    pub fn is_b_0x1(&self) -> bool {
212        *self == TESRC::B0x1
213    }
214}
215///Field `TESRC` writer - TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
216pub type TESRC_W<'a, REG> = crate::BitWriter<'a, REG, TESRC>;
217impl<'a, REG> TESRC_W<'a, REG>
218where
219    REG: crate::Writable + crate::RegisterSpec,
220{
221    ///DSI Link
222    #[inline(always)]
223    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
224        self.variant(TESRC::B0x0)
225    }
226    ///External pin
227    #[inline(always)]
228    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
229        self.variant(TESRC::B0x1)
230    }
231}
232/**TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
233
234Value on reset: 0*/
235#[cfg_attr(feature = "defmt", derive(defmt::Format))]
236#[derive(Clone, Copy, Debug, PartialEq, Eq)]
237pub enum TEPOL {
238    ///0: rising edge.
239    B0x0 = 0,
240    ///1: falling edge.
241    B0x1 = 1,
242}
243impl From<TEPOL> for bool {
244    #[inline(always)]
245    fn from(variant: TEPOL) -> Self {
246        variant as u8 != 0
247    }
248}
249///Field `TEPOL` reader - TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
250pub type TEPOL_R = crate::BitReader<TEPOL>;
251impl TEPOL_R {
252    ///Get enumerated values variant
253    #[inline(always)]
254    pub const fn variant(&self) -> TEPOL {
255        match self.bits {
256            false => TEPOL::B0x0,
257            true => TEPOL::B0x1,
258        }
259    }
260    ///rising edge.
261    #[inline(always)]
262    pub fn is_b_0x0(&self) -> bool {
263        *self == TEPOL::B0x0
264    }
265    ///falling edge.
266    #[inline(always)]
267    pub fn is_b_0x1(&self) -> bool {
268        *self == TEPOL::B0x1
269    }
270}
271///Field `TEPOL` writer - TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
272pub type TEPOL_W<'a, REG> = crate::BitWriter<'a, REG, TEPOL>;
273impl<'a, REG> TEPOL_W<'a, REG>
274where
275    REG: crate::Writable + crate::RegisterSpec,
276{
277    ///rising edge.
278    #[inline(always)]
279    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
280        self.variant(TEPOL::B0x0)
281    }
282    ///falling edge.
283    #[inline(always)]
284    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
285        self.variant(TEPOL::B0x1)
286    }
287}
288/**Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
289
290Value on reset: 0*/
291#[cfg_attr(feature = "defmt", derive(defmt::Format))]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum AR {
294    ///0: automatic refresh mode disabled
295    B0x0 = 0,
296    ///1: automatic refresh mode enabled
297    B0x1 = 1,
298}
299impl From<AR> for bool {
300    #[inline(always)]
301    fn from(variant: AR) -> Self {
302        variant as u8 != 0
303    }
304}
305///Field `AR` reader - Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
306pub type AR_R = crate::BitReader<AR>;
307impl AR_R {
308    ///Get enumerated values variant
309    #[inline(always)]
310    pub const fn variant(&self) -> AR {
311        match self.bits {
312            false => AR::B0x0,
313            true => AR::B0x1,
314        }
315    }
316    ///automatic refresh mode disabled
317    #[inline(always)]
318    pub fn is_b_0x0(&self) -> bool {
319        *self == AR::B0x0
320    }
321    ///automatic refresh mode enabled
322    #[inline(always)]
323    pub fn is_b_0x1(&self) -> bool {
324        *self == AR::B0x1
325    }
326}
327///Field `AR` writer - Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
328pub type AR_W<'a, REG> = crate::BitWriter<'a, REG, AR>;
329impl<'a, REG> AR_W<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    ///automatic refresh mode disabled
334    #[inline(always)]
335    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
336        self.variant(AR::B0x0)
337    }
338    ///automatic refresh mode enabled
339    #[inline(always)]
340    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
341        self.variant(AR::B0x1)
342    }
343}
344/**VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
345
346Value on reset: 0*/
347#[cfg_attr(feature = "defmt", derive(defmt::Format))]
348#[derive(Clone, Copy, Debug, PartialEq, Eq)]
349pub enum VSPOL {
350    ///0: LTDC halted on a falling edge
351    B0x0 = 0,
352    ///1: LTDC halted on a rising edge
353    B0x1 = 1,
354}
355impl From<VSPOL> for bool {
356    #[inline(always)]
357    fn from(variant: VSPOL) -> Self {
358        variant as u8 != 0
359    }
360}
361///Field `VSPOL` reader - VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
362pub type VSPOL_R = crate::BitReader<VSPOL>;
363impl VSPOL_R {
364    ///Get enumerated values variant
365    #[inline(always)]
366    pub const fn variant(&self) -> VSPOL {
367        match self.bits {
368            false => VSPOL::B0x0,
369            true => VSPOL::B0x1,
370        }
371    }
372    ///LTDC halted on a falling edge
373    #[inline(always)]
374    pub fn is_b_0x0(&self) -> bool {
375        *self == VSPOL::B0x0
376    }
377    ///LTDC halted on a rising edge
378    #[inline(always)]
379    pub fn is_b_0x1(&self) -> bool {
380        *self == VSPOL::B0x1
381    }
382}
383///Field `VSPOL` writer - VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
384pub type VSPOL_W<'a, REG> = crate::BitWriter<'a, REG, VSPOL>;
385impl<'a, REG> VSPOL_W<'a, REG>
386where
387    REG: crate::Writable + crate::RegisterSpec,
388{
389    ///LTDC halted on a falling edge
390    #[inline(always)]
391    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
392        self.variant(VSPOL::B0x0)
393    }
394    ///LTDC halted on a rising edge
395    #[inline(always)]
396    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
397        self.variant(VSPOL::B0x1)
398    }
399}
400impl R {
401    ///Bit 0 - DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
402    #[inline(always)]
403    pub fn dsim(&self) -> DSIM_R {
404        DSIM_R::new((self.bits & 1) != 0)
405    }
406    ///Bits 1:3 - Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
407    #[inline(always)]
408    pub fn colmux(&self) -> COLMUX_R {
409        COLMUX_R::new(((self.bits >> 1) & 7) as u8)
410    }
411    ///Bit 4 - TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
412    #[inline(always)]
413    pub fn tesrc(&self) -> TESRC_R {
414        TESRC_R::new(((self.bits >> 4) & 1) != 0)
415    }
416    ///Bit 5 - TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
417    #[inline(always)]
418    pub fn tepol(&self) -> TEPOL_R {
419        TEPOL_R::new(((self.bits >> 5) & 1) != 0)
420    }
421    ///Bit 6 - Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
422    #[inline(always)]
423    pub fn ar(&self) -> AR_R {
424        AR_R::new(((self.bits >> 6) & 1) != 0)
425    }
426    ///Bit 7 - VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
427    #[inline(always)]
428    pub fn vspol(&self) -> VSPOL_R {
429        VSPOL_R::new(((self.bits >> 7) & 1) != 0)
430    }
431}
432impl core::fmt::Debug for R {
433    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
434        f.debug_struct("WCFGR")
435            .field("dsim", &self.dsim())
436            .field("colmux", &self.colmux())
437            .field("tesrc", &self.tesrc())
438            .field("tepol", &self.tepol())
439            .field("ar", &self.ar())
440            .field("vspol", &self.vspol())
441            .finish()
442    }
443}
444impl W {
445    ///Bit 0 - DSI mode This bit selects the mode for the video transmission. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
446    #[inline(always)]
447    pub fn dsim(&mut self) -> DSIM_W<WCFGRrs> {
448        DSIM_W::new(self, 0)
449    }
450    ///Bits 1:3 - Color multiplexing This bit selects the color multiplexing used by DSI Host. This field must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
451    #[inline(always)]
452    pub fn colmux(&mut self) -> COLMUX_W<WCFGRrs> {
453        COLMUX_W::new(self, 1)
454    }
455    ///Bit 4 - TE source This bit selects the tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
456    #[inline(always)]
457    pub fn tesrc(&mut self) -> TESRC_W<WCFGRrs> {
458        TESRC_W::new(self, 4)
459    }
460    ///Bit 5 - TE polarity This bit selects the polarity of the external pin tearing effect (TE) source. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
461    #[inline(always)]
462    pub fn tepol(&mut self) -> TEPOL_W<WCFGRrs> {
463        TEPOL_W::new(self, 5)
464    }
465    ///Bit 6 - Automatic refresh This bit selects the refresh mode in DBI mode. This bit must only be changed when DSI Host is stopped (DSI_CR.EN = 0).
466    #[inline(always)]
467    pub fn ar(&mut self) -> AR_W<WCFGRrs> {
468        AR_W::new(self, 6)
469    }
470    ///Bit 7 - VSync polarity This bit selects the VSync edge on which the LTDC is halted. This bit must only be changed when DSI is stopped (DSI_WCR.DSIEN = 0 and DSI_CR.EN=0).
471    #[inline(always)]
472    pub fn vspol(&mut self) -> VSPOL_W<WCFGRrs> {
473        VSPOL_W::new(self, 7)
474    }
475}
476/**DSI Wrapper configuration register
477
478You can [`read`](crate::Reg::read) this register and get [`wcfgr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`wcfgr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
479
480See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI:WCFGR)*/
481pub struct WCFGRrs;
482impl crate::RegisterSpec for WCFGRrs {
483    type Ux = u32;
484}
485///`read()` method returns [`wcfgr::R`](R) reader structure
486impl crate::Readable for WCFGRrs {}
487///`write(|w| ..)` method takes [`wcfgr::W`](W) writer structure
488impl crate::Writable for WCFGRrs {
489    type Safety = crate::Unsafe;
490}
491///`reset()` method sets WCFGR to value 0
492impl crate::Resettable for WCFGRrs {}
stm32f4_staging/stm32f469/dsi/wcfgr.rs

stm32f4_staging/stm32f469/dsi/
wcfgr.rs
