stm32f4_staging/stm32f469/dsi/
dltcr.rs

1///Register `DLTCR` reader
2pub type R = crate::R<DLTCRrs>;
3///Register `DLTCR` writer
4pub type W = crate::W<DLTCRrs>;
5///Field `MRD_TIME` reader - Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.
6pub type MRD_TIME_R = crate::FieldReader<u16>;
7///Field `MRD_TIME` writer - Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.
8pub type MRD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
9///Field `LP2HS_TIME` reader - Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.
10pub type LP2HS_TIME_R = crate::FieldReader;
11///Field `LP2HS_TIME` writer - Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.
12pub type LP2HS_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13///Field `HS2LP_TIME` reader - High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.
14pub type HS2LP_TIME_R = crate::FieldReader;
15///Field `HS2LP_TIME` writer - High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.
16pub type HS2LP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17impl R {
18    ///Bits 0:14 - Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.
19    #[inline(always)]
20    pub fn mrd_time(&self) -> MRD_TIME_R {
21        MRD_TIME_R::new((self.bits & 0x7fff) as u16)
22    }
23    ///Bits 16:23 - Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.
24    #[inline(always)]
25    pub fn lp2hs_time(&self) -> LP2HS_TIME_R {
26        LP2HS_TIME_R::new(((self.bits >> 16) & 0xff) as u8)
27    }
28    ///Bits 24:31 - High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.
29    #[inline(always)]
30    pub fn hs2lp_time(&self) -> HS2LP_TIME_R {
31        HS2LP_TIME_R::new(((self.bits >> 24) & 0xff) as u8)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("DLTCR")
37            .field("mrd_time", &self.mrd_time())
38            .field("lp2hs_time", &self.lp2hs_time())
39            .field("hs2lp_time", &self.hs2lp_time())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:14 - Maximum read time This field configures the maximum time required to perform a read command in lane byte clock cycles. This register can only be modified when no read command is in progress.
45    #[inline(always)]
46    pub fn mrd_time(&mut self) -> MRD_TIME_W<DLTCRrs> {
47        MRD_TIME_W::new(self, 0)
48    }
49    ///Bits 16:23 - Low-power to high-speed time This field configures the maximum time that the D-PHY data lanes take to go from low-power to high-speed transmission measured in lane byte clock cycles.
50    #[inline(always)]
51    pub fn lp2hs_time(&mut self) -> LP2HS_TIME_W<DLTCRrs> {
52        LP2HS_TIME_W::new(self, 16)
53    }
54    ///Bits 24:31 - High-speed to low-power time This field configures the maximum time that the D-PHY data lanes take to go from high-speed to low-power transmission measured in lane byte clock cycles.
55    #[inline(always)]
56    pub fn hs2lp_time(&mut self) -> HS2LP_TIME_W<DLTCRrs> {
57        HS2LP_TIME_W::new(self, 24)
58    }
59}
60/**DSI Host data lane timer configuration register
61
62You can [`read`](crate::Reg::read) this register and get [`dltcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dltcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI:DLTCR)*/
65pub struct DLTCRrs;
66impl crate::RegisterSpec for DLTCRrs {
67    type Ux = u32;
68}
69///`read()` method returns [`dltcr::R`](R) reader structure
70impl crate::Readable for DLTCRrs {}
71///`write(|w| ..)` method takes [`dltcr::W`](W) writer structure
72impl crate::Writable for DLTCRrs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets DLTCR to value 0
76impl crate::Resettable for DLTCRrs {}
stm32f4_staging/stm32f469/dsi/dltcr.rs

stm32f4_staging/stm32f469/dsi/
dltcr.rs
