stm32f4_staging/stm32f469/dsi/
clcr.rs

1///Register `CLCR` reader
2pub type R = crate::R<CLCRrs>;
3///Register `CLCR` writer
4pub type W = crate::W<CLCRrs>;
5/**D-PHY clock control This bit controls the D-PHY clock state:
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum DPCC {
11    ///0: Clock lane is in low-power mode.
12    B0x0 = 0,
13    ///1: Clock lane runs in high-speed mode.
14    B0x1 = 1,
15}
16impl From<DPCC> for bool {
17    #[inline(always)]
18    fn from(variant: DPCC) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `DPCC` reader - D-PHY clock control This bit controls the D-PHY clock state:
23pub type DPCC_R = crate::BitReader<DPCC>;
24impl DPCC_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> DPCC {
28        match self.bits {
29            false => DPCC::B0x0,
30            true => DPCC::B0x1,
31        }
32    }
33    ///Clock lane is in low-power mode.
34    #[inline(always)]
35    pub fn is_b_0x0(&self) -> bool {
36        *self == DPCC::B0x0
37    }
38    ///Clock lane runs in high-speed mode.
39    #[inline(always)]
40    pub fn is_b_0x1(&self) -> bool {
41        *self == DPCC::B0x1
42    }
43}
44///Field `DPCC` writer - D-PHY clock control This bit controls the D-PHY clock state:
45pub type DPCC_W<'a, REG> = crate::BitWriter<'a, REG, DPCC>;
46impl<'a, REG> DPCC_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Clock lane is in low-power mode.
51    #[inline(always)]
52    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
53        self.variant(DPCC::B0x0)
54    }
55    ///Clock lane runs in high-speed mode.
56    #[inline(always)]
57    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
58        self.variant(DPCC::B0x1)
59    }
60}
61/**Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum ACR {
67    ///0: Automatic clock lane control disabled
68    B0x0 = 0,
69    ///1: Automatic clock lane control enabled
70    B0x1 = 1,
71}
72impl From<ACR> for bool {
73    #[inline(always)]
74    fn from(variant: ACR) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `ACR` reader - Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
79pub type ACR_R = crate::BitReader<ACR>;
80impl ACR_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> ACR {
84        match self.bits {
85            false => ACR::B0x0,
86            true => ACR::B0x1,
87        }
88    }
89    ///Automatic clock lane control disabled
90    #[inline(always)]
91    pub fn is_b_0x0(&self) -> bool {
92        *self == ACR::B0x0
93    }
94    ///Automatic clock lane control enabled
95    #[inline(always)]
96    pub fn is_b_0x1(&self) -> bool {
97        *self == ACR::B0x1
98    }
99}
100///Field `ACR` writer - Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
101pub type ACR_W<'a, REG> = crate::BitWriter<'a, REG, ACR>;
102impl<'a, REG> ACR_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Automatic clock lane control disabled
107    #[inline(always)]
108    pub fn b_0x0(self) -> &'a mut crate::W<REG> {
109        self.variant(ACR::B0x0)
110    }
111    ///Automatic clock lane control enabled
112    #[inline(always)]
113    pub fn b_0x1(self) -> &'a mut crate::W<REG> {
114        self.variant(ACR::B0x1)
115    }
116}
117impl R {
118    ///Bit 0 - D-PHY clock control This bit controls the D-PHY clock state:
119    #[inline(always)]
120    pub fn dpcc(&self) -> DPCC_R {
121        DPCC_R::new((self.bits & 1) != 0)
122    }
123    ///Bit 1 - Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
124    #[inline(always)]
125    pub fn acr(&self) -> ACR_R {
126        ACR_R::new(((self.bits >> 1) & 1) != 0)
127    }
128}
129impl core::fmt::Debug for R {
130    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
131        f.debug_struct("CLCR")
132            .field("dpcc", &self.dpcc())
133            .field("acr", &self.acr())
134            .finish()
135    }
136}
137impl W {
138    ///Bit 0 - D-PHY clock control This bit controls the D-PHY clock state:
139    #[inline(always)]
140    pub fn dpcc(&mut self) -> DPCC_W<CLCRrs> {
141        DPCC_W::new(self, 0)
142    }
143    ///Bit 1 - Automatic clock lane control This bit enables the automatic mechanism to stop providing clock in the clock lane when time allows.
144    #[inline(always)]
145    pub fn acr(&mut self) -> ACR_W<CLCRrs> {
146        ACR_W::new(self, 1)
147    }
148}
149/**DSI Host clock lane configuration register
150
151You can [`read`](crate::Reg::read) this register and get [`clcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
152
153See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI:CLCR)*/
154pub struct CLCRrs;
155impl crate::RegisterSpec for CLCRrs {
156    type Ux = u32;
157}
158///`read()` method returns [`clcr::R`](R) reader structure
159impl crate::Readable for CLCRrs {}
160///`write(|w| ..)` method takes [`clcr::W`](W) writer structure
161impl crate::Writable for CLCRrs {
162    type Safety = crate::Unsafe;
163}
164///`reset()` method sets CLCR to value 0
165impl crate::Resettable for CLCRrs {}
stm32f4_staging/stm32f469/dsi/clcr.rs

stm32f4_staging/stm32f469/dsi/
clcr.rs
