stm32f4_staging/stm32f469/dsi/
ccr.rs

1///Register `CCR` reader
2pub type R = crate::R<CCRrs>;
3///Register `CCR` writer
4pub type W = crate::W<CCRrs>;
5///Field `TXECKDIV` reader - TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
6pub type TXECKDIV_R = crate::FieldReader;
7///Field `TXECKDIV` writer - TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
8pub type TXECKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9///Field `TOCKDIV` reader - Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
10pub type TOCKDIV_R = crate::FieldReader;
11///Field `TOCKDIV` writer - Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
12pub type TOCKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13impl R {
14    ///Bits 0:7 - TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
15    #[inline(always)]
16    pub fn txeckdiv(&self) -> TXECKDIV_R {
17        TXECKDIV_R::new((self.bits & 0xff) as u8)
18    }
19    ///Bits 8:15 - Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
20    #[inline(always)]
21    pub fn tockdiv(&self) -> TOCKDIV_R {
22        TOCKDIV_R::new(((self.bits >> 8) & 0xff) as u8)
23    }
24}
25impl core::fmt::Debug for R {
26    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
27        f.debug_struct("CCR")
28            .field("txeckdiv", &self.txeckdiv())
29            .field("tockdiv", &self.tockdiv())
30            .finish()
31    }
32}
33impl W {
34    ///Bits 0:7 - TX escape clock division This field indicates the division factor for the TX escape clock source (lanebyteclk). The values 0 and 1 stop the TX_ESC clock generation.
35    #[inline(always)]
36    pub fn txeckdiv(&mut self) -> TXECKDIV_W<CCRrs> {
37        TXECKDIV_W::new(self, 0)
38    }
39    ///Bits 8:15 - Timeout clock division This field indicates the division factor for the timeout clock used as the timing unit in the configuration of HS to LP and LP to HS transition error.
40    #[inline(always)]
41    pub fn tockdiv(&mut self) -> TOCKDIV_W<CCRrs> {
42        TOCKDIV_W::new(self, 8)
43    }
44}
45/**DSI Host clock control register
46
47You can [`read`](crate::Reg::read) this register and get [`ccr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
48
49See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DSI:CCR)*/
50pub struct CCRrs;
51impl crate::RegisterSpec for CCRrs {
52    type Ux = u32;
53}
54///`read()` method returns [`ccr::R`](R) reader structure
55impl crate::Readable for CCRrs {}
56///`write(|w| ..)` method takes [`ccr::W`](W) writer structure
57impl crate::Writable for CCRrs {
58    type Safety = crate::Unsafe;
59}
60///`reset()` method sets CCR to value 0
61impl crate::Resettable for CCRrs {}
stm32f4_staging/stm32f469/dsi/ccr.rs

stm32f4_staging/stm32f469/dsi/
ccr.rs
