stm32f4_staging/stm32f469/dcmi/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5/**Capture enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CAPTURE {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CAPTURE> for bool {
17    #[inline(always)]
18    fn from(variant: CAPTURE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CAPTURE` reader - Capture enable
23pub type CAPTURE_R = crate::BitReader<CAPTURE>;
24impl CAPTURE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CAPTURE {
28        match self.bits {
29            false => CAPTURE::Disabled,
30            true => CAPTURE::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CAPTURE::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CAPTURE::Enabled
42    }
43}
44///Field `CAPTURE` writer - Capture enable
45pub type CAPTURE_W<'a, REG> = crate::BitWriter<'a, REG, CAPTURE>;
46impl<'a, REG> CAPTURE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CAPTURE::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CAPTURE::Enabled)
59    }
60}
61/**Capture mode
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CM {
67    ///0: Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA
68    Continuous = 0,
69    ///1: Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset
70    Snapshot = 1,
71}
72impl From<CM> for bool {
73    #[inline(always)]
74    fn from(variant: CM) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CM` reader - Capture mode
79pub type CM_R = crate::BitReader<CM>;
80impl CM_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CM {
84        match self.bits {
85            false => CM::Continuous,
86            true => CM::Snapshot,
87        }
88    }
89    ///Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA
90    #[inline(always)]
91    pub fn is_continuous(&self) -> bool {
92        *self == CM::Continuous
93    }
94    ///Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset
95    #[inline(always)]
96    pub fn is_snapshot(&self) -> bool {
97        *self == CM::Snapshot
98    }
99}
100///Field `CM` writer - Capture mode
101pub type CM_W<'a, REG> = crate::BitWriter<'a, REG, CM>;
102impl<'a, REG> CM_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Continuous grab mode - The received data are transferred into the destination memory through the DMA. The buffer location and mode (linear or circular buffer) is controlled through the system DMA
107    #[inline(always)]
108    pub fn continuous(self) -> &'a mut crate::W<REG> {
109        self.variant(CM::Continuous)
110    }
111    ///Snapshot mode (single frame) - Once activated, the interface waits for the start of frame and then transfers a single frame through the DMA. At the end of the frame, the CAPTURE bit is automatically reset
112    #[inline(always)]
113    pub fn snapshot(self) -> &'a mut crate::W<REG> {
114        self.variant(CM::Snapshot)
115    }
116}
117/**Crop feature
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum CROP {
123    ///0: The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four
124    Full = 0,
125    ///1: Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured
126    Cropped = 1,
127}
128impl From<CROP> for bool {
129    #[inline(always)]
130    fn from(variant: CROP) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `CROP` reader - Crop feature
135pub type CROP_R = crate::BitReader<CROP>;
136impl CROP_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> CROP {
140        match self.bits {
141            false => CROP::Full,
142            true => CROP::Cropped,
143        }
144    }
145    ///The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four
146    #[inline(always)]
147    pub fn is_full(&self) -> bool {
148        *self == CROP::Full
149    }
150    ///Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured
151    #[inline(always)]
152    pub fn is_cropped(&self) -> bool {
153        *self == CROP::Cropped
154    }
155}
156///Field `CROP` writer - Crop feature
157pub type CROP_W<'a, REG> = crate::BitWriter<'a, REG, CROP>;
158impl<'a, REG> CROP_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///The full image is captured. In this case the total number of bytes in an image frame must be a multiple of four
163    #[inline(always)]
164    pub fn full(self) -> &'a mut crate::W<REG> {
165        self.variant(CROP::Full)
166    }
167    ///Only the data inside the window specified by the crop register is captured. If the size of the crop window exceeds the picture size, then only the picture size is captured
168    #[inline(always)]
169    pub fn cropped(self) -> &'a mut crate::W<REG> {
170        self.variant(CROP::Cropped)
171    }
172}
173/**JPEG format
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum JPEG {
179    ///0: Uncompressed video format
180    Uncompressed = 0,
181    ///1: This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode
182    Jpeg = 1,
183}
184impl From<JPEG> for bool {
185    #[inline(always)]
186    fn from(variant: JPEG) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `JPEG` reader - JPEG format
191pub type JPEG_R = crate::BitReader<JPEG>;
192impl JPEG_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> JPEG {
196        match self.bits {
197            false => JPEG::Uncompressed,
198            true => JPEG::Jpeg,
199        }
200    }
201    ///Uncompressed video format
202    #[inline(always)]
203    pub fn is_uncompressed(&self) -> bool {
204        *self == JPEG::Uncompressed
205    }
206    ///This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode
207    #[inline(always)]
208    pub fn is_jpeg(&self) -> bool {
209        *self == JPEG::Jpeg
210    }
211}
212///Field `JPEG` writer - JPEG format
213pub type JPEG_W<'a, REG> = crate::BitWriter<'a, REG, JPEG>;
214impl<'a, REG> JPEG_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Uncompressed video format
219    #[inline(always)]
220    pub fn uncompressed(self) -> &'a mut crate::W<REG> {
221        self.variant(JPEG::Uncompressed)
222    }
223    ///This bit is used for JPEG data transfers. The DCMI_HSYNC signal is used as data enable. The crop and embedded synchronization features (ESS bit) cannot be used in this mode
224    #[inline(always)]
225    pub fn jpeg(self) -> &'a mut crate::W<REG> {
226        self.variant(JPEG::Jpeg)
227    }
228}
229/**Embedded synchronization select
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum ESS {
235    ///0: Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals
236    Hardware = 0,
237    ///1: Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow
238    Embedded = 1,
239}
240impl From<ESS> for bool {
241    #[inline(always)]
242    fn from(variant: ESS) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `ESS` reader - Embedded synchronization select
247pub type ESS_R = crate::BitReader<ESS>;
248impl ESS_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> ESS {
252        match self.bits {
253            false => ESS::Hardware,
254            true => ESS::Embedded,
255        }
256    }
257    ///Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals
258    #[inline(always)]
259    pub fn is_hardware(&self) -> bool {
260        *self == ESS::Hardware
261    }
262    ///Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow
263    #[inline(always)]
264    pub fn is_embedded(&self) -> bool {
265        *self == ESS::Embedded
266    }
267}
268///Field `ESS` writer - Embedded synchronization select
269pub type ESS_W<'a, REG> = crate::BitWriter<'a, REG, ESS>;
270impl<'a, REG> ESS_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///Hardware synchronization data capture (frame/line start/stop) is synchronized with the DCMI_HSYNC/DCMI_VSYNC signals
275    #[inline(always)]
276    pub fn hardware(self) -> &'a mut crate::W<REG> {
277        self.variant(ESS::Hardware)
278    }
279    ///Embedded synchronization data capture is synchronized with synchronization codes embedded in the data flow
280    #[inline(always)]
281    pub fn embedded(self) -> &'a mut crate::W<REG> {
282        self.variant(ESS::Embedded)
283    }
284}
285/**Pixel clock polarity
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum PCKPOL {
291    ///0: Falling edge active
292    FallingEdge = 0,
293    ///1: Rising edge active
294    RisingEdge = 1,
295}
296impl From<PCKPOL> for bool {
297    #[inline(always)]
298    fn from(variant: PCKPOL) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `PCKPOL` reader - Pixel clock polarity
303pub type PCKPOL_R = crate::BitReader<PCKPOL>;
304impl PCKPOL_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> PCKPOL {
308        match self.bits {
309            false => PCKPOL::FallingEdge,
310            true => PCKPOL::RisingEdge,
311        }
312    }
313    ///Falling edge active
314    #[inline(always)]
315    pub fn is_falling_edge(&self) -> bool {
316        *self == PCKPOL::FallingEdge
317    }
318    ///Rising edge active
319    #[inline(always)]
320    pub fn is_rising_edge(&self) -> bool {
321        *self == PCKPOL::RisingEdge
322    }
323}
324///Field `PCKPOL` writer - Pixel clock polarity
325pub type PCKPOL_W<'a, REG> = crate::BitWriter<'a, REG, PCKPOL>;
326impl<'a, REG> PCKPOL_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Falling edge active
331    #[inline(always)]
332    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
333        self.variant(PCKPOL::FallingEdge)
334    }
335    ///Rising edge active
336    #[inline(always)]
337    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
338        self.variant(PCKPOL::RisingEdge)
339    }
340}
341/**Horizontal synchronization polarity
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum HSPOL {
347    ///0: DCMI_HSYNC active low
348    ActiveLow = 0,
349    ///1: DCMI_HSYNC active high
350    ActiveHigh = 1,
351}
352impl From<HSPOL> for bool {
353    #[inline(always)]
354    fn from(variant: HSPOL) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `HSPOL` reader - Horizontal synchronization polarity
359pub type HSPOL_R = crate::BitReader<HSPOL>;
360impl HSPOL_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> HSPOL {
364        match self.bits {
365            false => HSPOL::ActiveLow,
366            true => HSPOL::ActiveHigh,
367        }
368    }
369    ///DCMI_HSYNC active low
370    #[inline(always)]
371    pub fn is_active_low(&self) -> bool {
372        *self == HSPOL::ActiveLow
373    }
374    ///DCMI_HSYNC active high
375    #[inline(always)]
376    pub fn is_active_high(&self) -> bool {
377        *self == HSPOL::ActiveHigh
378    }
379}
380///Field `HSPOL` writer - Horizontal synchronization polarity
381pub type HSPOL_W<'a, REG> = crate::BitWriter<'a, REG, HSPOL>;
382impl<'a, REG> HSPOL_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///DCMI_HSYNC active low
387    #[inline(always)]
388    pub fn active_low(self) -> &'a mut crate::W<REG> {
389        self.variant(HSPOL::ActiveLow)
390    }
391    ///DCMI_HSYNC active high
392    #[inline(always)]
393    pub fn active_high(self) -> &'a mut crate::W<REG> {
394        self.variant(HSPOL::ActiveHigh)
395    }
396}
397/**Vertical synchronization polarity
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum VSPOL {
403    ///0: DCMI_VSYNC active low
404    ActiveLow = 0,
405    ///1: DCMI_VSYNC active high
406    ActiveHigh = 1,
407}
408impl From<VSPOL> for bool {
409    #[inline(always)]
410    fn from(variant: VSPOL) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `VSPOL` reader - Vertical synchronization polarity
415pub type VSPOL_R = crate::BitReader<VSPOL>;
416impl VSPOL_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> VSPOL {
420        match self.bits {
421            false => VSPOL::ActiveLow,
422            true => VSPOL::ActiveHigh,
423        }
424    }
425    ///DCMI_VSYNC active low
426    #[inline(always)]
427    pub fn is_active_low(&self) -> bool {
428        *self == VSPOL::ActiveLow
429    }
430    ///DCMI_VSYNC active high
431    #[inline(always)]
432    pub fn is_active_high(&self) -> bool {
433        *self == VSPOL::ActiveHigh
434    }
435}
436///Field `VSPOL` writer - Vertical synchronization polarity
437pub type VSPOL_W<'a, REG> = crate::BitWriter<'a, REG, VSPOL>;
438impl<'a, REG> VSPOL_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///DCMI_VSYNC active low
443    #[inline(always)]
444    pub fn active_low(self) -> &'a mut crate::W<REG> {
445        self.variant(VSPOL::ActiveLow)
446    }
447    ///DCMI_VSYNC active high
448    #[inline(always)]
449    pub fn active_high(self) -> &'a mut crate::W<REG> {
450        self.variant(VSPOL::ActiveHigh)
451    }
452}
453/**Frame capture rate control
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458#[repr(u8)]
459pub enum FCRC {
460    ///0: All frames are captured
461    All = 0,
462    ///1: Every alternate frame captured (50% bandwidth reduction)
463    Alternate = 1,
464    ///2: One frame out of four captured (75% bandwidth reduction)
465    OneOfFour = 2,
466}
467impl From<FCRC> for u8 {
468    #[inline(always)]
469    fn from(variant: FCRC) -> Self {
470        variant as _
471    }
472}
473impl crate::FieldSpec for FCRC {
474    type Ux = u8;
475}
476impl crate::IsEnum for FCRC {}
477///Field `FCRC` reader - Frame capture rate control
478pub type FCRC_R = crate::FieldReader<FCRC>;
479impl FCRC_R {
480    ///Get enumerated values variant
481    #[inline(always)]
482    pub const fn variant(&self) -> Option<FCRC> {
483        match self.bits {
484            0 => Some(FCRC::All),
485            1 => Some(FCRC::Alternate),
486            2 => Some(FCRC::OneOfFour),
487            _ => None,
488        }
489    }
490    ///All frames are captured
491    #[inline(always)]
492    pub fn is_all(&self) -> bool {
493        *self == FCRC::All
494    }
495    ///Every alternate frame captured (50% bandwidth reduction)
496    #[inline(always)]
497    pub fn is_alternate(&self) -> bool {
498        *self == FCRC::Alternate
499    }
500    ///One frame out of four captured (75% bandwidth reduction)
501    #[inline(always)]
502    pub fn is_one_of_four(&self) -> bool {
503        *self == FCRC::OneOfFour
504    }
505}
506///Field `FCRC` writer - Frame capture rate control
507pub type FCRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, FCRC>;
508impl<'a, REG> FCRC_W<'a, REG>
509where
510    REG: crate::Writable + crate::RegisterSpec,
511    REG::Ux: From<u8>,
512{
513    ///All frames are captured
514    #[inline(always)]
515    pub fn all(self) -> &'a mut crate::W<REG> {
516        self.variant(FCRC::All)
517    }
518    ///Every alternate frame captured (50% bandwidth reduction)
519    #[inline(always)]
520    pub fn alternate(self) -> &'a mut crate::W<REG> {
521        self.variant(FCRC::Alternate)
522    }
523    ///One frame out of four captured (75% bandwidth reduction)
524    #[inline(always)]
525    pub fn one_of_four(self) -> &'a mut crate::W<REG> {
526        self.variant(FCRC::OneOfFour)
527    }
528}
529/**Extended data mode
530
531Value on reset: 0*/
532#[cfg_attr(feature = "defmt", derive(defmt::Format))]
533#[derive(Clone, Copy, Debug, PartialEq, Eq)]
534#[repr(u8)]
535pub enum EDM {
536    ///0: Interface captures 8-bit data on every pixel clock
537    BitWidth8 = 0,
538    ///1: Interface captures 10-bit data on every pixel clock
539    BitWidth10 = 1,
540    ///2: Interface captures 12-bit data on every pixel clock
541    BitWidth12 = 2,
542    ///3: Interface captures 14-bit data on every pixel clock
543    BitWidth14 = 3,
544}
545impl From<EDM> for u8 {
546    #[inline(always)]
547    fn from(variant: EDM) -> Self {
548        variant as _
549    }
550}
551impl crate::FieldSpec for EDM {
552    type Ux = u8;
553}
554impl crate::IsEnum for EDM {}
555///Field `EDM` reader - Extended data mode
556pub type EDM_R = crate::FieldReader<EDM>;
557impl EDM_R {
558    ///Get enumerated values variant
559    #[inline(always)]
560    pub const fn variant(&self) -> EDM {
561        match self.bits {
562            0 => EDM::BitWidth8,
563            1 => EDM::BitWidth10,
564            2 => EDM::BitWidth12,
565            3 => EDM::BitWidth14,
566            _ => unreachable!(),
567        }
568    }
569    ///Interface captures 8-bit data on every pixel clock
570    #[inline(always)]
571    pub fn is_bit_width8(&self) -> bool {
572        *self == EDM::BitWidth8
573    }
574    ///Interface captures 10-bit data on every pixel clock
575    #[inline(always)]
576    pub fn is_bit_width10(&self) -> bool {
577        *self == EDM::BitWidth10
578    }
579    ///Interface captures 12-bit data on every pixel clock
580    #[inline(always)]
581    pub fn is_bit_width12(&self) -> bool {
582        *self == EDM::BitWidth12
583    }
584    ///Interface captures 14-bit data on every pixel clock
585    #[inline(always)]
586    pub fn is_bit_width14(&self) -> bool {
587        *self == EDM::BitWidth14
588    }
589}
590///Field `EDM` writer - Extended data mode
591pub type EDM_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EDM, crate::Safe>;
592impl<'a, REG> EDM_W<'a, REG>
593where
594    REG: crate::Writable + crate::RegisterSpec,
595    REG::Ux: From<u8>,
596{
597    ///Interface captures 8-bit data on every pixel clock
598    #[inline(always)]
599    pub fn bit_width8(self) -> &'a mut crate::W<REG> {
600        self.variant(EDM::BitWidth8)
601    }
602    ///Interface captures 10-bit data on every pixel clock
603    #[inline(always)]
604    pub fn bit_width10(self) -> &'a mut crate::W<REG> {
605        self.variant(EDM::BitWidth10)
606    }
607    ///Interface captures 12-bit data on every pixel clock
608    #[inline(always)]
609    pub fn bit_width12(self) -> &'a mut crate::W<REG> {
610        self.variant(EDM::BitWidth12)
611    }
612    ///Interface captures 14-bit data on every pixel clock
613    #[inline(always)]
614    pub fn bit_width14(self) -> &'a mut crate::W<REG> {
615        self.variant(EDM::BitWidth14)
616    }
617}
618/**DCMI enable
619
620Value on reset: 0*/
621#[cfg_attr(feature = "defmt", derive(defmt::Format))]
622#[derive(Clone, Copy, Debug, PartialEq, Eq)]
623pub enum ENABLE {
624    ///0: DCMI disabled
625    Disabled = 0,
626    ///1: DCMI enabled
627    Enabled = 1,
628}
629impl From<ENABLE> for bool {
630    #[inline(always)]
631    fn from(variant: ENABLE) -> Self {
632        variant as u8 != 0
633    }
634}
635///Field `ENABLE` reader - DCMI enable
636pub type ENABLE_R = crate::BitReader<ENABLE>;
637impl ENABLE_R {
638    ///Get enumerated values variant
639    #[inline(always)]
640    pub const fn variant(&self) -> ENABLE {
641        match self.bits {
642            false => ENABLE::Disabled,
643            true => ENABLE::Enabled,
644        }
645    }
646    ///DCMI disabled
647    #[inline(always)]
648    pub fn is_disabled(&self) -> bool {
649        *self == ENABLE::Disabled
650    }
651    ///DCMI enabled
652    #[inline(always)]
653    pub fn is_enabled(&self) -> bool {
654        *self == ENABLE::Enabled
655    }
656}
657///Field `ENABLE` writer - DCMI enable
658pub type ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, ENABLE>;
659impl<'a, REG> ENABLE_W<'a, REG>
660where
661    REG: crate::Writable + crate::RegisterSpec,
662{
663    ///DCMI disabled
664    #[inline(always)]
665    pub fn disabled(self) -> &'a mut crate::W<REG> {
666        self.variant(ENABLE::Disabled)
667    }
668    ///DCMI enabled
669    #[inline(always)]
670    pub fn enabled(self) -> &'a mut crate::W<REG> {
671        self.variant(ENABLE::Enabled)
672    }
673}
674impl R {
675    ///Bit 0 - Capture enable
676    #[inline(always)]
677    pub fn capture(&self) -> CAPTURE_R {
678        CAPTURE_R::new((self.bits & 1) != 0)
679    }
680    ///Bit 1 - Capture mode
681    #[inline(always)]
682    pub fn cm(&self) -> CM_R {
683        CM_R::new(((self.bits >> 1) & 1) != 0)
684    }
685    ///Bit 2 - Crop feature
686    #[inline(always)]
687    pub fn crop(&self) -> CROP_R {
688        CROP_R::new(((self.bits >> 2) & 1) != 0)
689    }
690    ///Bit 3 - JPEG format
691    #[inline(always)]
692    pub fn jpeg(&self) -> JPEG_R {
693        JPEG_R::new(((self.bits >> 3) & 1) != 0)
694    }
695    ///Bit 4 - Embedded synchronization select
696    #[inline(always)]
697    pub fn ess(&self) -> ESS_R {
698        ESS_R::new(((self.bits >> 4) & 1) != 0)
699    }
700    ///Bit 5 - Pixel clock polarity
701    #[inline(always)]
702    pub fn pckpol(&self) -> PCKPOL_R {
703        PCKPOL_R::new(((self.bits >> 5) & 1) != 0)
704    }
705    ///Bit 6 - Horizontal synchronization polarity
706    #[inline(always)]
707    pub fn hspol(&self) -> HSPOL_R {
708        HSPOL_R::new(((self.bits >> 6) & 1) != 0)
709    }
710    ///Bit 7 - Vertical synchronization polarity
711    #[inline(always)]
712    pub fn vspol(&self) -> VSPOL_R {
713        VSPOL_R::new(((self.bits >> 7) & 1) != 0)
714    }
715    ///Bits 8:9 - Frame capture rate control
716    #[inline(always)]
717    pub fn fcrc(&self) -> FCRC_R {
718        FCRC_R::new(((self.bits >> 8) & 3) as u8)
719    }
720    ///Bits 10:11 - Extended data mode
721    #[inline(always)]
722    pub fn edm(&self) -> EDM_R {
723        EDM_R::new(((self.bits >> 10) & 3) as u8)
724    }
725    ///Bit 14 - DCMI enable
726    #[inline(always)]
727    pub fn enable(&self) -> ENABLE_R {
728        ENABLE_R::new(((self.bits >> 14) & 1) != 0)
729    }
730}
731impl core::fmt::Debug for R {
732    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
733        f.debug_struct("CR")
734            .field("enable", &self.enable())
735            .field("edm", &self.edm())
736            .field("fcrc", &self.fcrc())
737            .field("vspol", &self.vspol())
738            .field("hspol", &self.hspol())
739            .field("pckpol", &self.pckpol())
740            .field("ess", &self.ess())
741            .field("jpeg", &self.jpeg())
742            .field("crop", &self.crop())
743            .field("cm", &self.cm())
744            .field("capture", &self.capture())
745            .finish()
746    }
747}
748impl W {
749    ///Bit 0 - Capture enable
750    #[inline(always)]
751    pub fn capture(&mut self) -> CAPTURE_W<CRrs> {
752        CAPTURE_W::new(self, 0)
753    }
754    ///Bit 1 - Capture mode
755    #[inline(always)]
756    pub fn cm(&mut self) -> CM_W<CRrs> {
757        CM_W::new(self, 1)
758    }
759    ///Bit 2 - Crop feature
760    #[inline(always)]
761    pub fn crop(&mut self) -> CROP_W<CRrs> {
762        CROP_W::new(self, 2)
763    }
764    ///Bit 3 - JPEG format
765    #[inline(always)]
766    pub fn jpeg(&mut self) -> JPEG_W<CRrs> {
767        JPEG_W::new(self, 3)
768    }
769    ///Bit 4 - Embedded synchronization select
770    #[inline(always)]
771    pub fn ess(&mut self) -> ESS_W<CRrs> {
772        ESS_W::new(self, 4)
773    }
774    ///Bit 5 - Pixel clock polarity
775    #[inline(always)]
776    pub fn pckpol(&mut self) -> PCKPOL_W<CRrs> {
777        PCKPOL_W::new(self, 5)
778    }
779    ///Bit 6 - Horizontal synchronization polarity
780    #[inline(always)]
781    pub fn hspol(&mut self) -> HSPOL_W<CRrs> {
782        HSPOL_W::new(self, 6)
783    }
784    ///Bit 7 - Vertical synchronization polarity
785    #[inline(always)]
786    pub fn vspol(&mut self) -> VSPOL_W<CRrs> {
787        VSPOL_W::new(self, 7)
788    }
789    ///Bits 8:9 - Frame capture rate control
790    #[inline(always)]
791    pub fn fcrc(&mut self) -> FCRC_W<CRrs> {
792        FCRC_W::new(self, 8)
793    }
794    ///Bits 10:11 - Extended data mode
795    #[inline(always)]
796    pub fn edm(&mut self) -> EDM_W<CRrs> {
797        EDM_W::new(self, 10)
798    }
799    ///Bit 14 - DCMI enable
800    #[inline(always)]
801    pub fn enable(&mut self) -> ENABLE_W<CRrs> {
802        ENABLE_W::new(self, 14)
803    }
804}
805/**control register 1
806
807You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
808
809See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F469.html#DCMI:CR)*/
810pub struct CRrs;
811impl crate::RegisterSpec for CRrs {
812    type Ux = u32;
813}
814///`read()` method returns [`cr::R`](R) reader structure
815impl crate::Readable for CRrs {}
816///`write(|w| ..)` method takes [`cr::W`](W) writer structure
817impl crate::Writable for CRrs {
818    type Safety = crate::Unsafe;
819}
820///`reset()` method sets CR to value 0
821impl crate::Resettable for CRrs {}
stm32f4_staging/stm32f469/dcmi/cr.rs

stm32f4_staging/stm32f469/dcmi/
cr.rs
