stm32f4_staging/stm32f413/
mod.rs

1/*!Peripheral access API for STM32F413 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn PVD();
21    fn TAMP_STAMP();
22    fn RTC_WKUP();
23    fn FLASH();
24    fn RCC();
25    fn EXTI0();
26    fn EXTI1();
27    fn EXTI2();
28    fn EXTI3();
29    fn EXTI4();
30    fn DMA1_STREAM0();
31    fn DMA1_STREAM1();
32    fn DMA1_STREAM2();
33    fn DMA1_STREAM3();
34    fn DMA1_STREAM4();
35    fn DMA1_STREAM5();
36    fn DMA1_STREAM6();
37    fn ADC();
38    fn CAN1_TX();
39    fn CAN1_RX0();
40    fn CAN1_RX1();
41    fn CAN1_SCE();
42    fn EXTI9_5();
43    fn TIM1_BRK_TIM9();
44    fn TIM1_UP_TIM10();
45    fn TIM1_TRG_COM_TIM11();
46    fn TIM1_CC();
47    fn TIM2();
48    fn TIM3();
49    fn TIM4();
50    fn I2C1_EVT();
51    fn I2C1_ERR();
52    fn I2C2_EVT();
53    fn I2C2_ERR();
54    fn SPI1();
55    fn SPI2();
56    fn USART1();
57    fn USART2();
58    fn USART3();
59    fn EXTI15_10();
60    fn EXTI17_RTC_ALARM();
61    fn TIM8_BRK_TIM12();
62    fn TIM8_UP_TIM13();
63    fn TIM8_TRG_COM_TIM14();
64    fn TIM8_CC();
65    fn DMA1_STREAM7();
66    fn FSMC();
67    fn SDIO();
68    fn TIM5();
69    fn UART4();
70    fn UART5();
71    fn TIM6_GLB_IT_DAC1_DAC2();
72    fn TIM7();
73    fn DMA2_STREAM0();
74    fn DMA2_STREAM1();
75    fn DMA2_STREAM2();
76    fn DMA2_STREAM3();
77    fn DMA2_STREAM4();
78    fn DFSDM1_FLT0();
79    fn DFSDM1_FLT1();
80    fn CAN2_TX();
81    fn CAN2_RX0();
82    fn CAN2_RX1();
83    fn CAN2_SCE();
84    fn OTG_FS();
85    fn DMA2_STREAM5();
86    fn DMA2_STREAM6();
87    fn DMA2_STREAM7();
88    fn USART6();
89    fn I2C3_EV();
90    fn I2C3_ER();
91    fn CAN3_TX();
92    fn CAN3_RX0();
93    fn CAN3_RX1();
94    fn CAN3_SCE();
95    fn CRYPTO();
96    fn RNG();
97    fn FPU();
98    fn UART7();
99    fn UART8();
100    fn SPI4();
101    fn SPI5();
102    fn SAI1();
103    fn UART9();
104    fn UART10();
105    fn QUAD_SPI();
106    fn I2CFMP1EVENT();
107    fn I2CFMP1ERROR();
108    fn LPTIM1_OR_IT_EIT_23();
109    fn DFSDM2_FILTER1();
110    fn DFSDM2_FILTER2();
111    fn DFSDM2_FILTER3();
112    fn DFSDM2_FILTER4();
113}
114#[doc(hidden)]
115#[repr(C)]
116pub union Vector {
117    _handler: unsafe extern "C" fn(),
118    _reserved: u32,
119}
120#[cfg(feature = "rt")]
121#[doc(hidden)]
122#[link_section = ".vector_table.interrupts"]
123#[no_mangle]
124pub static __INTERRUPTS: [Vector; 102] = [
125    Vector { _reserved: 0 },
126    Vector { _handler: PVD },
127    Vector {
128        _handler: TAMP_STAMP,
129    },
130    Vector { _handler: RTC_WKUP },
131    Vector { _handler: FLASH },
132    Vector { _handler: RCC },
133    Vector { _handler: EXTI0 },
134    Vector { _handler: EXTI1 },
135    Vector { _handler: EXTI2 },
136    Vector { _handler: EXTI3 },
137    Vector { _handler: EXTI4 },
138    Vector {
139        _handler: DMA1_STREAM0,
140    },
141    Vector {
142        _handler: DMA1_STREAM1,
143    },
144    Vector {
145        _handler: DMA1_STREAM2,
146    },
147    Vector {
148        _handler: DMA1_STREAM3,
149    },
150    Vector {
151        _handler: DMA1_STREAM4,
152    },
153    Vector {
154        _handler: DMA1_STREAM5,
155    },
156    Vector {
157        _handler: DMA1_STREAM6,
158    },
159    Vector { _handler: ADC },
160    Vector { _handler: CAN1_TX },
161    Vector { _handler: CAN1_RX0 },
162    Vector { _handler: CAN1_RX1 },
163    Vector { _handler: CAN1_SCE },
164    Vector { _handler: EXTI9_5 },
165    Vector {
166        _handler: TIM1_BRK_TIM9,
167    },
168    Vector {
169        _handler: TIM1_UP_TIM10,
170    },
171    Vector {
172        _handler: TIM1_TRG_COM_TIM11,
173    },
174    Vector { _handler: TIM1_CC },
175    Vector { _handler: TIM2 },
176    Vector { _handler: TIM3 },
177    Vector { _handler: TIM4 },
178    Vector { _handler: I2C1_EVT },
179    Vector { _handler: I2C1_ERR },
180    Vector { _handler: I2C2_EVT },
181    Vector { _handler: I2C2_ERR },
182    Vector { _handler: SPI1 },
183    Vector { _handler: SPI2 },
184    Vector { _handler: USART1 },
185    Vector { _handler: USART2 },
186    Vector { _handler: USART3 },
187    Vector {
188        _handler: EXTI15_10,
189    },
190    Vector {
191        _handler: EXTI17_RTC_ALARM,
192    },
193    Vector { _reserved: 0 },
194    Vector {
195        _handler: TIM8_BRK_TIM12,
196    },
197    Vector {
198        _handler: TIM8_UP_TIM13,
199    },
200    Vector {
201        _handler: TIM8_TRG_COM_TIM14,
202    },
203    Vector { _handler: TIM8_CC },
204    Vector {
205        _handler: DMA1_STREAM7,
206    },
207    Vector { _handler: FSMC },
208    Vector { _handler: SDIO },
209    Vector { _handler: TIM5 },
210    Vector { _reserved: 0 },
211    Vector { _handler: UART4 },
212    Vector { _handler: UART5 },
213    Vector {
214        _handler: TIM6_GLB_IT_DAC1_DAC2,
215    },
216    Vector { _handler: TIM7 },
217    Vector {
218        _handler: DMA2_STREAM0,
219    },
220    Vector {
221        _handler: DMA2_STREAM1,
222    },
223    Vector {
224        _handler: DMA2_STREAM2,
225    },
226    Vector {
227        _handler: DMA2_STREAM3,
228    },
229    Vector {
230        _handler: DMA2_STREAM4,
231    },
232    Vector {
233        _handler: DFSDM1_FLT0,
234    },
235    Vector {
236        _handler: DFSDM1_FLT1,
237    },
238    Vector { _handler: CAN2_TX },
239    Vector { _handler: CAN2_RX0 },
240    Vector { _handler: CAN2_RX1 },
241    Vector { _handler: CAN2_SCE },
242    Vector { _handler: OTG_FS },
243    Vector {
244        _handler: DMA2_STREAM5,
245    },
246    Vector {
247        _handler: DMA2_STREAM6,
248    },
249    Vector {
250        _handler: DMA2_STREAM7,
251    },
252    Vector { _handler: USART6 },
253    Vector { _handler: I2C3_EV },
254    Vector { _handler: I2C3_ER },
255    Vector { _handler: CAN3_TX },
256    Vector { _handler: CAN3_RX0 },
257    Vector { _handler: CAN3_RX1 },
258    Vector { _handler: CAN3_SCE },
259    Vector { _reserved: 0 },
260    Vector { _handler: CRYPTO },
261    Vector { _handler: RNG },
262    Vector { _handler: FPU },
263    Vector { _handler: UART7 },
264    Vector { _handler: UART8 },
265    Vector { _handler: SPI4 },
266    Vector { _handler: SPI5 },
267    Vector { _reserved: 0 },
268    Vector { _handler: SAI1 },
269    Vector { _handler: UART9 },
270    Vector { _handler: UART10 },
271    Vector { _reserved: 0 },
272    Vector { _reserved: 0 },
273    Vector { _handler: QUAD_SPI },
274    Vector { _reserved: 0 },
275    Vector { _reserved: 0 },
276    Vector {
277        _handler: I2CFMP1EVENT,
278    },
279    Vector {
280        _handler: I2CFMP1ERROR,
281    },
282    Vector {
283        _handler: LPTIM1_OR_IT_EIT_23,
284    },
285    Vector {
286        _handler: DFSDM2_FILTER1,
287    },
288    Vector {
289        _handler: DFSDM2_FILTER2,
290    },
291    Vector {
292        _handler: DFSDM2_FILTER3,
293    },
294    Vector {
295        _handler: DFSDM2_FILTER4,
296    },
297];
298///Enumeration of all the interrupts.
299#[cfg_attr(feature = "defmt", derive(defmt::Format))]
300#[derive(Copy, Clone, Debug, PartialEq, Eq)]
301#[repr(u16)]
302pub enum Interrupt {
303    ///1 - PVD through EXTI line detection interrupt
304    PVD = 1,
305    ///2 - Tamper and TimeStamp interrupts through the EXTI line
306    TAMP_STAMP = 2,
307    ///3 - RTC Wakeup interrupt through the EXTI line
308    RTC_WKUP = 3,
309    ///4 - FLASH global interrupt
310    FLASH = 4,
311    ///5 - RCC global interrupt
312    RCC = 5,
313    ///6 - EXTI Line0 interrupt
314    EXTI0 = 6,
315    ///7 - EXTI Line1 interrupt
316    EXTI1 = 7,
317    ///8 - EXTI Line2 interrupt
318    EXTI2 = 8,
319    ///9 - EXTI Line3 interrupt
320    EXTI3 = 9,
321    ///10 - EXTI Line4 interrupt
322    EXTI4 = 10,
323    ///11 - DMA1 Stream0 global interrupt
324    DMA1_STREAM0 = 11,
325    ///12 - DMA1 Stream1 global interrupt
326    DMA1_STREAM1 = 12,
327    ///13 - DMA1 Stream2 global interrupt
328    DMA1_STREAM2 = 13,
329    ///14 - DMA1 Stream3 global interrupt
330    DMA1_STREAM3 = 14,
331    ///15 - DMA1 Stream4 global interrupt
332    DMA1_STREAM4 = 15,
333    ///16 - DMA1 Stream5 global interrupt
334    DMA1_STREAM5 = 16,
335    ///17 - DMA1 Stream6 global interrupt
336    DMA1_STREAM6 = 17,
337    ///18 - ADC1 global interrupt
338    ADC = 18,
339    ///19 - CAN1 TX interrupts
340    CAN1_TX = 19,
341    ///20 - CAN1 RX0 interrupts
342    CAN1_RX0 = 20,
343    ///21 - CAN1 RX1 interrupts
344    CAN1_RX1 = 21,
345    ///22 - CAN1 SCE interrupt
346    CAN1_SCE = 22,
347    ///23 - EXTI Line\[9:5\] interrupts
348    EXTI9_5 = 23,
349    ///24 - TIM1 Break interrupt and TIM9 global interrupt
350    TIM1_BRK_TIM9 = 24,
351    ///25 - TIM1 Update interrupt and TIM10 global interrupt
352    TIM1_UP_TIM10 = 25,
353    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
354    TIM1_TRG_COM_TIM11 = 26,
355    ///27 - TIM1 Capture Compare interrupt
356    TIM1_CC = 27,
357    ///28 - TIM2 global interrupt
358    TIM2 = 28,
359    ///29 - TIM3 global interrupt
360    TIM3 = 29,
361    ///30 - TIM4 global interrupt
362    TIM4 = 30,
363    ///31 - I2C1 event interrupt
364    I2C1_EVT = 31,
365    ///32 - I2C1 error interrupt
366    I2C1_ERR = 32,
367    ///33 - I2C2 event interrupt
368    I2C2_EVT = 33,
369    ///34 - I2C2 error interrupt
370    I2C2_ERR = 34,
371    ///35 - SPI1 global interrupt
372    SPI1 = 35,
373    ///36 - SPI2 global interrupt
374    SPI2 = 36,
375    ///37 - USART1 global interrupt
376    USART1 = 37,
377    ///38 - USART 2 global interrupt
378    USART2 = 38,
379    ///39 - USART 3 global interrupt
380    USART3 = 39,
381    ///40 - EXTI Line\[15:10\] interrupts
382    EXTI15_10 = 40,
383    ///41 - RTC Alarms (A and B) through EXTI line interrupt
384    EXTI17_RTC_ALARM = 41,
385    ///43 - Timer 12 global interrupt
386    TIM8_BRK_TIM12 = 43,
387    ///44 - Timer 13 global interrupt
388    TIM8_UP_TIM13 = 44,
389    ///45 - Timer 14 global interrupt
390    TIM8_TRG_COM_TIM14 = 45,
391    ///46 - TIM8 Cap/Com interrupt
392    TIM8_CC = 46,
393    ///47 - DMA1 global interrupt Channel 7
394    DMA1_STREAM7 = 47,
395    ///48 - FSMC global interrupt
396    FSMC = 48,
397    ///49 - SDIO global interrupt
398    SDIO = 49,
399    ///50 - TIM5 global interrupt
400    TIM5 = 50,
401    ///52 - UART4 global interrupt
402    UART4 = 52,
403    ///53 - UART5 global interrupt
404    UART5 = 53,
405    ///54 - TIM6 global and DAC12 underrun interrupts
406    TIM6_GLB_IT_DAC1_DAC2 = 54,
407    ///55 - TIM7 global interrupt
408    TIM7 = 55,
409    ///56 - DMA2 Stream0 global interrupt
410    DMA2_STREAM0 = 56,
411    ///57 - DMA2 Stream1 global interrupt
412    DMA2_STREAM1 = 57,
413    ///58 - DMA2 Stream2 global interrupt
414    DMA2_STREAM2 = 58,
415    ///59 - DMA2 Stream3 global interrupt
416    DMA2_STREAM3 = 59,
417    ///60 - DMA2 Stream4 global interrupt
418    DMA2_STREAM4 = 60,
419    ///61 - SD filter0 global interrupt
420    DFSDM1_FLT0 = 61,
421    ///62 - SD filter1 global interrupt
422    DFSDM1_FLT1 = 62,
423    ///63 - CAN2 TX interrupt
424    CAN2_TX = 63,
425    ///64 - BXCAN2 RX0 interrupt
426    CAN2_RX0 = 64,
427    ///65 - BXCAN2 RX1 interrupt
428    CAN2_RX1 = 65,
429    ///66 - CAN2 SCE interrupt
430    CAN2_SCE = 66,
431    ///67 - USB OTG FS Interrupt
432    OTG_FS = 67,
433    ///68 - DMA2 Stream5 global interrupt
434    DMA2_STREAM5 = 68,
435    ///69 - DMA2 Stream6 global interrupt
436    DMA2_STREAM6 = 69,
437    ///70 - DMA2 Stream7 global interrupt
438    DMA2_STREAM7 = 70,
439    ///71 - USART 6 global interrupt
440    USART6 = 71,
441    ///72 - I2C3 event interrupt
442    I2C3_EV = 72,
443    ///73 - I2C3 error interrupt
444    I2C3_ER = 73,
445    ///74 - CAN 3 TX interrupt
446    CAN3_TX = 74,
447    ///75 - BxCAN 3 RX0 interrupt
448    CAN3_RX0 = 75,
449    ///76 - BxCAN 3 RX1 interrupt
450    CAN3_RX1 = 76,
451    ///77 - CAN 3 SCE interrupt
452    CAN3_SCE = 77,
453    ///79 - AES global interrupt
454    CRYPTO = 79,
455    ///80 - Rng global interrupt
456    RNG = 80,
457    ///81 - FPU interrupt
458    FPU = 81,
459    ///82 - UART 7 global interrupt
460    UART7 = 82,
461    ///83 - UART 8 global interrupt
462    UART8 = 83,
463    ///84 - SPI4 global interrupt
464    SPI4 = 84,
465    ///85 - SPI5 global interrupt
466    SPI5 = 85,
467    ///87 - SAI1 global interrupt
468    SAI1 = 87,
469    ///88 - UART9 global interrupt
470    UART9 = 88,
471    ///89 - UART10 global interrupt
472    UART10 = 89,
473    ///92 - Quad-SPI global interrupt
474    QUAD_SPI = 92,
475    ///95 - I2CFMP1 event interrupt
476    I2CFMP1EVENT = 95,
477    ///96 - I2CFMP1 error interrupt
478    I2CFMP1ERROR = 96,
479    ///97 - LP Timer global interrupt or EXT1 interrupt line 23
480    LPTIM1_OR_IT_EIT_23 = 97,
481    ///98 - DFSDM2 SD filter 1 global interrupt
482    DFSDM2_FILTER1 = 98,
483    ///99 - DFSDM2 SD filter 2 global interrupt
484    DFSDM2_FILTER2 = 99,
485    ///100 - DFSDM2 SD filter 3 global interrupt
486    DFSDM2_FILTER3 = 100,
487    ///101 - DFSDM2 SD filter 4 global interrupt
488    DFSDM2_FILTER4 = 101,
489}
490unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
491    #[inline(always)]
492    fn number(self) -> u16 {
493        self as u16
494    }
495}
496///Advanced encryption standard hardware accelerator
497///
498///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#AES)
499pub type AES = crate::Periph<aes::RegisterBlock, 0x5006_0000>;
500impl core::fmt::Debug for AES {
501    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
502        f.debug_struct("AES").finish()
503    }
504}
505///Advanced encryption standard hardware accelerator
506pub mod aes;
507///Advanced-timers
508///
509///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM1)
510pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
511impl core::fmt::Debug for TIM1 {
512    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
513        f.debug_struct("TIM1").finish()
514    }
515}
516///Advanced-timers
517pub mod tim1;
518///Advanced-timers
519///
520///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM1)
521pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
522impl core::fmt::Debug for TIM8 {
523    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
524        f.debug_struct("TIM8").finish()
525    }
526}
527///Advanced-timers
528pub use self::tim1 as tim8;
529///Analog-to-digital converter
530///
531///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#ADC1)
532pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
533impl core::fmt::Debug for ADC1 {
534    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
535        f.debug_struct("ADC1").finish()
536    }
537}
538///Analog-to-digital converter
539pub mod adc1;
540///Basic timers
541///
542///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM7)
543pub type TIM7 = crate::Periph<tim7::RegisterBlock, 0x4000_1400>;
544impl core::fmt::Debug for TIM7 {
545    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
546        f.debug_struct("TIM7").finish()
547    }
548}
549///Basic timers
550pub mod tim7;
551///Basic timers
552///
553///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM7)
554pub type TIM6 = crate::Periph<tim7::RegisterBlock, 0x4000_1000>;
555impl core::fmt::Debug for TIM6 {
556    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
557        f.debug_struct("TIM6").finish()
558    }
559}
560///Basic timers
561pub use self::tim7 as tim6;
562///Controller area network
563///
564///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
565pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
566impl core::fmt::Debug for CAN1 {
567    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
568        f.debug_struct("CAN1").finish()
569    }
570}
571///Controller area network
572pub mod can1;
573///Controller area network
574///
575///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
576pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
577impl core::fmt::Debug for CAN2 {
578    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
579        f.debug_struct("CAN2").finish()
580    }
581}
582///Controller area network
583pub use self::can1 as can2;
584///Controller area network
585///
586///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CAN1)
587pub type CAN3 = crate::Periph<can1::RegisterBlock, 0x4000_6c00>;
588impl core::fmt::Debug for CAN3 {
589    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
590        f.debug_struct("CAN3").finish()
591    }
592}
593///Controller area network
594pub use self::can1 as can3;
595///Cryptographic processor
596///
597///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#CRC)
598pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
599impl core::fmt::Debug for CRC {
600    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
601        f.debug_struct("CRC").finish()
602    }
603}
604///Cryptographic processor
605pub mod crc;
606///Debug support
607///
608///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DBGMCU)
609pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
610impl core::fmt::Debug for DBGMCU {
611    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
612        f.debug_struct("DBGMCU").finish()
613    }
614}
615///Debug support
616pub mod dbgmcu;
617///Digital filter for sigma delta modulators
618///
619///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DFSDM2)
620pub type DFSDM2 = crate::Periph<dfsdm2::RegisterBlock, 0x4001_6400>;
621impl core::fmt::Debug for DFSDM2 {
622    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
623        f.debug_struct("DFSDM2").finish()
624    }
625}
626///Digital filter for sigma delta modulators
627pub mod dfsdm2;
628///Digital filter for sigma delta modulators
629///
630///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DFSDM2)
631pub type DFSDM1 = crate::Periph<dfsdm2::RegisterBlock, 0x4001_6000>;
632impl core::fmt::Debug for DFSDM1 {
633    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
634        f.debug_struct("DFSDM1").finish()
635    }
636}
637///Digital filter for sigma delta modulators
638pub use self::dfsdm2 as dfsdm1;
639///Digital-to-analog converter
640///
641///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DAC)
642pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
643impl core::fmt::Debug for DAC {
644    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
645        f.debug_struct("DAC").finish()
646    }
647}
648///Digital-to-analog converter
649pub mod dac;
650///DMA controller
651///
652///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DMA1)
653pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_6000>;
654impl core::fmt::Debug for DMA1 {
655    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
656        f.debug_struct("DMA1").finish()
657    }
658}
659///DMA controller
660pub mod dma1;
661///DMA controller
662///
663///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#DMA1)
664pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_6400>;
665impl core::fmt::Debug for DMA2 {
666    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
667        f.debug_struct("DMA2").finish()
668    }
669}
670///DMA controller
671pub use self::dma1 as dma2;
672///External interrupt/event controller
673///
674///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#EXTI)
675pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
676impl core::fmt::Debug for EXTI {
677    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
678        f.debug_struct("EXTI").finish()
679    }
680}
681///External interrupt/event controller
682pub mod exti;
683///fast-mode Inter-integrated circuit
684///
685///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FMPI2C1)
686pub type FMPI2C1 = crate::Periph<fmpi2c1::RegisterBlock, 0x4000_6000>;
687impl core::fmt::Debug for FMPI2C1 {
688    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
689        f.debug_struct("FMPI2C1").finish()
690    }
691}
692///fast-mode Inter-integrated circuit
693pub mod fmpi2c1;
694///FLASH
695///
696///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FLASH)
697pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
698impl core::fmt::Debug for FLASH {
699    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
700        f.debug_struct("FLASH").finish()
701    }
702}
703///FLASH
704pub mod flash;
705///General purpose timers
706///
707///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM12)
708pub type TIM12 = crate::Periph<tim12::RegisterBlock, 0x4000_1800>;
709impl core::fmt::Debug for TIM12 {
710    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
711        f.debug_struct("TIM12").finish()
712    }
713}
714///General purpose timers
715pub mod tim12;
716///General-purpose-timers
717///
718///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
719pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
720impl core::fmt::Debug for TIM10 {
721    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
722        f.debug_struct("TIM10").finish()
723    }
724}
725///General-purpose-timers
726pub mod tim10;
727///General purpose timers
728///
729///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
730pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
731impl core::fmt::Debug for TIM13 {
732    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
733        f.debug_struct("TIM13").finish()
734    }
735}
736///General purpose timers
737pub use self::tim10 as tim13;
738///General-purpose-timers
739///
740///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM10)
741pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
742impl core::fmt::Debug for TIM14 {
743    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
744        f.debug_struct("TIM14").finish()
745    }
746}
747///General-purpose-timers
748pub use self::tim10 as tim14;
749///General purpose timers
750///
751///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM12)
752pub type TIM9 = crate::Periph<tim12::RegisterBlock, 0x4001_4000>;
753impl core::fmt::Debug for TIM9 {
754    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
755        f.debug_struct("TIM9").finish()
756    }
757}
758///General purpose timers
759pub use self::tim12 as tim9;
760///General purpose timers
761///
762///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM3)
763pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
764impl core::fmt::Debug for TIM3 {
765    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
766        f.debug_struct("TIM3").finish()
767    }
768}
769///General purpose timers
770pub mod tim3;
771///General purpose timers
772///
773///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM3)
774pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
775impl core::fmt::Debug for TIM4 {
776    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
777        f.debug_struct("TIM4").finish()
778    }
779}
780///General purpose timers
781pub use self::tim3 as tim4;
782///General purpose timers
783///
784///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM2)
785pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
786impl core::fmt::Debug for TIM2 {
787    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
788        f.debug_struct("TIM2").finish()
789    }
790}
791///General purpose timers
792pub mod tim2;
793///General-purpose I/Os
794///
795///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
796pub type GPIOF = crate::Periph<gpiof::RegisterBlock, 0x4002_1400>;
797impl core::fmt::Debug for GPIOF {
798    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
799        f.debug_struct("GPIOF").finish()
800    }
801}
802///General-purpose I/Os
803pub mod gpiof;
804///General-purpose I/Os
805///
806///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
807pub type GPIOH = crate::Periph<gpiof::RegisterBlock, 0x4002_1c00>;
808impl core::fmt::Debug for GPIOH {
809    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
810        f.debug_struct("GPIOH").finish()
811    }
812}
813///General-purpose I/Os
814pub use self::gpiof as gpioh;
815///General-purpose I/Os
816///
817///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
818pub type GPIOE = crate::Periph<gpiof::RegisterBlock, 0x4002_1000>;
819impl core::fmt::Debug for GPIOE {
820    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
821        f.debug_struct("GPIOE").finish()
822    }
823}
824///General-purpose I/Os
825pub use self::gpiof as gpioe;
826///General-purpose I/Os
827///
828///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
829pub type GPIOC = crate::Periph<gpiof::RegisterBlock, 0x4002_0800>;
830impl core::fmt::Debug for GPIOC {
831    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
832        f.debug_struct("GPIOC").finish()
833    }
834}
835///General-purpose I/Os
836pub use self::gpiof as gpioc;
837///General-purpose I/Os
838///
839///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
840pub type GPIOG = crate::Periph<gpiof::RegisterBlock, 0x4002_1800>;
841impl core::fmt::Debug for GPIOG {
842    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
843        f.debug_struct("GPIOG").finish()
844    }
845}
846///General-purpose I/Os
847pub use self::gpiof as gpiog;
848///General-purpose I/Os
849///
850///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOF)
851pub type GPIOD = crate::Periph<gpiof::RegisterBlock, 0x4002_0c00>;
852impl core::fmt::Debug for GPIOD {
853    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
854        f.debug_struct("GPIOD").finish()
855    }
856}
857///General-purpose I/Os
858pub use self::gpiof as gpiod;
859///General-purpose I/Os
860///
861///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOB)
862pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
863impl core::fmt::Debug for GPIOB {
864    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
865        f.debug_struct("GPIOB").finish()
866    }
867}
868///General-purpose I/Os
869pub mod gpiob;
870///General-purpose I/Os
871///
872///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#GPIOA)
873pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
874impl core::fmt::Debug for GPIOA {
875    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
876        f.debug_struct("GPIOA").finish()
877    }
878}
879///General-purpose I/Os
880pub mod gpioa;
881///General-purpose-timers
882///
883///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM11)
884pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
885impl core::fmt::Debug for TIM11 {
886    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
887        f.debug_struct("TIM11").finish()
888    }
889}
890///General-purpose-timers
891pub mod tim11;
892///General-purpose-timers
893///
894///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#TIM5)
895pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
896impl core::fmt::Debug for TIM5 {
897    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
898        f.debug_struct("TIM5").finish()
899    }
900}
901///General-purpose-timers
902pub mod tim5;
903///Independent watchdog
904///
905///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#IWDG)
906pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
907impl core::fmt::Debug for IWDG {
908    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
909        f.debug_struct("IWDG").finish()
910    }
911}
912///Independent watchdog
913pub mod iwdg;
914///Serial peripheral interface
915///
916///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
917pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
918impl core::fmt::Debug for I2S2EXT {
919    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
920        f.debug_struct("I2S2EXT").finish()
921    }
922}
923///Serial peripheral interface
924pub use self::spi1 as i2s2ext;
925///Inter-integrated circuit
926///
927///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
928pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
929impl core::fmt::Debug for I2C1 {
930    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
931        f.debug_struct("I2C1").finish()
932    }
933}
934///Inter-integrated circuit
935pub mod i2c1;
936///Inter-integrated circuit
937///
938///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
939pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
940impl core::fmt::Debug for I2C2 {
941    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
942        f.debug_struct("I2C2").finish()
943    }
944}
945///Inter-integrated circuit
946pub use self::i2c1 as i2c2;
947///Inter-integrated circuit
948///
949///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#I2C1)
950pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
951impl core::fmt::Debug for I2C3 {
952    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
953        f.debug_struct("I2C3").finish()
954    }
955}
956///Inter-integrated circuit
957pub use self::i2c1 as i2c3;
958///Low power timer
959///
960///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM)
961pub type LPTIM = crate::Periph<lptim::RegisterBlock, 0x4000_2400>;
962impl core::fmt::Debug for LPTIM {
963    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
964        f.debug_struct("LPTIM").finish()
965    }
966}
967///Low power timer
968pub mod lptim;
969///Power control
970///
971///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#PWR)
972pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
973impl core::fmt::Debug for PWR {
974    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
975        f.debug_struct("PWR").finish()
976    }
977}
978///Power control
979pub mod pwr;
980///QuadSPI interface
981///
982///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#QUADSPI)
983pub type QUADSPI = crate::Periph<quadspi::RegisterBlock, 0xa000_1000>;
984impl core::fmt::Debug for QUADSPI {
985    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
986        f.debug_struct("QUADSPI").finish()
987    }
988}
989///QuadSPI interface
990pub mod quadspi;
991///Random number generator
992///
993///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RNG)
994pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
995impl core::fmt::Debug for RNG {
996    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
997        f.debug_struct("RNG").finish()
998    }
999}
1000///Random number generator
1001pub mod rng;
1002///Real-time clock
1003///
1004///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RTC)
1005pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
1006impl core::fmt::Debug for RTC {
1007    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1008        f.debug_struct("RTC").finish()
1009    }
1010}
1011///Real-time clock
1012pub mod rtc;
1013///Reset and clock control
1014///
1015///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#RCC)
1016pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
1017impl core::fmt::Debug for RCC {
1018    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1019        f.debug_struct("RCC").finish()
1020    }
1021}
1022///Reset and clock control
1023pub mod rcc;
1024///Secure digital input/output interface
1025///
1026///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SDIO)
1027pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
1028impl core::fmt::Debug for SDIO {
1029    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1030        f.debug_struct("SDIO").finish()
1031    }
1032}
1033///Secure digital input/output interface
1034pub mod sdio;
1035///Serial audio interface
1036///
1037///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SAI)
1038pub type SAI = crate::Periph<sai::RegisterBlock, 0x4001_5800>;
1039impl core::fmt::Debug for SAI {
1040    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1041        f.debug_struct("SAI").finish()
1042    }
1043}
1044///Serial audio interface
1045pub mod sai;
1046///Serial peripheral interface
1047///
1048///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1049pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
1050impl core::fmt::Debug for SPI1 {
1051    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1052        f.debug_struct("SPI1").finish()
1053    }
1054}
1055///Serial peripheral interface
1056pub mod spi1;
1057///Serial peripheral interface
1058///
1059///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1060pub type SPI5 = crate::Periph<spi1::RegisterBlock, 0x4001_5000>;
1061impl core::fmt::Debug for SPI5 {
1062    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1063        f.debug_struct("SPI5").finish()
1064    }
1065}
1066///Serial peripheral interface
1067pub use self::spi1 as spi5;
1068///Serial peripheral interface
1069///
1070///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1071pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3400>;
1072impl core::fmt::Debug for SPI4 {
1073    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1074        f.debug_struct("SPI4").finish()
1075    }
1076}
1077///Serial peripheral interface
1078pub use self::spi1 as spi4;
1079///Serial peripheral interface
1080///
1081///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1082pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
1083impl core::fmt::Debug for SPI2 {
1084    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1085        f.debug_struct("SPI2").finish()
1086    }
1087}
1088///Serial peripheral interface
1089pub use self::spi1 as spi2;
1090///Serial peripheral interface
1091///
1092///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1093pub type SPI6 = crate::Periph<spi1::RegisterBlock, 0x4001_5400>;
1094impl core::fmt::Debug for SPI6 {
1095    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1096        f.debug_struct("SPI6").finish()
1097    }
1098}
1099///Serial peripheral interface
1100pub use self::spi1 as spi6;
1101///Serial peripheral interface
1102///
1103///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1104pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
1105impl core::fmt::Debug for SPI3 {
1106    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1107        f.debug_struct("SPI3").finish()
1108    }
1109}
1110///Serial peripheral interface
1111pub use self::spi1 as spi3;
1112///Serial peripheral interface
1113///
1114///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SPI1)
1115pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
1116impl core::fmt::Debug for I2S3EXT {
1117    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1118        f.debug_struct("I2S3EXT").finish()
1119    }
1120}
1121///Serial peripheral interface
1122pub use self::spi1 as i2s3ext;
1123///System configuration controller
1124///
1125///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#SYSCFG)
1126pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
1127impl core::fmt::Debug for SYSCFG {
1128    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1129        f.debug_struct("SYSCFG").finish()
1130    }
1131}
1132///System configuration controller
1133pub mod syscfg;
1134///Universal synchronous asynchronous receiver transmitter
1135///
1136///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
1137pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
1138impl core::fmt::Debug for USART1 {
1139    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1140        f.debug_struct("USART1").finish()
1141    }
1142}
1143///Universal synchronous asynchronous receiver transmitter
1144pub mod usart1;
1145///Universal synchronous asynchronous receiver transmitter
1146///
1147///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
1148pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
1149impl core::fmt::Debug for USART3 {
1150    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1151        f.debug_struct("USART3").finish()
1152    }
1153}
1154///Universal synchronous asynchronous receiver transmitter
1155pub use self::usart1 as usart3;
1156///Universal synchronous asynchronous receiver transmitter
1157///
1158///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
1159pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
1160impl core::fmt::Debug for USART6 {
1161    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1162        f.debug_struct("USART6").finish()
1163    }
1164}
1165///Universal synchronous asynchronous receiver transmitter
1166pub use self::usart1 as usart6;
1167///Universal synchronous asynchronous receiver transmitter
1168///
1169///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#USART1)
1170pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
1171impl core::fmt::Debug for USART2 {
1172    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1173        f.debug_struct("USART2").finish()
1174    }
1175}
1176///Universal synchronous asynchronous receiver transmitter
1177pub use self::usart1 as usart2;
1178///Universal synchronous asynchronous receiver transmitter
1179///
1180///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1181pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
1182impl core::fmt::Debug for UART4 {
1183    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1184        f.debug_struct("UART4").finish()
1185    }
1186}
1187///Universal synchronous asynchronous receiver transmitter
1188pub mod uart4;
1189///Universal synchronous asynchronous receiver transmitter
1190///
1191///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1192pub type UART10 = crate::Periph<uart4::RegisterBlock, 0x4001_1c00>;
1193impl core::fmt::Debug for UART10 {
1194    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1195        f.debug_struct("UART10").finish()
1196    }
1197}
1198///Universal synchronous asynchronous receiver transmitter
1199pub use self::uart4 as uart10;
1200///Universal synchronous asynchronous receiver transmitter
1201///
1202///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1203pub type UART9 = crate::Periph<uart4::RegisterBlock, 0x4001_1800>;
1204impl core::fmt::Debug for UART9 {
1205    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1206        f.debug_struct("UART9").finish()
1207    }
1208}
1209///Universal synchronous asynchronous receiver transmitter
1210pub use self::uart4 as uart9;
1211///USB on the go full speed
1212///
1213///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_DEVICE)
1214pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
1215impl core::fmt::Debug for OTG_FS_DEVICE {
1216    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1217        f.debug_struct("OTG_FS_DEVICE").finish()
1218    }
1219}
1220///USB on the go full speed
1221pub mod otg_fs_device;
1222///USB on the go full speed
1223///
1224///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_HOST)
1225pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
1226impl core::fmt::Debug for OTG_FS_HOST {
1227    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1228        f.debug_struct("OTG_FS_HOST").finish()
1229    }
1230}
1231///USB on the go full speed
1232pub mod otg_fs_host;
1233///USB on the go full speed
1234///
1235///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_PWRCLK)
1236pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
1237impl core::fmt::Debug for OTG_FS_PWRCLK {
1238    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1239        f.debug_struct("OTG_FS_PWRCLK").finish()
1240    }
1241}
1242///USB on the go full speed
1243pub mod otg_fs_pwrclk;
1244///USB on the go full speed
1245///
1246///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#OTG_FS_GLOBAL)
1247pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
1248impl core::fmt::Debug for OTG_FS_GLOBAL {
1249    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1250        f.debug_struct("OTG_FS_GLOBAL").finish()
1251    }
1252}
1253///USB on the go full speed
1254pub mod otg_fs_global;
1255///Window watchdog
1256///
1257///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#WWDG)
1258pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
1259impl core::fmt::Debug for WWDG {
1260    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1261        f.debug_struct("WWDG").finish()
1262    }
1263}
1264///Window watchdog
1265pub mod wwdg;
1266///Flexible static memory controller
1267///
1268///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FSMC)
1269pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
1270impl core::fmt::Debug for FSMC {
1271    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1272        f.debug_struct("FSMC").finish()
1273    }
1274}
1275///Flexible static memory controller
1276pub mod fsmc;
1277///ADC common registers
1278///
1279///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#ADC_Common)
1280pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
1281impl core::fmt::Debug for ADC_COMMON {
1282    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1283        f.debug_struct("ADC_COMMON").finish()
1284    }
1285}
1286///ADC common registers
1287pub mod adc_common;
1288///Universal synchronous asynchronous receiver transmitter
1289///
1290///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1291pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
1292impl core::fmt::Debug for UART5 {
1293    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1294        f.debug_struct("UART5").finish()
1295    }
1296}
1297///Universal synchronous asynchronous receiver transmitter
1298pub use self::uart4 as uart5;
1299///Universal synchronous asynchronous receiver transmitter
1300///
1301///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1302pub type UART7 = crate::Periph<uart4::RegisterBlock, 0x4000_7800>;
1303impl core::fmt::Debug for UART7 {
1304    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1305        f.debug_struct("UART7").finish()
1306    }
1307}
1308///Universal synchronous asynchronous receiver transmitter
1309pub use self::uart4 as uart7;
1310///Universal synchronous asynchronous receiver transmitter
1311///
1312///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#UART4)
1313pub type UART8 = crate::Periph<uart4::RegisterBlock, 0x4000_7c00>;
1314impl core::fmt::Debug for UART8 {
1315    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1316        f.debug_struct("UART8").finish()
1317    }
1318}
1319///Universal synchronous asynchronous receiver transmitter
1320pub use self::uart4 as uart8;
1321#[no_mangle]
1322static mut DEVICE_PERIPHERALS: bool = false;
1323/// All the peripherals.
1324#[allow(non_snake_case)]
1325pub struct Peripherals {
1326    ///AES
1327    pub AES: AES,
1328    ///TIM1
1329    pub TIM1: TIM1,
1330    ///TIM8
1331    pub TIM8: TIM8,
1332    ///ADC1
1333    pub ADC1: ADC1,
1334    ///TIM7
1335    pub TIM7: TIM7,
1336    ///TIM6
1337    pub TIM6: TIM6,
1338    ///CAN1
1339    pub CAN1: CAN1,
1340    ///CAN2
1341    pub CAN2: CAN2,
1342    ///CAN3
1343    pub CAN3: CAN3,
1344    ///CRC
1345    pub CRC: CRC,
1346    ///DBGMCU
1347    pub DBGMCU: DBGMCU,
1348    ///DFSDM2
1349    pub DFSDM2: DFSDM2,
1350    ///DFSDM1
1351    pub DFSDM1: DFSDM1,
1352    ///DAC
1353    pub DAC: DAC,
1354    ///DMA1
1355    pub DMA1: DMA1,
1356    ///DMA2
1357    pub DMA2: DMA2,
1358    ///EXTI
1359    pub EXTI: EXTI,
1360    ///FMPI2C1
1361    pub FMPI2C1: FMPI2C1,
1362    ///FLASH
1363    pub FLASH: FLASH,
1364    ///TIM12
1365    pub TIM12: TIM12,
1366    ///TIM10
1367    pub TIM10: TIM10,
1368    ///TIM13
1369    pub TIM13: TIM13,
1370    ///TIM14
1371    pub TIM14: TIM14,
1372    ///TIM9
1373    pub TIM9: TIM9,
1374    ///TIM3
1375    pub TIM3: TIM3,
1376    ///TIM4
1377    pub TIM4: TIM4,
1378    ///TIM2
1379    pub TIM2: TIM2,
1380    ///GPIOF
1381    pub GPIOF: GPIOF,
1382    ///GPIOH
1383    pub GPIOH: GPIOH,
1384    ///GPIOE
1385    pub GPIOE: GPIOE,
1386    ///GPIOC
1387    pub GPIOC: GPIOC,
1388    ///GPIOG
1389    pub GPIOG: GPIOG,
1390    ///GPIOD
1391    pub GPIOD: GPIOD,
1392    ///GPIOB
1393    pub GPIOB: GPIOB,
1394    ///GPIOA
1395    pub GPIOA: GPIOA,
1396    ///TIM11
1397    pub TIM11: TIM11,
1398    ///TIM5
1399    pub TIM5: TIM5,
1400    ///IWDG
1401    pub IWDG: IWDG,
1402    ///I2S2ext
1403    pub I2S2EXT: I2S2EXT,
1404    ///I2C1
1405    pub I2C1: I2C1,
1406    ///I2C2
1407    pub I2C2: I2C2,
1408    ///I2C3
1409    pub I2C3: I2C3,
1410    ///LPTIM
1411    pub LPTIM: LPTIM,
1412    ///PWR
1413    pub PWR: PWR,
1414    ///QUADSPI
1415    pub QUADSPI: QUADSPI,
1416    ///RNG
1417    pub RNG: RNG,
1418    ///RTC
1419    pub RTC: RTC,
1420    ///RCC
1421    pub RCC: RCC,
1422    ///SDIO
1423    pub SDIO: SDIO,
1424    ///SAI
1425    pub SAI: SAI,
1426    ///SPI1
1427    pub SPI1: SPI1,
1428    ///SPI5
1429    pub SPI5: SPI5,
1430    ///SPI4
1431    pub SPI4: SPI4,
1432    ///SPI2
1433    pub SPI2: SPI2,
1434    ///SPI6
1435    pub SPI6: SPI6,
1436    ///SPI3
1437    pub SPI3: SPI3,
1438    ///I2S3ext
1439    pub I2S3EXT: I2S3EXT,
1440    ///SYSCFG
1441    pub SYSCFG: SYSCFG,
1442    ///USART1
1443    pub USART1: USART1,
1444    ///USART3
1445    pub USART3: USART3,
1446    ///USART6
1447    pub USART6: USART6,
1448    ///USART2
1449    pub USART2: USART2,
1450    ///UART4
1451    pub UART4: UART4,
1452    ///UART10
1453    pub UART10: UART10,
1454    ///UART9
1455    pub UART9: UART9,
1456    ///OTG_FS_DEVICE
1457    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1458    ///OTG_FS_HOST
1459    pub OTG_FS_HOST: OTG_FS_HOST,
1460    ///OTG_FS_PWRCLK
1461    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1462    ///OTG_FS_GLOBAL
1463    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1464    ///WWDG
1465    pub WWDG: WWDG,
1466    ///FSMC
1467    pub FSMC: FSMC,
1468    ///ADC_Common
1469    pub ADC_COMMON: ADC_COMMON,
1470    ///UART5
1471    pub UART5: UART5,
1472    ///UART7
1473    pub UART7: UART7,
1474    ///UART8
1475    pub UART8: UART8,
1476}
1477impl Peripherals {
1478    /// Returns all the peripherals *once*.
1479    #[cfg(feature = "critical-section")]
1480    #[inline]
1481    pub fn take() -> Option<Self> {
1482        critical_section::with(|_| {
1483            if unsafe { DEVICE_PERIPHERALS } {
1484                return None;
1485            }
1486            Some(unsafe { Peripherals::steal() })
1487        })
1488    }
1489    /// Unchecked version of `Peripherals::take`.
1490    ///
1491    /// # Safety
1492    ///
1493    /// Each of the returned peripherals must be used at most once.
1494    #[inline]
1495    pub unsafe fn steal() -> Self {
1496        DEVICE_PERIPHERALS = true;
1497        Peripherals {
1498            AES: AES::steal(),
1499            TIM1: TIM1::steal(),
1500            TIM8: TIM8::steal(),
1501            ADC1: ADC1::steal(),
1502            TIM7: TIM7::steal(),
1503            TIM6: TIM6::steal(),
1504            CAN1: CAN1::steal(),
1505            CAN2: CAN2::steal(),
1506            CAN3: CAN3::steal(),
1507            CRC: CRC::steal(),
1508            DBGMCU: DBGMCU::steal(),
1509            DFSDM2: DFSDM2::steal(),
1510            DFSDM1: DFSDM1::steal(),
1511            DAC: DAC::steal(),
1512            DMA1: DMA1::steal(),
1513            DMA2: DMA2::steal(),
1514            EXTI: EXTI::steal(),
1515            FMPI2C1: FMPI2C1::steal(),
1516            FLASH: FLASH::steal(),
1517            TIM12: TIM12::steal(),
1518            TIM10: TIM10::steal(),
1519            TIM13: TIM13::steal(),
1520            TIM14: TIM14::steal(),
1521            TIM9: TIM9::steal(),
1522            TIM3: TIM3::steal(),
1523            TIM4: TIM4::steal(),
1524            TIM2: TIM2::steal(),
1525            GPIOF: GPIOF::steal(),
1526            GPIOH: GPIOH::steal(),
1527            GPIOE: GPIOE::steal(),
1528            GPIOC: GPIOC::steal(),
1529            GPIOG: GPIOG::steal(),
1530            GPIOD: GPIOD::steal(),
1531            GPIOB: GPIOB::steal(),
1532            GPIOA: GPIOA::steal(),
1533            TIM11: TIM11::steal(),
1534            TIM5: TIM5::steal(),
1535            IWDG: IWDG::steal(),
1536            I2S2EXT: I2S2EXT::steal(),
1537            I2C1: I2C1::steal(),
1538            I2C2: I2C2::steal(),
1539            I2C3: I2C3::steal(),
1540            LPTIM: LPTIM::steal(),
1541            PWR: PWR::steal(),
1542            QUADSPI: QUADSPI::steal(),
1543            RNG: RNG::steal(),
1544            RTC: RTC::steal(),
1545            RCC: RCC::steal(),
1546            SDIO: SDIO::steal(),
1547            SAI: SAI::steal(),
1548            SPI1: SPI1::steal(),
1549            SPI5: SPI5::steal(),
1550            SPI4: SPI4::steal(),
1551            SPI2: SPI2::steal(),
1552            SPI6: SPI6::steal(),
1553            SPI3: SPI3::steal(),
1554            I2S3EXT: I2S3EXT::steal(),
1555            SYSCFG: SYSCFG::steal(),
1556            USART1: USART1::steal(),
1557            USART3: USART3::steal(),
1558            USART6: USART6::steal(),
1559            USART2: USART2::steal(),
1560            UART4: UART4::steal(),
1561            UART10: UART10::steal(),
1562            UART9: UART9::steal(),
1563            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1564            OTG_FS_HOST: OTG_FS_HOST::steal(),
1565            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1566            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1567            WWDG: WWDG::steal(),
1568            FSMC: FSMC::steal(),
1569            ADC_COMMON: ADC_COMMON::steal(),
1570            UART5: UART5::steal(),
1571            UART7: UART7::steal(),
1572            UART8: UART8::steal(),
1573        }
1574    }
1575}
stm32f4_staging/stm32f413/mod.rs

stm32f4_staging/stm32f413/
mod.rs
