stm32f4_staging/stm32f413/
lptim.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    isr: ISR,
6    icr: ICR,
7    ier: IER,
8    cfgr: CFGR,
9    cr: CR,
10    cmp: CMP,
11    arr: ARR,
12    cnt: CNT,
13}
14impl RegisterBlock {
15    ///0x00 - Interrupt and Status Register
16    #[inline(always)]
17    pub const fn isr(&self) -> &ISR {
18        &self.isr
19    }
20    ///0x04 - Interrupt Clear Register
21    #[inline(always)]
22    pub const fn icr(&self) -> &ICR {
23        &self.icr
24    }
25    ///0x08 - Interrupt Enable Register
26    #[inline(always)]
27    pub const fn ier(&self) -> &IER {
28        &self.ier
29    }
30    ///0x0c - Configuration Register
31    #[inline(always)]
32    pub const fn cfgr(&self) -> &CFGR {
33        &self.cfgr
34    }
35    ///0x10 - Control Register
36    #[inline(always)]
37    pub const fn cr(&self) -> &CR {
38        &self.cr
39    }
40    ///0x14 - Compare Register
41    #[inline(always)]
42    pub const fn cmp(&self) -> &CMP {
43        &self.cmp
44    }
45    ///0x18 - Autoreload Register
46    #[inline(always)]
47    pub const fn arr(&self) -> &ARR {
48        &self.arr
49    }
50    ///0x1c - Counter Register
51    #[inline(always)]
52    pub const fn cnt(&self) -> &CNT {
53        &self.cnt
54    }
55}
56/**ISR (r) register accessor: Interrupt and Status Register
57
58You can [`read`](crate::Reg::read) this register and get [`isr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
59
60See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:ISR)
61
62For information about available fields see [`mod@isr`] module*/
63pub type ISR = crate::Reg<isr::ISRrs>;
64///Interrupt and Status Register
65pub mod isr;
66/**ICR (w) register accessor: Interrupt Clear Register
67
68You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
69
70See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:ICR)
71
72For information about available fields see [`mod@icr`] module*/
73pub type ICR = crate::Reg<icr::ICRrs>;
74///Interrupt Clear Register
75pub mod icr;
76/**IER (rw) register accessor: Interrupt Enable Register
77
78You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
79
80See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:IER)
81
82For information about available fields see [`mod@ier`] module*/
83pub type IER = crate::Reg<ier::IERrs>;
84///Interrupt Enable Register
85pub mod ier;
86/**CFGR (rw) register accessor: Configuration Register
87
88You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
89
90See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:CFGR)
91
92For information about available fields see [`mod@cfgr`] module*/
93pub type CFGR = crate::Reg<cfgr::CFGRrs>;
94///Configuration Register
95pub mod cfgr;
96/**CR (rw) register accessor: Control Register
97
98You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
99
100See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:CR)
101
102For information about available fields see [`mod@cr`] module*/
103pub type CR = crate::Reg<cr::CRrs>;
104///Control Register
105pub mod cr;
106/**CMP (rw) register accessor: Compare Register
107
108You can [`read`](crate::Reg::read) this register and get [`cmp::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
109
110See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:CMP)
111
112For information about available fields see [`mod@cmp`] module*/
113pub type CMP = crate::Reg<cmp::CMPrs>;
114///Compare Register
115pub mod cmp;
116/**ARR (rw) register accessor: Autoreload Register
117
118You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
119
120See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:ARR)
121
122For information about available fields see [`mod@arr`] module*/
123pub type ARR = crate::Reg<arr::ARRrs>;
124///Autoreload Register
125pub mod arr;
126/**CNT (r) register accessor: Counter Register
127
128You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
129
130See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#LPTIM:CNT)
131
132For information about available fields see [`mod@cnt`] module*/
133pub type CNT = crate::Reg<cnt::CNTrs>;
134///Counter Register
135pub mod cnt;
stm32f4_staging/stm32f413/lptim.rs

stm32f4_staging/stm32f413/
lptim.rs
