stm32f4_staging/stm32f413/flash/
acr.rs

1///Register `ACR` reader
2pub type R = crate::R<ACRrs>;
3///Register `ACR` writer
4pub type W = crate::W<ACRrs>;
5/**Latency
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum LATENCY {
12    ///0: 0 wait states
13    Ws0 = 0,
14    ///1: 1 wait states
15    Ws1 = 1,
16    ///2: 2 wait states
17    Ws2 = 2,
18    ///3: 3 wait states
19    Ws3 = 3,
20    ///4: 4 wait states
21    Ws4 = 4,
22    ///5: 5 wait states
23    Ws5 = 5,
24    ///6: 6 wait states
25    Ws6 = 6,
26    ///7: 7 wait states
27    Ws7 = 7,
28    ///8: 8 wait states
29    Ws8 = 8,
30    ///9: 9 wait states
31    Ws9 = 9,
32    ///10: 10 wait states
33    Ws10 = 10,
34    ///11: 11 wait states
35    Ws11 = 11,
36    ///12: 12 wait states
37    Ws12 = 12,
38    ///13: 13 wait states
39    Ws13 = 13,
40    ///14: 14 wait states
41    Ws14 = 14,
42    ///15: 15 wait states
43    Ws15 = 15,
44}
45impl From<LATENCY> for u8 {
46    #[inline(always)]
47    fn from(variant: LATENCY) -> Self {
48        variant as _
49    }
50}
51impl crate::FieldSpec for LATENCY {
52    type Ux = u8;
53}
54impl crate::IsEnum for LATENCY {}
55///Field `LATENCY` reader - Latency
56pub type LATENCY_R = crate::FieldReader<LATENCY>;
57impl LATENCY_R {
58    ///Get enumerated values variant
59    #[inline(always)]
60    pub const fn variant(&self) -> LATENCY {
61        match self.bits {
62            0 => LATENCY::Ws0,
63            1 => LATENCY::Ws1,
64            2 => LATENCY::Ws2,
65            3 => LATENCY::Ws3,
66            4 => LATENCY::Ws4,
67            5 => LATENCY::Ws5,
68            6 => LATENCY::Ws6,
69            7 => LATENCY::Ws7,
70            8 => LATENCY::Ws8,
71            9 => LATENCY::Ws9,
72            10 => LATENCY::Ws10,
73            11 => LATENCY::Ws11,
74            12 => LATENCY::Ws12,
75            13 => LATENCY::Ws13,
76            14 => LATENCY::Ws14,
77            15 => LATENCY::Ws15,
78            _ => unreachable!(),
79        }
80    }
81    ///0 wait states
82    #[inline(always)]
83    pub fn is_ws0(&self) -> bool {
84        *self == LATENCY::Ws0
85    }
86    ///1 wait states
87    #[inline(always)]
88    pub fn is_ws1(&self) -> bool {
89        *self == LATENCY::Ws1
90    }
91    ///2 wait states
92    #[inline(always)]
93    pub fn is_ws2(&self) -> bool {
94        *self == LATENCY::Ws2
95    }
96    ///3 wait states
97    #[inline(always)]
98    pub fn is_ws3(&self) -> bool {
99        *self == LATENCY::Ws3
100    }
101    ///4 wait states
102    #[inline(always)]
103    pub fn is_ws4(&self) -> bool {
104        *self == LATENCY::Ws4
105    }
106    ///5 wait states
107    #[inline(always)]
108    pub fn is_ws5(&self) -> bool {
109        *self == LATENCY::Ws5
110    }
111    ///6 wait states
112    #[inline(always)]
113    pub fn is_ws6(&self) -> bool {
114        *self == LATENCY::Ws6
115    }
116    ///7 wait states
117    #[inline(always)]
118    pub fn is_ws7(&self) -> bool {
119        *self == LATENCY::Ws7
120    }
121    ///8 wait states
122    #[inline(always)]
123    pub fn is_ws8(&self) -> bool {
124        *self == LATENCY::Ws8
125    }
126    ///9 wait states
127    #[inline(always)]
128    pub fn is_ws9(&self) -> bool {
129        *self == LATENCY::Ws9
130    }
131    ///10 wait states
132    #[inline(always)]
133    pub fn is_ws10(&self) -> bool {
134        *self == LATENCY::Ws10
135    }
136    ///11 wait states
137    #[inline(always)]
138    pub fn is_ws11(&self) -> bool {
139        *self == LATENCY::Ws11
140    }
141    ///12 wait states
142    #[inline(always)]
143    pub fn is_ws12(&self) -> bool {
144        *self == LATENCY::Ws12
145    }
146    ///13 wait states
147    #[inline(always)]
148    pub fn is_ws13(&self) -> bool {
149        *self == LATENCY::Ws13
150    }
151    ///14 wait states
152    #[inline(always)]
153    pub fn is_ws14(&self) -> bool {
154        *self == LATENCY::Ws14
155    }
156    ///15 wait states
157    #[inline(always)]
158    pub fn is_ws15(&self) -> bool {
159        *self == LATENCY::Ws15
160    }
161}
162///Field `LATENCY` writer - Latency
163pub type LATENCY_W<'a, REG> = crate::FieldWriter<'a, REG, 4, LATENCY, crate::Safe>;
164impl<'a, REG> LATENCY_W<'a, REG>
165where
166    REG: crate::Writable + crate::RegisterSpec,
167    REG::Ux: From<u8>,
168{
169    ///0 wait states
170    #[inline(always)]
171    pub fn ws0(self) -> &'a mut crate::W<REG> {
172        self.variant(LATENCY::Ws0)
173    }
174    ///1 wait states
175    #[inline(always)]
176    pub fn ws1(self) -> &'a mut crate::W<REG> {
177        self.variant(LATENCY::Ws1)
178    }
179    ///2 wait states
180    #[inline(always)]
181    pub fn ws2(self) -> &'a mut crate::W<REG> {
182        self.variant(LATENCY::Ws2)
183    }
184    ///3 wait states
185    #[inline(always)]
186    pub fn ws3(self) -> &'a mut crate::W<REG> {
187        self.variant(LATENCY::Ws3)
188    }
189    ///4 wait states
190    #[inline(always)]
191    pub fn ws4(self) -> &'a mut crate::W<REG> {
192        self.variant(LATENCY::Ws4)
193    }
194    ///5 wait states
195    #[inline(always)]
196    pub fn ws5(self) -> &'a mut crate::W<REG> {
197        self.variant(LATENCY::Ws5)
198    }
199    ///6 wait states
200    #[inline(always)]
201    pub fn ws6(self) -> &'a mut crate::W<REG> {
202        self.variant(LATENCY::Ws6)
203    }
204    ///7 wait states
205    #[inline(always)]
206    pub fn ws7(self) -> &'a mut crate::W<REG> {
207        self.variant(LATENCY::Ws7)
208    }
209    ///8 wait states
210    #[inline(always)]
211    pub fn ws8(self) -> &'a mut crate::W<REG> {
212        self.variant(LATENCY::Ws8)
213    }
214    ///9 wait states
215    #[inline(always)]
216    pub fn ws9(self) -> &'a mut crate::W<REG> {
217        self.variant(LATENCY::Ws9)
218    }
219    ///10 wait states
220    #[inline(always)]
221    pub fn ws10(self) -> &'a mut crate::W<REG> {
222        self.variant(LATENCY::Ws10)
223    }
224    ///11 wait states
225    #[inline(always)]
226    pub fn ws11(self) -> &'a mut crate::W<REG> {
227        self.variant(LATENCY::Ws11)
228    }
229    ///12 wait states
230    #[inline(always)]
231    pub fn ws12(self) -> &'a mut crate::W<REG> {
232        self.variant(LATENCY::Ws12)
233    }
234    ///13 wait states
235    #[inline(always)]
236    pub fn ws13(self) -> &'a mut crate::W<REG> {
237        self.variant(LATENCY::Ws13)
238    }
239    ///14 wait states
240    #[inline(always)]
241    pub fn ws14(self) -> &'a mut crate::W<REG> {
242        self.variant(LATENCY::Ws14)
243    }
244    ///15 wait states
245    #[inline(always)]
246    pub fn ws15(self) -> &'a mut crate::W<REG> {
247        self.variant(LATENCY::Ws15)
248    }
249}
250/**Prefetch enable
251
252Value on reset: 0*/
253#[cfg_attr(feature = "defmt", derive(defmt::Format))]
254#[derive(Clone, Copy, Debug, PartialEq, Eq)]
255pub enum PRFTEN {
256    ///0: Prefetch is disabled
257    Disabled = 0,
258    ///1: Prefetch is enabled
259    Enabled = 1,
260}
261impl From<PRFTEN> for bool {
262    #[inline(always)]
263    fn from(variant: PRFTEN) -> Self {
264        variant as u8 != 0
265    }
266}
267///Field `PRFTEN` reader - Prefetch enable
268pub type PRFTEN_R = crate::BitReader<PRFTEN>;
269impl PRFTEN_R {
270    ///Get enumerated values variant
271    #[inline(always)]
272    pub const fn variant(&self) -> PRFTEN {
273        match self.bits {
274            false => PRFTEN::Disabled,
275            true => PRFTEN::Enabled,
276        }
277    }
278    ///Prefetch is disabled
279    #[inline(always)]
280    pub fn is_disabled(&self) -> bool {
281        *self == PRFTEN::Disabled
282    }
283    ///Prefetch is enabled
284    #[inline(always)]
285    pub fn is_enabled(&self) -> bool {
286        *self == PRFTEN::Enabled
287    }
288}
289///Field `PRFTEN` writer - Prefetch enable
290pub type PRFTEN_W<'a, REG> = crate::BitWriter<'a, REG, PRFTEN>;
291impl<'a, REG> PRFTEN_W<'a, REG>
292where
293    REG: crate::Writable + crate::RegisterSpec,
294{
295    ///Prefetch is disabled
296    #[inline(always)]
297    pub fn disabled(self) -> &'a mut crate::W<REG> {
298        self.variant(PRFTEN::Disabled)
299    }
300    ///Prefetch is enabled
301    #[inline(always)]
302    pub fn enabled(self) -> &'a mut crate::W<REG> {
303        self.variant(PRFTEN::Enabled)
304    }
305}
306/**Instruction cache enable
307
308Value on reset: 0*/
309#[cfg_attr(feature = "defmt", derive(defmt::Format))]
310#[derive(Clone, Copy, Debug, PartialEq, Eq)]
311pub enum ICEN {
312    ///0: Instruction cache is disabled
313    Disabled = 0,
314    ///1: Instruction cache is enabled
315    Enabled = 1,
316}
317impl From<ICEN> for bool {
318    #[inline(always)]
319    fn from(variant: ICEN) -> Self {
320        variant as u8 != 0
321    }
322}
323///Field `ICEN` reader - Instruction cache enable
324pub type ICEN_R = crate::BitReader<ICEN>;
325impl ICEN_R {
326    ///Get enumerated values variant
327    #[inline(always)]
328    pub const fn variant(&self) -> ICEN {
329        match self.bits {
330            false => ICEN::Disabled,
331            true => ICEN::Enabled,
332        }
333    }
334    ///Instruction cache is disabled
335    #[inline(always)]
336    pub fn is_disabled(&self) -> bool {
337        *self == ICEN::Disabled
338    }
339    ///Instruction cache is enabled
340    #[inline(always)]
341    pub fn is_enabled(&self) -> bool {
342        *self == ICEN::Enabled
343    }
344}
345///Field `ICEN` writer - Instruction cache enable
346pub type ICEN_W<'a, REG> = crate::BitWriter<'a, REG, ICEN>;
347impl<'a, REG> ICEN_W<'a, REG>
348where
349    REG: crate::Writable + crate::RegisterSpec,
350{
351    ///Instruction cache is disabled
352    #[inline(always)]
353    pub fn disabled(self) -> &'a mut crate::W<REG> {
354        self.variant(ICEN::Disabled)
355    }
356    ///Instruction cache is enabled
357    #[inline(always)]
358    pub fn enabled(self) -> &'a mut crate::W<REG> {
359        self.variant(ICEN::Enabled)
360    }
361}
362/**Data cache enable
363
364Value on reset: 0*/
365#[cfg_attr(feature = "defmt", derive(defmt::Format))]
366#[derive(Clone, Copy, Debug, PartialEq, Eq)]
367pub enum DCEN {
368    ///0: Data cache is disabled
369    Disabled = 0,
370    ///1: Data cache is enabled
371    Enabled = 1,
372}
373impl From<DCEN> for bool {
374    #[inline(always)]
375    fn from(variant: DCEN) -> Self {
376        variant as u8 != 0
377    }
378}
379///Field `DCEN` reader - Data cache enable
380pub type DCEN_R = crate::BitReader<DCEN>;
381impl DCEN_R {
382    ///Get enumerated values variant
383    #[inline(always)]
384    pub const fn variant(&self) -> DCEN {
385        match self.bits {
386            false => DCEN::Disabled,
387            true => DCEN::Enabled,
388        }
389    }
390    ///Data cache is disabled
391    #[inline(always)]
392    pub fn is_disabled(&self) -> bool {
393        *self == DCEN::Disabled
394    }
395    ///Data cache is enabled
396    #[inline(always)]
397    pub fn is_enabled(&self) -> bool {
398        *self == DCEN::Enabled
399    }
400}
401///Field `DCEN` writer - Data cache enable
402pub type DCEN_W<'a, REG> = crate::BitWriter<'a, REG, DCEN>;
403impl<'a, REG> DCEN_W<'a, REG>
404where
405    REG: crate::Writable + crate::RegisterSpec,
406{
407    ///Data cache is disabled
408    #[inline(always)]
409    pub fn disabled(self) -> &'a mut crate::W<REG> {
410        self.variant(DCEN::Disabled)
411    }
412    ///Data cache is enabled
413    #[inline(always)]
414    pub fn enabled(self) -> &'a mut crate::W<REG> {
415        self.variant(DCEN::Enabled)
416    }
417}
418/**Instruction cache reset
419
420Value on reset: 0*/
421#[cfg_attr(feature = "defmt", derive(defmt::Format))]
422#[derive(Clone, Copy, Debug, PartialEq, Eq)]
423pub enum ICRST {
424    ///0: Instruction cache is not reset
425    NoReset = 0,
426    ///1: Instruction cache is reset
427    Reset = 1,
428}
429impl From<ICRST> for bool {
430    #[inline(always)]
431    fn from(variant: ICRST) -> Self {
432        variant as u8 != 0
433    }
434}
435///Field `ICRST` writer - Instruction cache reset
436pub type ICRST_W<'a, REG> = crate::BitWriter<'a, REG, ICRST>;
437impl<'a, REG> ICRST_W<'a, REG>
438where
439    REG: crate::Writable + crate::RegisterSpec,
440{
441    ///Instruction cache is not reset
442    #[inline(always)]
443    pub fn no_reset(self) -> &'a mut crate::W<REG> {
444        self.variant(ICRST::NoReset)
445    }
446    ///Instruction cache is reset
447    #[inline(always)]
448    pub fn reset(self) -> &'a mut crate::W<REG> {
449        self.variant(ICRST::Reset)
450    }
451}
452/**Data cache reset
453
454Value on reset: 0*/
455#[cfg_attr(feature = "defmt", derive(defmt::Format))]
456#[derive(Clone, Copy, Debug, PartialEq, Eq)]
457pub enum DCRST {
458    ///0: Data cache is not reset
459    NoReset = 0,
460    ///1: Data cache is reset
461    Reset = 1,
462}
463impl From<DCRST> for bool {
464    #[inline(always)]
465    fn from(variant: DCRST) -> Self {
466        variant as u8 != 0
467    }
468}
469///Field `DCRST` reader - Data cache reset
470pub type DCRST_R = crate::BitReader<DCRST>;
471impl DCRST_R {
472    ///Get enumerated values variant
473    #[inline(always)]
474    pub const fn variant(&self) -> DCRST {
475        match self.bits {
476            false => DCRST::NoReset,
477            true => DCRST::Reset,
478        }
479    }
480    ///Data cache is not reset
481    #[inline(always)]
482    pub fn is_no_reset(&self) -> bool {
483        *self == DCRST::NoReset
484    }
485    ///Data cache is reset
486    #[inline(always)]
487    pub fn is_reset(&self) -> bool {
488        *self == DCRST::Reset
489    }
490}
491///Field `DCRST` writer - Data cache reset
492pub type DCRST_W<'a, REG> = crate::BitWriter<'a, REG, DCRST>;
493impl<'a, REG> DCRST_W<'a, REG>
494where
495    REG: crate::Writable + crate::RegisterSpec,
496{
497    ///Data cache is not reset
498    #[inline(always)]
499    pub fn no_reset(self) -> &'a mut crate::W<REG> {
500        self.variant(DCRST::NoReset)
501    }
502    ///Data cache is reset
503    #[inline(always)]
504    pub fn reset(self) -> &'a mut crate::W<REG> {
505        self.variant(DCRST::Reset)
506    }
507}
508impl R {
509    ///Bits 0:3 - Latency
510    #[inline(always)]
511    pub fn latency(&self) -> LATENCY_R {
512        LATENCY_R::new((self.bits & 0x0f) as u8)
513    }
514    ///Bit 8 - Prefetch enable
515    #[inline(always)]
516    pub fn prften(&self) -> PRFTEN_R {
517        PRFTEN_R::new(((self.bits >> 8) & 1) != 0)
518    }
519    ///Bit 9 - Instruction cache enable
520    #[inline(always)]
521    pub fn icen(&self) -> ICEN_R {
522        ICEN_R::new(((self.bits >> 9) & 1) != 0)
523    }
524    ///Bit 10 - Data cache enable
525    #[inline(always)]
526    pub fn dcen(&self) -> DCEN_R {
527        DCEN_R::new(((self.bits >> 10) & 1) != 0)
528    }
529    ///Bit 12 - Data cache reset
530    #[inline(always)]
531    pub fn dcrst(&self) -> DCRST_R {
532        DCRST_R::new(((self.bits >> 12) & 1) != 0)
533    }
534}
535impl core::fmt::Debug for R {
536    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
537        f.debug_struct("ACR")
538            .field("latency", &self.latency())
539            .field("prften", &self.prften())
540            .field("icen", &self.icen())
541            .field("dcen", &self.dcen())
542            .field("dcrst", &self.dcrst())
543            .finish()
544    }
545}
546impl W {
547    ///Bits 0:3 - Latency
548    #[inline(always)]
549    pub fn latency(&mut self) -> LATENCY_W<ACRrs> {
550        LATENCY_W::new(self, 0)
551    }
552    ///Bit 8 - Prefetch enable
553    #[inline(always)]
554    pub fn prften(&mut self) -> PRFTEN_W<ACRrs> {
555        PRFTEN_W::new(self, 8)
556    }
557    ///Bit 9 - Instruction cache enable
558    #[inline(always)]
559    pub fn icen(&mut self) -> ICEN_W<ACRrs> {
560        ICEN_W::new(self, 9)
561    }
562    ///Bit 10 - Data cache enable
563    #[inline(always)]
564    pub fn dcen(&mut self) -> DCEN_W<ACRrs> {
565        DCEN_W::new(self, 10)
566    }
567    ///Bit 11 - Instruction cache reset
568    #[inline(always)]
569    pub fn icrst(&mut self) -> ICRST_W<ACRrs> {
570        ICRST_W::new(self, 11)
571    }
572    ///Bit 12 - Data cache reset
573    #[inline(always)]
574    pub fn dcrst(&mut self) -> DCRST_W<ACRrs> {
575        DCRST_W::new(self, 12)
576    }
577}
578/**Flash access control register
579
580You can [`read`](crate::Reg::read) this register and get [`acr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`acr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
581
582See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F413.html#FLASH:ACR)*/
583pub struct ACRrs;
584impl crate::RegisterSpec for ACRrs {
585    type Ux = u32;
586}
587///`read()` method returns [`acr::R`](R) reader structure
588impl crate::Readable for ACRrs {}
589///`write(|w| ..)` method takes [`acr::W`](W) writer structure
590impl crate::Writable for ACRrs {
591    type Safety = crate::Unsafe;
592}
593///`reset()` method sets ACR to value 0
594impl crate::Resettable for ACRrs {}
stm32f4_staging/stm32f413/flash/acr.rs

stm32f4_staging/stm32f413/flash/
acr.rs
