stm32f4_staging/stm32f407/
tim5.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved12: [u8; 0x04],
18    ccr: [CCR; 4],
19    _reserved13: [u8; 0x04],
20    dcr: DCR,
21    dmar: DMAR,
22    or: OR,
23}
24impl RegisterBlock {
25    ///0x00 - control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x04 - control register 2
31    #[inline(always)]
32    pub const fn cr2(&self) -> &CR2 {
33        &self.cr2
34    }
35    ///0x08 - slave mode control register
36    #[inline(always)]
37    pub const fn smcr(&self) -> &SMCR {
38        &self.smcr
39    }
40    ///0x0c - DMA/Interrupt enable register
41    #[inline(always)]
42    pub const fn dier(&self) -> &DIER {
43        &self.dier
44    }
45    ///0x10 - status register
46    #[inline(always)]
47    pub const fn sr(&self) -> &SR {
48        &self.sr
49    }
50    ///0x14 - event generation register
51    #[inline(always)]
52    pub const fn egr(&self) -> &EGR {
53        &self.egr
54    }
55    ///0x18 - capture/compare mode register 1 (input mode)
56    #[inline(always)]
57    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
58        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
59    }
60    ///0x18 - capture/compare mode register 1 (output mode)
61    #[inline(always)]
62    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
64    }
65    ///0x1c - capture/compare mode register 2 (input mode)
66    #[inline(always)]
67    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
68        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
69    }
70    ///0x1c - capture/compare mode register 2 (output mode)
71    #[inline(always)]
72    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
73        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
74    }
75    ///0x20 - capture/compare enable register
76    #[inline(always)]
77    pub const fn ccer(&self) -> &CCER {
78        &self.ccer
79    }
80    ///0x24 - counter
81    #[inline(always)]
82    pub const fn cnt(&self) -> &CNT {
83        &self.cnt
84    }
85    ///0x28 - prescaler
86    #[inline(always)]
87    pub const fn psc(&self) -> &PSC {
88        &self.psc
89    }
90    ///0x2c - auto-reload register
91    #[inline(always)]
92    pub const fn arr(&self) -> &ARR {
93        &self.arr
94    }
95    ///0x34..0x44 - capture/compare register
96    ///
97    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
98    #[inline(always)]
99    pub const fn ccr(&self, n: usize) -> &CCR {
100        &self.ccr[n]
101    }
102    ///Iterator for array of:
103    ///0x34..0x44 - capture/compare register
104    #[inline(always)]
105    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
106        self.ccr.iter()
107    }
108    ///0x34 - capture/compare register
109    #[inline(always)]
110    pub const fn ccr1(&self) -> &CCR {
111        self.ccr(0)
112    }
113    ///0x38 - capture/compare register
114    #[inline(always)]
115    pub const fn ccr2(&self) -> &CCR {
116        self.ccr(1)
117    }
118    ///0x3c - capture/compare register
119    #[inline(always)]
120    pub const fn ccr3(&self) -> &CCR {
121        self.ccr(2)
122    }
123    ///0x40 - capture/compare register
124    #[inline(always)]
125    pub const fn ccr4(&self) -> &CCR {
126        self.ccr(3)
127    }
128    ///0x48 - DMA control register
129    #[inline(always)]
130    pub const fn dcr(&self) -> &DCR {
131        &self.dcr
132    }
133    ///0x4c - DMA address for full transfer
134    #[inline(always)]
135    pub const fn dmar(&self) -> &DMAR {
136        &self.dmar
137    }
138    ///0x50 - TIM5 option register
139    #[inline(always)]
140    pub const fn or(&self) -> &OR {
141        &self.or
142    }
143}
144pub use crate::stm32f407::tim2::cr1;
145pub use crate::stm32f407::tim2::cr2;
146pub use crate::stm32f407::tim2::CR1;
147pub use crate::stm32f407::tim2::CR2;
148/**SMCR (rw) register accessor: slave mode control register
149
150You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM5:SMCR)
153
154For information about available fields see [`mod@smcr`] module*/
155pub type SMCR = crate::Reg<smcr::SMCRrs>;
156///slave mode control register
157pub mod smcr;
158pub use crate::stm32f407::tim2::arr;
159pub use crate::stm32f407::tim2::ccer;
160pub use crate::stm32f407::tim2::ccmr1_input;
161pub use crate::stm32f407::tim2::ccmr1_output;
162pub use crate::stm32f407::tim2::ccmr2_input;
163pub use crate::stm32f407::tim2::ccmr2_output;
164pub use crate::stm32f407::tim2::ccr;
165pub use crate::stm32f407::tim2::cnt;
166pub use crate::stm32f407::tim2::dcr;
167pub use crate::stm32f407::tim2::dier;
168pub use crate::stm32f407::tim2::dmar;
169pub use crate::stm32f407::tim2::egr;
170pub use crate::stm32f407::tim2::psc;
171pub use crate::stm32f407::tim2::sr;
172pub use crate::stm32f407::tim2::ARR;
173pub use crate::stm32f407::tim2::CCER;
174pub use crate::stm32f407::tim2::CCMR1_INPUT;
175pub use crate::stm32f407::tim2::CCMR1_OUTPUT;
176pub use crate::stm32f407::tim2::CCMR2_INPUT;
177pub use crate::stm32f407::tim2::CCMR2_OUTPUT;
178pub use crate::stm32f407::tim2::CCR;
179pub use crate::stm32f407::tim2::CNT;
180pub use crate::stm32f407::tim2::DCR;
181pub use crate::stm32f407::tim2::DIER;
182pub use crate::stm32f407::tim2::DMAR;
183pub use crate::stm32f407::tim2::EGR;
184pub use crate::stm32f407::tim2::PSC;
185pub use crate::stm32f407::tim2::SR;
186/**OR (rw) register accessor: TIM5 option register
187
188You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
189
190See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM5:OR)
191
192For information about available fields see [`mod@or`] module*/
193pub type OR = crate::Reg<or::ORrs>;
194///TIM5 option register
195pub mod or;
stm32f4_staging/stm32f407/tim5.rs

stm32f4_staging/stm32f407/
tim5.rs
