stm32f4_staging/stm32f407/tim2/
ccer.rs

1///Register `CCER` reader
2pub type R = crate::R<CCERrs>;
3///Register `CCER` writer
4pub type W = crate::W<CCERrs>;
5/**Capture/Compare %s output enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum CC1E {
11    ///0: Capture disabled
12    Disabled = 0,
13    ///1: Capture enabled
14    Enabled = 1,
15}
16impl From<CC1E> for bool {
17    #[inline(always)]
18    fn from(variant: CC1E) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `CCE(1-4)` reader - Capture/Compare %s output enable
23pub type CCE_R = crate::BitReader<CC1E>;
24impl CCE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> CC1E {
28        match self.bits {
29            false => CC1E::Disabled,
30            true => CC1E::Enabled,
31        }
32    }
33    ///Capture disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == CC1E::Disabled
37    }
38    ///Capture enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == CC1E::Enabled
42    }
43}
44///Field `CCE(1-4)` writer - Capture/Compare %s output enable
45pub type CCE_W<'a, REG> = crate::BitWriter<'a, REG, CC1E>;
46impl<'a, REG> CCE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Capture disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(CC1E::Disabled)
54    }
55    ///Capture enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(CC1E::Enabled)
59    }
60}
61/**Capture/Compare %s output Polarity
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CC1P {
67    ///0: Noninverted/rising edge
68    RisingEdge = 0,
69    ///1: Inverted/falling edge
70    FallingEdge = 1,
71}
72impl From<CC1P> for bool {
73    #[inline(always)]
74    fn from(variant: CC1P) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `CCP(1-4)` reader - Capture/Compare %s output Polarity
79pub type CCP_R = crate::BitReader<CC1P>;
80impl CCP_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> CC1P {
84        match self.bits {
85            false => CC1P::RisingEdge,
86            true => CC1P::FallingEdge,
87        }
88    }
89    ///Noninverted/rising edge
90    #[inline(always)]
91    pub fn is_rising_edge(&self) -> bool {
92        *self == CC1P::RisingEdge
93    }
94    ///Inverted/falling edge
95    #[inline(always)]
96    pub fn is_falling_edge(&self) -> bool {
97        *self == CC1P::FallingEdge
98    }
99}
100///Field `CCP(1-4)` writer - Capture/Compare %s output Polarity
101pub type CCP_W<'a, REG> = crate::BitWriter<'a, REG, CC1P>;
102impl<'a, REG> CCP_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///Noninverted/rising edge
107    #[inline(always)]
108    pub fn rising_edge(self) -> &'a mut crate::W<REG> {
109        self.variant(CC1P::RisingEdge)
110    }
111    ///Inverted/falling edge
112    #[inline(always)]
113    pub fn falling_edge(self) -> &'a mut crate::W<REG> {
114        self.variant(CC1P::FallingEdge)
115    }
116}
117///Field `CCNP(1-4)` reader - Capture/Compare %s output Polarity
118pub type CCNP_R = crate::BitReader;
119///Field `CCNP(1-4)` writer - Capture/Compare %s output Polarity
120pub type CCNP_W<'a, REG> = crate::BitWriter<'a, REG>;
121impl R {
122    ///Capture/Compare (1-4) output enable
123    ///
124    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
125    #[inline(always)]
126    pub fn cce(&self, n: u8) -> CCE_R {
127        #[allow(clippy::no_effect)]
128        [(); 4][n as usize];
129        CCE_R::new(((self.bits >> (n * 4)) & 1) != 0)
130    }
131    ///Iterator for array of:
132    ///Capture/Compare (1-4) output enable
133    #[inline(always)]
134    pub fn cce_iter(&self) -> impl Iterator<Item = CCE_R> + '_ {
135        (0..4).map(move |n| CCE_R::new(((self.bits >> (n * 4)) & 1) != 0))
136    }
137    ///Bit 0 - Capture/Compare 1 output enable
138    #[inline(always)]
139    pub fn cc1e(&self) -> CCE_R {
140        CCE_R::new((self.bits & 1) != 0)
141    }
142    ///Bit 4 - Capture/Compare 2 output enable
143    #[inline(always)]
144    pub fn cc2e(&self) -> CCE_R {
145        CCE_R::new(((self.bits >> 4) & 1) != 0)
146    }
147    ///Bit 8 - Capture/Compare 3 output enable
148    #[inline(always)]
149    pub fn cc3e(&self) -> CCE_R {
150        CCE_R::new(((self.bits >> 8) & 1) != 0)
151    }
152    ///Bit 12 - Capture/Compare 4 output enable
153    #[inline(always)]
154    pub fn cc4e(&self) -> CCE_R {
155        CCE_R::new(((self.bits >> 12) & 1) != 0)
156    }
157    ///Capture/Compare (1-4) output Polarity
158    ///
159    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
160    #[inline(always)]
161    pub fn ccp(&self, n: u8) -> CCP_R {
162        #[allow(clippy::no_effect)]
163        [(); 4][n as usize];
164        CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0)
165    }
166    ///Iterator for array of:
167    ///Capture/Compare (1-4) output Polarity
168    #[inline(always)]
169    pub fn ccp_iter(&self) -> impl Iterator<Item = CCP_R> + '_ {
170        (0..4).map(move |n| CCP_R::new(((self.bits >> (n * 4 + 1)) & 1) != 0))
171    }
172    ///Bit 1 - Capture/Compare 1 output Polarity
173    #[inline(always)]
174    pub fn cc1p(&self) -> CCP_R {
175        CCP_R::new(((self.bits >> 1) & 1) != 0)
176    }
177    ///Bit 5 - Capture/Compare 2 output Polarity
178    #[inline(always)]
179    pub fn cc2p(&self) -> CCP_R {
180        CCP_R::new(((self.bits >> 5) & 1) != 0)
181    }
182    ///Bit 9 - Capture/Compare 3 output Polarity
183    #[inline(always)]
184    pub fn cc3p(&self) -> CCP_R {
185        CCP_R::new(((self.bits >> 9) & 1) != 0)
186    }
187    ///Bit 13 - Capture/Compare 4 output Polarity
188    #[inline(always)]
189    pub fn cc4p(&self) -> CCP_R {
190        CCP_R::new(((self.bits >> 13) & 1) != 0)
191    }
192    ///Capture/Compare (1-4) output Polarity
193    ///
194    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
195    #[inline(always)]
196    pub fn ccnp(&self, n: u8) -> CCNP_R {
197        #[allow(clippy::no_effect)]
198        [(); 4][n as usize];
199        CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0)
200    }
201    ///Iterator for array of:
202    ///Capture/Compare (1-4) output Polarity
203    #[inline(always)]
204    pub fn ccnp_iter(&self) -> impl Iterator<Item = CCNP_R> + '_ {
205        (0..4).map(move |n| CCNP_R::new(((self.bits >> (n * 4 + 3)) & 1) != 0))
206    }
207    ///Bit 3 - Capture/Compare 1 output Polarity
208    #[inline(always)]
209    pub fn cc1np(&self) -> CCNP_R {
210        CCNP_R::new(((self.bits >> 3) & 1) != 0)
211    }
212    ///Bit 7 - Capture/Compare 2 output Polarity
213    #[inline(always)]
214    pub fn cc2np(&self) -> CCNP_R {
215        CCNP_R::new(((self.bits >> 7) & 1) != 0)
216    }
217    ///Bit 11 - Capture/Compare 3 output Polarity
218    #[inline(always)]
219    pub fn cc3np(&self) -> CCNP_R {
220        CCNP_R::new(((self.bits >> 11) & 1) != 0)
221    }
222    ///Bit 15 - Capture/Compare 4 output Polarity
223    #[inline(always)]
224    pub fn cc4np(&self) -> CCNP_R {
225        CCNP_R::new(((self.bits >> 15) & 1) != 0)
226    }
227}
228impl core::fmt::Debug for R {
229    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
230        f.debug_struct("CCER")
231            .field("cc1np", &self.cc1np())
232            .field("cc2np", &self.cc2np())
233            .field("cc3np", &self.cc3np())
234            .field("cc4np", &self.cc4np())
235            .field("cc1p", &self.cc1p())
236            .field("cc2p", &self.cc2p())
237            .field("cc3p", &self.cc3p())
238            .field("cc4p", &self.cc4p())
239            .field("cc1e", &self.cc1e())
240            .field("cc2e", &self.cc2e())
241            .field("cc3e", &self.cc3e())
242            .field("cc4e", &self.cc4e())
243            .finish()
244    }
245}
246impl W {
247    ///Capture/Compare (1-4) output enable
248    ///
249    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1E` field.</div>
250    #[inline(always)]
251    pub fn cce(&mut self, n: u8) -> CCE_W<CCERrs> {
252        #[allow(clippy::no_effect)]
253        [(); 4][n as usize];
254        CCE_W::new(self, n * 4)
255    }
256    ///Bit 0 - Capture/Compare 1 output enable
257    #[inline(always)]
258    pub fn cc1e(&mut self) -> CCE_W<CCERrs> {
259        CCE_W::new(self, 0)
260    }
261    ///Bit 4 - Capture/Compare 2 output enable
262    #[inline(always)]
263    pub fn cc2e(&mut self) -> CCE_W<CCERrs> {
264        CCE_W::new(self, 4)
265    }
266    ///Bit 8 - Capture/Compare 3 output enable
267    #[inline(always)]
268    pub fn cc3e(&mut self) -> CCE_W<CCERrs> {
269        CCE_W::new(self, 8)
270    }
271    ///Bit 12 - Capture/Compare 4 output enable
272    #[inline(always)]
273    pub fn cc4e(&mut self) -> CCE_W<CCERrs> {
274        CCE_W::new(self, 12)
275    }
276    ///Capture/Compare (1-4) output Polarity
277    ///
278    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1P` field.</div>
279    #[inline(always)]
280    pub fn ccp(&mut self, n: u8) -> CCP_W<CCERrs> {
281        #[allow(clippy::no_effect)]
282        [(); 4][n as usize];
283        CCP_W::new(self, n * 4 + 1)
284    }
285    ///Bit 1 - Capture/Compare 1 output Polarity
286    #[inline(always)]
287    pub fn cc1p(&mut self) -> CCP_W<CCERrs> {
288        CCP_W::new(self, 1)
289    }
290    ///Bit 5 - Capture/Compare 2 output Polarity
291    #[inline(always)]
292    pub fn cc2p(&mut self) -> CCP_W<CCERrs> {
293        CCP_W::new(self, 5)
294    }
295    ///Bit 9 - Capture/Compare 3 output Polarity
296    #[inline(always)]
297    pub fn cc3p(&mut self) -> CCP_W<CCERrs> {
298        CCP_W::new(self, 9)
299    }
300    ///Bit 13 - Capture/Compare 4 output Polarity
301    #[inline(always)]
302    pub fn cc4p(&mut self) -> CCP_W<CCERrs> {
303        CCP_W::new(self, 13)
304    }
305    ///Capture/Compare (1-4) output Polarity
306    ///
307    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1NP` field.</div>
308    #[inline(always)]
309    pub fn ccnp(&mut self, n: u8) -> CCNP_W<CCERrs> {
310        #[allow(clippy::no_effect)]
311        [(); 4][n as usize];
312        CCNP_W::new(self, n * 4 + 3)
313    }
314    ///Bit 3 - Capture/Compare 1 output Polarity
315    #[inline(always)]
316    pub fn cc1np(&mut self) -> CCNP_W<CCERrs> {
317        CCNP_W::new(self, 3)
318    }
319    ///Bit 7 - Capture/Compare 2 output Polarity
320    #[inline(always)]
321    pub fn cc2np(&mut self) -> CCNP_W<CCERrs> {
322        CCNP_W::new(self, 7)
323    }
324    ///Bit 11 - Capture/Compare 3 output Polarity
325    #[inline(always)]
326    pub fn cc3np(&mut self) -> CCNP_W<CCERrs> {
327        CCNP_W::new(self, 11)
328    }
329    ///Bit 15 - Capture/Compare 4 output Polarity
330    #[inline(always)]
331    pub fn cc4np(&mut self) -> CCNP_W<CCERrs> {
332        CCNP_W::new(self, 15)
333    }
334}
335/**capture/compare enable register
336
337You can [`read`](crate::Reg::read) this register and get [`ccer::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
338
339See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM2:CCER)*/
340pub struct CCERrs;
341impl crate::RegisterSpec for CCERrs {
342    type Ux = u32;
343}
344///`read()` method returns [`ccer::R`](R) reader structure
345impl crate::Readable for CCERrs {}
346///`write(|w| ..)` method takes [`ccer::W`](W) writer structure
347impl crate::Writable for CCERrs {
348    type Safety = crate::Unsafe;
349}
350///`reset()` method sets CCER to value 0
351impl crate::Resettable for CCERrs {}
stm32f4_staging/stm32f407/tim2/ccer.rs

stm32f4_staging/stm32f407/tim2/
ccer.rs
