stm32f4_staging/stm32f407/syscfg/
pmc.rs

1///Register `PMC` reader
2pub type R = crate::R<PMCrs>;
3///Register `PMC` writer
4pub type W = crate::W<PMCrs>;
5/**Ethernet PHY interface selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum MII_RMII_SEL {
11    ///0: MII interface is selected
12    Mii = 0,
13    ///1: RMII PHY interface is selected
14    RmiiPhy = 1,
15}
16impl From<MII_RMII_SEL> for bool {
17    #[inline(always)]
18    fn from(variant: MII_RMII_SEL) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MII_RMII_SEL` reader - Ethernet PHY interface selection
23pub type MII_RMII_SEL_R = crate::BitReader<MII_RMII_SEL>;
24impl MII_RMII_SEL_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> MII_RMII_SEL {
28        match self.bits {
29            false => MII_RMII_SEL::Mii,
30            true => MII_RMII_SEL::RmiiPhy,
31        }
32    }
33    ///MII interface is selected
34    #[inline(always)]
35    pub fn is_mii(&self) -> bool {
36        *self == MII_RMII_SEL::Mii
37    }
38    ///RMII PHY interface is selected
39    #[inline(always)]
40    pub fn is_rmii_phy(&self) -> bool {
41        *self == MII_RMII_SEL::RmiiPhy
42    }
43}
44///Field `MII_RMII_SEL` writer - Ethernet PHY interface selection
45pub type MII_RMII_SEL_W<'a, REG> = crate::BitWriter<'a, REG, MII_RMII_SEL>;
46impl<'a, REG> MII_RMII_SEL_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///MII interface is selected
51    #[inline(always)]
52    pub fn mii(self) -> &'a mut crate::W<REG> {
53        self.variant(MII_RMII_SEL::Mii)
54    }
55    ///RMII PHY interface is selected
56    #[inline(always)]
57    pub fn rmii_phy(self) -> &'a mut crate::W<REG> {
58        self.variant(MII_RMII_SEL::RmiiPhy)
59    }
60}
61impl R {
62    ///Bit 23 - Ethernet PHY interface selection
63    #[inline(always)]
64    pub fn mii_rmii_sel(&self) -> MII_RMII_SEL_R {
65        MII_RMII_SEL_R::new(((self.bits >> 23) & 1) != 0)
66    }
67}
68impl core::fmt::Debug for R {
69    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
70        f.debug_struct("PMC")
71            .field("mii_rmii_sel", &self.mii_rmii_sel())
72            .finish()
73    }
74}
75impl W {
76    ///Bit 23 - Ethernet PHY interface selection
77    #[inline(always)]
78    pub fn mii_rmii_sel(&mut self) -> MII_RMII_SEL_W<PMCrs> {
79        MII_RMII_SEL_W::new(self, 23)
80    }
81}
82/**peripheral mode configuration register
83
84You can [`read`](crate::Reg::read) this register and get [`pmc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pmc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
85
86See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SYSCFG:PMC)*/
87pub struct PMCrs;
88impl crate::RegisterSpec for PMCrs {
89    type Ux = u32;
90}
91///`read()` method returns [`pmc::R`](R) reader structure
92impl crate::Readable for PMCrs {}
93///`write(|w| ..)` method takes [`pmc::W`](W) writer structure
94impl crate::Writable for PMCrs {
95    type Safety = crate::Unsafe;
96}
97///`reset()` method sets PMC to value 0
98impl crate::Resettable for PMCrs {}
stm32f4_staging/stm32f407/syscfg/pmc.rs

stm32f4_staging/stm32f407/syscfg/
pmc.rs
