stm32f4_staging/stm32f407/
mod.rs

1/*!Peripheral access API for STM32F407 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMP_STAMP();
23    fn RTC_WKUP();
24    fn RCC();
25    fn EXTI0();
26    fn EXTI1();
27    fn EXTI2();
28    fn EXTI3();
29    fn EXTI4();
30    fn DMA1_STREAM0();
31    fn DMA1_STREAM1();
32    fn DMA1_STREAM2();
33    fn DMA1_STREAM3();
34    fn DMA1_STREAM4();
35    fn DMA1_STREAM5();
36    fn DMA1_STREAM6();
37    fn ADC();
38    fn CAN1_TX();
39    fn CAN1_RX0();
40    fn CAN1_RX1();
41    fn CAN1_SCE();
42    fn EXTI9_5();
43    fn TIM1_BRK_TIM9();
44    fn TIM1_UP_TIM10();
45    fn TIM1_TRG_COM_TIM11();
46    fn TIM1_CC();
47    fn TIM2();
48    fn TIM3();
49    fn TIM4();
50    fn I2C1_EV();
51    fn I2C1_ER();
52    fn I2C2_EV();
53    fn I2C2_ER();
54    fn SPI1();
55    fn SPI2();
56    fn USART1();
57    fn USART2();
58    fn USART3();
59    fn EXTI15_10();
60    fn RTC_ALARM();
61    fn OTG_FS_WKUP();
62    fn TIM8_BRK_TIM12();
63    fn TIM8_UP_TIM13();
64    fn TIM8_TRG_COM_TIM14();
65    fn TIM8_CC();
66    fn DMA1_STREAM7();
67    fn FSMC();
68    fn SDIO();
69    fn TIM5();
70    fn SPI3();
71    fn UART4();
72    fn UART5();
73    fn TIM6_DAC();
74    fn TIM7();
75    fn DMA2_STREAM0();
76    fn DMA2_STREAM1();
77    fn DMA2_STREAM2();
78    fn DMA2_STREAM3();
79    fn DMA2_STREAM4();
80    fn ETH();
81    fn ETH_WKUP();
82    fn CAN2_TX();
83    fn CAN2_RX0();
84    fn CAN2_RX1();
85    fn CAN2_SCE();
86    fn OTG_FS();
87    fn DMA2_STREAM5();
88    fn DMA2_STREAM6();
89    fn DMA2_STREAM7();
90    fn USART6();
91    fn I2C3_EV();
92    fn I2C3_ER();
93    fn OTG_HS_EP1_OUT();
94    fn OTG_HS_EP1_IN();
95    fn OTG_HS_WKUP();
96    fn OTG_HS();
97    fn DCMI();
98    fn CRYP();
99    fn HASH_RNG();
100    fn FPU();
101}
102#[doc(hidden)]
103#[repr(C)]
104pub union Vector {
105    _handler: unsafe extern "C" fn(),
106    _reserved: u32,
107}
108#[cfg(feature = "rt")]
109#[doc(hidden)]
110#[link_section = ".vector_table.interrupts"]
111#[no_mangle]
112pub static __INTERRUPTS: [Vector; 82] = [
113    Vector { _handler: WWDG },
114    Vector { _handler: PVD },
115    Vector {
116        _handler: TAMP_STAMP,
117    },
118    Vector { _handler: RTC_WKUP },
119    Vector { _reserved: 0 },
120    Vector { _handler: RCC },
121    Vector { _handler: EXTI0 },
122    Vector { _handler: EXTI1 },
123    Vector { _handler: EXTI2 },
124    Vector { _handler: EXTI3 },
125    Vector { _handler: EXTI4 },
126    Vector {
127        _handler: DMA1_STREAM0,
128    },
129    Vector {
130        _handler: DMA1_STREAM1,
131    },
132    Vector {
133        _handler: DMA1_STREAM2,
134    },
135    Vector {
136        _handler: DMA1_STREAM3,
137    },
138    Vector {
139        _handler: DMA1_STREAM4,
140    },
141    Vector {
142        _handler: DMA1_STREAM5,
143    },
144    Vector {
145        _handler: DMA1_STREAM6,
146    },
147    Vector { _handler: ADC },
148    Vector { _handler: CAN1_TX },
149    Vector { _handler: CAN1_RX0 },
150    Vector { _handler: CAN1_RX1 },
151    Vector { _handler: CAN1_SCE },
152    Vector { _handler: EXTI9_5 },
153    Vector {
154        _handler: TIM1_BRK_TIM9,
155    },
156    Vector {
157        _handler: TIM1_UP_TIM10,
158    },
159    Vector {
160        _handler: TIM1_TRG_COM_TIM11,
161    },
162    Vector { _handler: TIM1_CC },
163    Vector { _handler: TIM2 },
164    Vector { _handler: TIM3 },
165    Vector { _handler: TIM4 },
166    Vector { _handler: I2C1_EV },
167    Vector { _handler: I2C1_ER },
168    Vector { _handler: I2C2_EV },
169    Vector { _handler: I2C2_ER },
170    Vector { _handler: SPI1 },
171    Vector { _handler: SPI2 },
172    Vector { _handler: USART1 },
173    Vector { _handler: USART2 },
174    Vector { _handler: USART3 },
175    Vector {
176        _handler: EXTI15_10,
177    },
178    Vector {
179        _handler: RTC_ALARM,
180    },
181    Vector {
182        _handler: OTG_FS_WKUP,
183    },
184    Vector {
185        _handler: TIM8_BRK_TIM12,
186    },
187    Vector {
188        _handler: TIM8_UP_TIM13,
189    },
190    Vector {
191        _handler: TIM8_TRG_COM_TIM14,
192    },
193    Vector { _handler: TIM8_CC },
194    Vector {
195        _handler: DMA1_STREAM7,
196    },
197    Vector { _handler: FSMC },
198    Vector { _handler: SDIO },
199    Vector { _handler: TIM5 },
200    Vector { _handler: SPI3 },
201    Vector { _handler: UART4 },
202    Vector { _handler: UART5 },
203    Vector { _handler: TIM6_DAC },
204    Vector { _handler: TIM7 },
205    Vector {
206        _handler: DMA2_STREAM0,
207    },
208    Vector {
209        _handler: DMA2_STREAM1,
210    },
211    Vector {
212        _handler: DMA2_STREAM2,
213    },
214    Vector {
215        _handler: DMA2_STREAM3,
216    },
217    Vector {
218        _handler: DMA2_STREAM4,
219    },
220    Vector { _handler: ETH },
221    Vector { _handler: ETH_WKUP },
222    Vector { _handler: CAN2_TX },
223    Vector { _handler: CAN2_RX0 },
224    Vector { _handler: CAN2_RX1 },
225    Vector { _handler: CAN2_SCE },
226    Vector { _handler: OTG_FS },
227    Vector {
228        _handler: DMA2_STREAM5,
229    },
230    Vector {
231        _handler: DMA2_STREAM6,
232    },
233    Vector {
234        _handler: DMA2_STREAM7,
235    },
236    Vector { _handler: USART6 },
237    Vector { _handler: I2C3_EV },
238    Vector { _handler: I2C3_ER },
239    Vector {
240        _handler: OTG_HS_EP1_OUT,
241    },
242    Vector {
243        _handler: OTG_HS_EP1_IN,
244    },
245    Vector {
246        _handler: OTG_HS_WKUP,
247    },
248    Vector { _handler: OTG_HS },
249    Vector { _handler: DCMI },
250    Vector { _handler: CRYP },
251    Vector { _handler: HASH_RNG },
252    Vector { _handler: FPU },
253];
254///Enumeration of all the interrupts.
255#[cfg_attr(feature = "defmt", derive(defmt::Format))]
256#[derive(Copy, Clone, Debug, PartialEq, Eq)]
257#[repr(u16)]
258pub enum Interrupt {
259    ///0 - Window Watchdog interrupt
260    WWDG = 0,
261    ///1 - PVD through EXTI line detection interrupt
262    PVD = 1,
263    ///2 - Tamper and TimeStamp interrupts through the EXTI line
264    TAMP_STAMP = 2,
265    ///3 - RTC Wakeup interrupt through the EXTI line
266    RTC_WKUP = 3,
267    ///5 - RCC global interrupt
268    RCC = 5,
269    ///6 - EXTI Line0 interrupt
270    EXTI0 = 6,
271    ///7 - EXTI Line1 interrupt
272    EXTI1 = 7,
273    ///8 - EXTI Line2 interrupt
274    EXTI2 = 8,
275    ///9 - EXTI Line3 interrupt
276    EXTI3 = 9,
277    ///10 - EXTI Line4 interrupt
278    EXTI4 = 10,
279    ///11 - DMA1 Stream0 global interrupt
280    DMA1_STREAM0 = 11,
281    ///12 - DMA1 Stream1 global interrupt
282    DMA1_STREAM1 = 12,
283    ///13 - DMA1 Stream2 global interrupt
284    DMA1_STREAM2 = 13,
285    ///14 - DMA1 Stream3 global interrupt
286    DMA1_STREAM3 = 14,
287    ///15 - DMA1 Stream4 global interrupt
288    DMA1_STREAM4 = 15,
289    ///16 - DMA1 Stream5 global interrupt
290    DMA1_STREAM5 = 16,
291    ///17 - DMA1 Stream6 global interrupt
292    DMA1_STREAM6 = 17,
293    ///18 - ADC1, ADC2 and ADC3 global interrupts
294    ADC = 18,
295    ///19 - CAN1 TX interrupts
296    CAN1_TX = 19,
297    ///20 - CAN1 RX0 interrupts
298    CAN1_RX0 = 20,
299    ///21 - CAN1 RX1 interrupts
300    CAN1_RX1 = 21,
301    ///22 - CAN1 SCE interrupt
302    CAN1_SCE = 22,
303    ///23 - EXTI Line\[9:5\] interrupts
304    EXTI9_5 = 23,
305    ///24 - TIM1 Break interrupt and TIM9 global interrupt
306    TIM1_BRK_TIM9 = 24,
307    ///25 - TIM1 Update interrupt and TIM10 global interrupt
308    TIM1_UP_TIM10 = 25,
309    ///26 - TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
310    TIM1_TRG_COM_TIM11 = 26,
311    ///27 - TIM1 Capture Compare interrupt
312    TIM1_CC = 27,
313    ///28 - TIM2 global interrupt
314    TIM2 = 28,
315    ///29 - TIM3 global interrupt
316    TIM3 = 29,
317    ///30 - TIM4 global interrupt
318    TIM4 = 30,
319    ///31 - I2C1 event interrupt
320    I2C1_EV = 31,
321    ///32 - I2C1 error interrupt
322    I2C1_ER = 32,
323    ///33 - I2C2 event interrupt
324    I2C2_EV = 33,
325    ///34 - I2C2 error interrupt
326    I2C2_ER = 34,
327    ///35 - SPI1 global interrupt
328    SPI1 = 35,
329    ///36 - SPI2 global interrupt
330    SPI2 = 36,
331    ///37 - USART1 global interrupt
332    USART1 = 37,
333    ///38 - USART2 global interrupt
334    USART2 = 38,
335    ///39 - USART3 global interrupt
336    USART3 = 39,
337    ///40 - EXTI Line\[15:10\] interrupts
338    EXTI15_10 = 40,
339    ///41 - RTC Alarms (A and B) through EXTI line interrupt
340    RTC_ALARM = 41,
341    ///42 - USB On-The-Go FS Wakeup through EXTI line interrupt
342    OTG_FS_WKUP = 42,
343    ///43 - TIM8 Break interrupt and TIM12 global interrupt
344    TIM8_BRK_TIM12 = 43,
345    ///44 - TIM8 Update interrupt and TIM13 global interrupt
346    TIM8_UP_TIM13 = 44,
347    ///45 - TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
348    TIM8_TRG_COM_TIM14 = 45,
349    ///46 - TIM8 Capture Compare interrupt
350    TIM8_CC = 46,
351    ///47 - DMA1 Stream7 global interrupt
352    DMA1_STREAM7 = 47,
353    ///48 - FSMC global interrupt
354    FSMC = 48,
355    ///49 - SDIO global interrupt
356    SDIO = 49,
357    ///50 - TIM5 global interrupt
358    TIM5 = 50,
359    ///51 - SPI3 global interrupt
360    SPI3 = 51,
361    ///52 - UART4 global interrupt
362    UART4 = 52,
363    ///53 - UART5 global interrupt
364    UART5 = 53,
365    ///54 - TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
366    TIM6_DAC = 54,
367    ///55 - TIM7 global interrupt
368    TIM7 = 55,
369    ///56 - DMA2 Stream0 global interrupt
370    DMA2_STREAM0 = 56,
371    ///57 - DMA2 Stream1 global interrupt
372    DMA2_STREAM1 = 57,
373    ///58 - DMA2 Stream2 global interrupt
374    DMA2_STREAM2 = 58,
375    ///59 - DMA2 Stream3 global interrupt
376    DMA2_STREAM3 = 59,
377    ///60 - DMA2 Stream4 global interrupt
378    DMA2_STREAM4 = 60,
379    ///61 - Ethernet global interrupt
380    ETH = 61,
381    ///62 - Ethernet Wakeup through EXTI line interrupt
382    ETH_WKUP = 62,
383    ///63 - CAN2 TX interrupts
384    CAN2_TX = 63,
385    ///64 - CAN2 RX0 interrupts
386    CAN2_RX0 = 64,
387    ///65 - CAN2 RX1 interrupts
388    CAN2_RX1 = 65,
389    ///66 - CAN2 SCE interrupt
390    CAN2_SCE = 66,
391    ///67 - USB On The Go FS global interrupt
392    OTG_FS = 67,
393    ///68 - DMA2 Stream5 global interrupt
394    DMA2_STREAM5 = 68,
395    ///69 - DMA2 Stream6 global interrupt
396    DMA2_STREAM6 = 69,
397    ///70 - DMA2 Stream7 global interrupt
398    DMA2_STREAM7 = 70,
399    ///71 - USART6 global interrupt
400    USART6 = 71,
401    ///72 - I2C3 event interrupt
402    I2C3_EV = 72,
403    ///73 - I2C3 error interrupt
404    I2C3_ER = 73,
405    ///74 - USB On The Go HS End Point 1 Out global interrupt
406    OTG_HS_EP1_OUT = 74,
407    ///75 - USB On The Go HS End Point 1 In global interrupt
408    OTG_HS_EP1_IN = 75,
409    ///76 - USB On The Go HS Wakeup through EXTI interrupt
410    OTG_HS_WKUP = 76,
411    ///77 - USB On The Go HS global interrupt
412    OTG_HS = 77,
413    ///78 - DCMI global interrupt
414    DCMI = 78,
415    ///79 - CRYP crypto global interrupt
416    CRYP = 79,
417    ///80 - Hash and Rng global interrupt
418    HASH_RNG = 80,
419    ///81 - Floating point unit interrupt
420    FPU = 81,
421}
422unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
423    #[inline(always)]
424    fn number(self) -> u16 {
425        self as u16
426    }
427}
428///Random number generator
429///
430///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#RNG)
431pub type RNG = crate::Periph<rng::RegisterBlock, 0x5006_0800>;
432impl core::fmt::Debug for RNG {
433    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
434        f.debug_struct("RNG").finish()
435    }
436}
437///Random number generator
438pub mod rng;
439///Digital camera interface
440///
441///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI)
442pub type DCMI = crate::Periph<dcmi::RegisterBlock, 0x5005_0000>;
443impl core::fmt::Debug for DCMI {
444    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
445        f.debug_struct("DCMI").finish()
446    }
447}
448///Digital camera interface
449pub mod dcmi;
450///Flexible memory controller
451///
452///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#FSMC)
453pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
454impl core::fmt::Debug for FSMC {
455    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
456        f.debug_struct("FSMC").finish()
457    }
458}
459///Flexible memory controller
460pub mod fsmc;
461///Debug support
462///
463///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DBGMCU)
464pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
465impl core::fmt::Debug for DBGMCU {
466    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
467        f.debug_struct("DBGMCU").finish()
468    }
469}
470///Debug support
471pub mod dbgmcu;
472///DMA controller
473///
474///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DMA2)
475pub type DMA2 = crate::Periph<dma2::RegisterBlock, 0x4002_6400>;
476impl core::fmt::Debug for DMA2 {
477    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
478        f.debug_struct("DMA2").finish()
479    }
480}
481///DMA controller
482pub mod dma2;
483///DMA controller
484///
485///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DMA2)
486pub type DMA1 = crate::Periph<dma2::RegisterBlock, 0x4002_6000>;
487impl core::fmt::Debug for DMA1 {
488    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
489        f.debug_struct("DMA1").finish()
490    }
491}
492///DMA controller
493pub use self::dma2 as dma1;
494///Reset and clock control
495///
496///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#RCC)
497pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_3800>;
498impl core::fmt::Debug for RCC {
499    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
500        f.debug_struct("RCC").finish()
501    }
502}
503///Reset and clock control
504pub mod rcc;
505///General-purpose I/Os
506///
507///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
508pub type GPIOI = crate::Periph<gpioi::RegisterBlock, 0x4002_2000>;
509impl core::fmt::Debug for GPIOI {
510    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
511        f.debug_struct("GPIOI").finish()
512    }
513}
514///General-purpose I/Os
515pub mod gpioi;
516///General-purpose I/Os
517///
518///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
519pub type GPIOH = crate::Periph<gpioi::RegisterBlock, 0x4002_1c00>;
520impl core::fmt::Debug for GPIOH {
521    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
522        f.debug_struct("GPIOH").finish()
523    }
524}
525///General-purpose I/Os
526pub use self::gpioi as gpioh;
527///General-purpose I/Os
528///
529///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
530pub type GPIOG = crate::Periph<gpioi::RegisterBlock, 0x4002_1800>;
531impl core::fmt::Debug for GPIOG {
532    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
533        f.debug_struct("GPIOG").finish()
534    }
535}
536///General-purpose I/Os
537pub use self::gpioi as gpiog;
538///General-purpose I/Os
539///
540///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
541pub type GPIOF = crate::Periph<gpioi::RegisterBlock, 0x4002_1400>;
542impl core::fmt::Debug for GPIOF {
543    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
544        f.debug_struct("GPIOF").finish()
545    }
546}
547///General-purpose I/Os
548pub use self::gpioi as gpiof;
549///General-purpose I/Os
550///
551///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
552pub type GPIOE = crate::Periph<gpioi::RegisterBlock, 0x4002_1000>;
553impl core::fmt::Debug for GPIOE {
554    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
555        f.debug_struct("GPIOE").finish()
556    }
557}
558///General-purpose I/Os
559pub use self::gpioi as gpioe;
560///General-purpose I/Os
561///
562///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
563pub type GPIOD = crate::Periph<gpioi::RegisterBlock, 0x4002_0c00>;
564impl core::fmt::Debug for GPIOD {
565    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
566        f.debug_struct("GPIOD").finish()
567    }
568}
569///General-purpose I/Os
570pub use self::gpioi as gpiod;
571///General-purpose I/Os
572///
573///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
574pub type GPIOC = crate::Periph<gpioi::RegisterBlock, 0x4002_0800>;
575impl core::fmt::Debug for GPIOC {
576    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
577        f.debug_struct("GPIOC").finish()
578    }
579}
580///General-purpose I/Os
581pub use self::gpioi as gpioc;
582///General-purpose I/Os
583///
584///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
585pub type GPIOJ = crate::Periph<gpioi::RegisterBlock, 0x4002_2400>;
586impl core::fmt::Debug for GPIOJ {
587    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
588        f.debug_struct("GPIOJ").finish()
589    }
590}
591///General-purpose I/Os
592pub use self::gpioi as gpioj;
593///General-purpose I/Os
594///
595///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOI)
596pub type GPIOK = crate::Periph<gpioi::RegisterBlock, 0x4002_2800>;
597impl core::fmt::Debug for GPIOK {
598    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
599        f.debug_struct("GPIOK").finish()
600    }
601}
602///General-purpose I/Os
603pub use self::gpioi as gpiok;
604///General-purpose I/Os
605///
606///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOB)
607pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4002_0400>;
608impl core::fmt::Debug for GPIOB {
609    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
610        f.debug_struct("GPIOB").finish()
611    }
612}
613///General-purpose I/Os
614pub mod gpiob;
615///General-purpose I/Os
616///
617///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#GPIOA)
618pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4002_0000>;
619impl core::fmt::Debug for GPIOA {
620    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
621        f.debug_struct("GPIOA").finish()
622    }
623}
624///General-purpose I/Os
625pub mod gpioa;
626///System configuration controller
627///
628///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SYSCFG)
629pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_3800>;
630impl core::fmt::Debug for SYSCFG {
631    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
632        f.debug_struct("SYSCFG").finish()
633    }
634}
635///System configuration controller
636pub mod syscfg;
637///Serial peripheral interface
638///
639///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SPI1)
640pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
641impl core::fmt::Debug for SPI1 {
642    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
643        f.debug_struct("SPI1").finish()
644    }
645}
646///Serial peripheral interface
647pub mod spi1;
648///Serial peripheral interface
649///
650///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SPI1)
651pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
652impl core::fmt::Debug for SPI2 {
653    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
654        f.debug_struct("SPI2").finish()
655    }
656}
657///Serial peripheral interface
658pub use self::spi1 as spi2;
659///Serial peripheral interface
660///
661///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SPI1)
662pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
663impl core::fmt::Debug for SPI3 {
664    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
665        f.debug_struct("SPI3").finish()
666    }
667}
668///Serial peripheral interface
669pub use self::spi1 as spi3;
670///Serial peripheral interface
671///
672///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SPI1)
673pub type I2S2EXT = crate::Periph<spi1::RegisterBlock, 0x4000_3400>;
674impl core::fmt::Debug for I2S2EXT {
675    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
676        f.debug_struct("I2S2EXT").finish()
677    }
678}
679///Serial peripheral interface
680pub use self::spi1 as i2s2ext;
681///Serial peripheral interface
682///
683///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SPI1)
684pub type I2S3EXT = crate::Periph<spi1::RegisterBlock, 0x4000_4000>;
685impl core::fmt::Debug for I2S3EXT {
686    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
687        f.debug_struct("I2S3EXT").finish()
688    }
689}
690///Serial peripheral interface
691pub use self::spi1 as i2s3ext;
692///Secure digital input/output interface
693///
694///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#SDIO)
695pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_2c00>;
696impl core::fmt::Debug for SDIO {
697    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
698        f.debug_struct("SDIO").finish()
699    }
700}
701///Secure digital input/output interface
702pub mod sdio;
703///Analog-to-digital converter
704///
705///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#ADC1)
706pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2000>;
707impl core::fmt::Debug for ADC1 {
708    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
709        f.debug_struct("ADC1").finish()
710    }
711}
712///Analog-to-digital converter
713pub mod adc1;
714///Analog-to-digital converter
715///
716///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#ADC1)
717pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x4001_2100>;
718impl core::fmt::Debug for ADC2 {
719    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
720        f.debug_struct("ADC2").finish()
721    }
722}
723///Analog-to-digital converter
724pub use self::adc1 as adc2;
725///Analog-to-digital converter
726///
727///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#ADC1)
728pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x4001_2200>;
729impl core::fmt::Debug for ADC3 {
730    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
731        f.debug_struct("ADC3").finish()
732    }
733}
734///Analog-to-digital converter
735pub use self::adc1 as adc3;
736///Universal synchronous asynchronous receiver transmitter
737///
738///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#USART1)
739pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_1000>;
740impl core::fmt::Debug for USART1 {
741    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
742        f.debug_struct("USART1").finish()
743    }
744}
745///Universal synchronous asynchronous receiver transmitter
746pub mod usart1;
747///Universal synchronous asynchronous receiver transmitter
748///
749///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#USART1)
750pub type USART6 = crate::Periph<usart1::RegisterBlock, 0x4001_1400>;
751impl core::fmt::Debug for USART6 {
752    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
753        f.debug_struct("USART6").finish()
754    }
755}
756///Universal synchronous asynchronous receiver transmitter
757pub use self::usart1 as usart6;
758///Universal synchronous asynchronous receiver transmitter
759///
760///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#USART1)
761pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
762impl core::fmt::Debug for USART2 {
763    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
764        f.debug_struct("USART2").finish()
765    }
766}
767///Universal synchronous asynchronous receiver transmitter
768pub use self::usart1 as usart2;
769///Universal synchronous asynchronous receiver transmitter
770///
771///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#USART1)
772pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
773impl core::fmt::Debug for USART3 {
774    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
775        f.debug_struct("USART3").finish()
776    }
777}
778///Universal synchronous asynchronous receiver transmitter
779pub use self::usart1 as usart3;
780///Digital-to-analog converter
781///
782///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DAC)
783pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
784impl core::fmt::Debug for DAC {
785    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
786        f.debug_struct("DAC").finish()
787    }
788}
789///Digital-to-analog converter
790pub mod dac;
791///Power control
792///
793///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#PWR)
794pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
795impl core::fmt::Debug for PWR {
796    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
797        f.debug_struct("PWR").finish()
798    }
799}
800///Power control
801pub mod pwr;
802///Inter-integrated circuit
803///
804///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#I2C1)
805pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
806impl core::fmt::Debug for I2C1 {
807    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
808        f.debug_struct("I2C1").finish()
809    }
810}
811///Inter-integrated circuit
812pub mod i2c1;
813///Inter-integrated circuit
814///
815///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#I2C1)
816pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_5c00>;
817impl core::fmt::Debug for I2C3 {
818    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
819        f.debug_struct("I2C3").finish()
820    }
821}
822///Inter-integrated circuit
823pub use self::i2c1 as i2c3;
824///Inter-integrated circuit
825///
826///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#I2C1)
827pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
828impl core::fmt::Debug for I2C2 {
829    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
830        f.debug_struct("I2C2").finish()
831    }
832}
833///Inter-integrated circuit
834pub use self::i2c1 as i2c2;
835///Independent watchdog
836///
837///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#IWDG)
838pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
839impl core::fmt::Debug for IWDG {
840    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
841        f.debug_struct("IWDG").finish()
842    }
843}
844///Independent watchdog
845pub mod iwdg;
846///Window watchdog
847///
848///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#WWDG)
849pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
850impl core::fmt::Debug for WWDG {
851    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
852        f.debug_struct("WWDG").finish()
853    }
854}
855///Window watchdog
856pub mod wwdg;
857///Real-time clock
858///
859///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#RTC)
860pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
861impl core::fmt::Debug for RTC {
862    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
863        f.debug_struct("RTC").finish()
864    }
865}
866///Real-time clock
867pub mod rtc;
868///Universal synchronous asynchronous receiver transmitter
869///
870///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#UART4)
871pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
872impl core::fmt::Debug for UART4 {
873    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
874        f.debug_struct("UART4").finish()
875    }
876}
877///Universal synchronous asynchronous receiver transmitter
878pub mod uart4;
879///Universal synchronous asynchronous receiver transmitter
880///
881///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#UART4)
882pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
883impl core::fmt::Debug for UART5 {
884    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
885        f.debug_struct("UART5").finish()
886    }
887}
888///Universal synchronous asynchronous receiver transmitter
889pub use self::uart4 as uart5;
890///Common ADC registers
891///
892///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#ADC_Common)
893pub type ADC_COMMON = crate::Periph<adc_common::RegisterBlock, 0x4001_2300>;
894impl core::fmt::Debug for ADC_COMMON {
895    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
896        f.debug_struct("ADC_COMMON").finish()
897    }
898}
899///Common ADC registers
900pub mod adc_common;
901///Advanced-timers
902///
903///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM1)
904pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_0000>;
905impl core::fmt::Debug for TIM1 {
906    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
907        f.debug_struct("TIM1").finish()
908    }
909}
910///Advanced-timers
911pub mod tim1;
912///Advanced-timers
913///
914///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM1)
915pub type TIM8 = crate::Periph<tim1::RegisterBlock, 0x4001_0400>;
916impl core::fmt::Debug for TIM8 {
917    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
918        f.debug_struct("TIM8").finish()
919    }
920}
921///Advanced-timers
922pub use self::tim1 as tim8;
923///General purpose timers
924///
925///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM2)
926pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
927impl core::fmt::Debug for TIM2 {
928    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
929        f.debug_struct("TIM2").finish()
930    }
931}
932///General purpose timers
933pub mod tim2;
934///General purpose timers
935///
936///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM3)
937pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
938impl core::fmt::Debug for TIM3 {
939    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
940        f.debug_struct("TIM3").finish()
941    }
942}
943///General purpose timers
944pub mod tim3;
945///General purpose timers
946///
947///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM3)
948pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
949impl core::fmt::Debug for TIM4 {
950    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
951        f.debug_struct("TIM4").finish()
952    }
953}
954///General purpose timers
955pub use self::tim3 as tim4;
956///General-purpose-timers
957///
958///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM5)
959pub type TIM5 = crate::Periph<tim5::RegisterBlock, 0x4000_0c00>;
960impl core::fmt::Debug for TIM5 {
961    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
962        f.debug_struct("TIM5").finish()
963    }
964}
965///General-purpose-timers
966pub mod tim5;
967///General purpose timers
968///
969///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM9)
970pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4000>;
971impl core::fmt::Debug for TIM9 {
972    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
973        f.debug_struct("TIM9").finish()
974    }
975}
976///General purpose timers
977pub mod tim9;
978///General purpose timers
979///
980///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM9)
981pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
982impl core::fmt::Debug for TIM12 {
983    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
984        f.debug_struct("TIM12").finish()
985    }
986}
987///General purpose timers
988pub use self::tim9 as tim12;
989///General-purpose-timers
990///
991///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM10)
992pub type TIM10 = crate::Periph<tim10::RegisterBlock, 0x4001_4400>;
993impl core::fmt::Debug for TIM10 {
994    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
995        f.debug_struct("TIM10").finish()
996    }
997}
998///General-purpose-timers
999pub mod tim10;
1000///General-purpose-timers
1001///
1002///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM10)
1003pub type TIM13 = crate::Periph<tim10::RegisterBlock, 0x4000_1c00>;
1004impl core::fmt::Debug for TIM13 {
1005    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1006        f.debug_struct("TIM13").finish()
1007    }
1008}
1009///General-purpose-timers
1010pub use self::tim10 as tim13;
1011///General-purpose-timers
1012///
1013///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM10)
1014pub type TIM14 = crate::Periph<tim10::RegisterBlock, 0x4000_2000>;
1015impl core::fmt::Debug for TIM14 {
1016    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1017        f.debug_struct("TIM14").finish()
1018    }
1019}
1020///General-purpose-timers
1021pub use self::tim10 as tim14;
1022///General-purpose-timers
1023///
1024///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM11)
1025pub type TIM11 = crate::Periph<tim11::RegisterBlock, 0x4001_4800>;
1026impl core::fmt::Debug for TIM11 {
1027    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1028        f.debug_struct("TIM11").finish()
1029    }
1030}
1031///General-purpose-timers
1032pub mod tim11;
1033///Basic timers
1034///
1035///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM6)
1036pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
1037impl core::fmt::Debug for TIM6 {
1038    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1039        f.debug_struct("TIM6").finish()
1040    }
1041}
1042///Basic timers
1043pub mod tim6;
1044///Basic timers
1045///
1046///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#TIM6)
1047pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
1048impl core::fmt::Debug for TIM7 {
1049    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1050        f.debug_struct("TIM7").finish()
1051    }
1052}
1053///Basic timers
1054pub use self::tim6 as tim7;
1055///Ethernet: media access control (MAC)
1056///
1057///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#Ethernet_MAC)
1058pub type ETHERNET_MAC = crate::Periph<ethernet_mac::RegisterBlock, 0x4002_8000>;
1059impl core::fmt::Debug for ETHERNET_MAC {
1060    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1061        f.debug_struct("ETHERNET_MAC").finish()
1062    }
1063}
1064///Ethernet: media access control (MAC)
1065pub mod ethernet_mac;
1066///Ethernet: MAC management counters
1067///
1068///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#Ethernet_MMC)
1069pub type ETHERNET_MMC = crate::Periph<ethernet_mmc::RegisterBlock, 0x4002_8100>;
1070impl core::fmt::Debug for ETHERNET_MMC {
1071    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1072        f.debug_struct("ETHERNET_MMC").finish()
1073    }
1074}
1075///Ethernet: MAC management counters
1076pub mod ethernet_mmc;
1077///Ethernet: Precision time protocol
1078///
1079///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#Ethernet_PTP)
1080pub type ETHERNET_PTP = crate::Periph<ethernet_ptp::RegisterBlock, 0x4002_8700>;
1081impl core::fmt::Debug for ETHERNET_PTP {
1082    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1083        f.debug_struct("ETHERNET_PTP").finish()
1084    }
1085}
1086///Ethernet: Precision time protocol
1087pub mod ethernet_ptp;
1088///Ethernet: DMA controller operation
1089///
1090///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#Ethernet_DMA)
1091pub type ETHERNET_DMA = crate::Periph<ethernet_dma::RegisterBlock, 0x4002_9000>;
1092impl core::fmt::Debug for ETHERNET_DMA {
1093    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1094        f.debug_struct("ETHERNET_DMA").finish()
1095    }
1096}
1097///Ethernet: DMA controller operation
1098pub mod ethernet_dma;
1099///Cryptographic processor
1100///
1101///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#CRC)
1102pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
1103impl core::fmt::Debug for CRC {
1104    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1105        f.debug_struct("CRC").finish()
1106    }
1107}
1108///Cryptographic processor
1109pub mod crc;
1110///USB on the go full speed
1111///
1112///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_FS_GLOBAL)
1113pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
1114impl core::fmt::Debug for OTG_FS_GLOBAL {
1115    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1116        f.debug_struct("OTG_FS_GLOBAL").finish()
1117    }
1118}
1119///USB on the go full speed
1120pub mod otg_fs_global;
1121///USB on the go full speed
1122///
1123///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_FS_HOST)
1124pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
1125impl core::fmt::Debug for OTG_FS_HOST {
1126    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1127        f.debug_struct("OTG_FS_HOST").finish()
1128    }
1129}
1130///USB on the go full speed
1131pub mod otg_fs_host;
1132///USB on the go full speed
1133///
1134///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_FS_DEVICE)
1135pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
1136impl core::fmt::Debug for OTG_FS_DEVICE {
1137    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1138        f.debug_struct("OTG_FS_DEVICE").finish()
1139    }
1140}
1141///USB on the go full speed
1142pub mod otg_fs_device;
1143///USB on the go full speed
1144///
1145///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_FS_PWRCLK)
1146pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
1147impl core::fmt::Debug for OTG_FS_PWRCLK {
1148    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1149        f.debug_struct("OTG_FS_PWRCLK").finish()
1150    }
1151}
1152///USB on the go full speed
1153pub mod otg_fs_pwrclk;
1154///Controller area network
1155///
1156///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#CAN1)
1157pub type CAN1 = crate::Periph<can1::RegisterBlock, 0x4000_6400>;
1158impl core::fmt::Debug for CAN1 {
1159    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1160        f.debug_struct("CAN1").finish()
1161    }
1162}
1163///Controller area network
1164pub mod can1;
1165///Controller area network
1166///
1167///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#CAN1)
1168pub type CAN2 = crate::Periph<can1::RegisterBlock, 0x4000_6800>;
1169impl core::fmt::Debug for CAN2 {
1170    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1171        f.debug_struct("CAN2").finish()
1172    }
1173}
1174///Controller area network
1175pub use self::can1 as can2;
1176///FLASH
1177///
1178///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#FLASH)
1179pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_3c00>;
1180impl core::fmt::Debug for FLASH {
1181    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1182        f.debug_struct("FLASH").finish()
1183    }
1184}
1185///FLASH
1186pub mod flash;
1187///External interrupt/event controller
1188///
1189///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#EXTI)
1190pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_3c00>;
1191impl core::fmt::Debug for EXTI {
1192    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1193        f.debug_struct("EXTI").finish()
1194    }
1195}
1196///External interrupt/event controller
1197pub mod exti;
1198///USB on the go high speed
1199///
1200///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_GLOBAL)
1201pub type OTG_HS_GLOBAL = crate::Periph<otg_hs_global::RegisterBlock, 0x4004_0000>;
1202impl core::fmt::Debug for OTG_HS_GLOBAL {
1203    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1204        f.debug_struct("OTG_HS_GLOBAL").finish()
1205    }
1206}
1207///USB on the go high speed
1208pub mod otg_hs_global;
1209///USB on the go high speed
1210///
1211///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_HOST)
1212pub type OTG_HS_HOST = crate::Periph<otg_hs_host::RegisterBlock, 0x4004_0400>;
1213impl core::fmt::Debug for OTG_HS_HOST {
1214    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1215        f.debug_struct("OTG_HS_HOST").finish()
1216    }
1217}
1218///USB on the go high speed
1219pub mod otg_hs_host;
1220///USB on the go high speed
1221///
1222///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_DEVICE)
1223pub type OTG_HS_DEVICE = crate::Periph<otg_hs_device::RegisterBlock, 0x4004_0800>;
1224impl core::fmt::Debug for OTG_HS_DEVICE {
1225    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1226        f.debug_struct("OTG_HS_DEVICE").finish()
1227    }
1228}
1229///USB on the go high speed
1230pub mod otg_hs_device;
1231///USB on the go high speed
1232///
1233///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#OTG_HS_PWRCLK)
1234pub type OTG_HS_PWRCLK = crate::Periph<otg_hs_pwrclk::RegisterBlock, 0x4004_0e00>;
1235impl core::fmt::Debug for OTG_HS_PWRCLK {
1236    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1237        f.debug_struct("OTG_HS_PWRCLK").finish()
1238    }
1239}
1240///USB on the go high speed
1241pub mod otg_hs_pwrclk;
1242///Hash processor
1243///
1244///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#HASH)
1245pub type HASH = crate::Periph<hash::RegisterBlock, 0x5006_0400>;
1246impl core::fmt::Debug for HASH {
1247    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1248        f.debug_struct("HASH").finish()
1249    }
1250}
1251///Hash processor
1252pub mod hash;
1253///Cryptographic processor
1254///
1255///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#CRYP)
1256pub type CRYP = crate::Periph<cryp::RegisterBlock, 0x5006_0000>;
1257impl core::fmt::Debug for CRYP {
1258    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1259        f.debug_struct("CRYP").finish()
1260    }
1261}
1262///Cryptographic processor
1263pub mod cryp;
1264#[no_mangle]
1265static mut DEVICE_PERIPHERALS: bool = false;
1266/// All the peripherals.
1267#[allow(non_snake_case)]
1268pub struct Peripherals {
1269    ///RNG
1270    pub RNG: RNG,
1271    ///DCMI
1272    pub DCMI: DCMI,
1273    ///FSMC
1274    pub FSMC: FSMC,
1275    ///DBGMCU
1276    pub DBGMCU: DBGMCU,
1277    ///DMA2
1278    pub DMA2: DMA2,
1279    ///DMA1
1280    pub DMA1: DMA1,
1281    ///RCC
1282    pub RCC: RCC,
1283    ///GPIOI
1284    pub GPIOI: GPIOI,
1285    ///GPIOH
1286    pub GPIOH: GPIOH,
1287    ///GPIOG
1288    pub GPIOG: GPIOG,
1289    ///GPIOF
1290    pub GPIOF: GPIOF,
1291    ///GPIOE
1292    pub GPIOE: GPIOE,
1293    ///GPIOD
1294    pub GPIOD: GPIOD,
1295    ///GPIOC
1296    pub GPIOC: GPIOC,
1297    ///GPIOJ
1298    pub GPIOJ: GPIOJ,
1299    ///GPIOK
1300    pub GPIOK: GPIOK,
1301    ///GPIOB
1302    pub GPIOB: GPIOB,
1303    ///GPIOA
1304    pub GPIOA: GPIOA,
1305    ///SYSCFG
1306    pub SYSCFG: SYSCFG,
1307    ///SPI1
1308    pub SPI1: SPI1,
1309    ///SPI2
1310    pub SPI2: SPI2,
1311    ///SPI3
1312    pub SPI3: SPI3,
1313    ///I2S2ext
1314    pub I2S2EXT: I2S2EXT,
1315    ///I2S3ext
1316    pub I2S3EXT: I2S3EXT,
1317    ///SDIO
1318    pub SDIO: SDIO,
1319    ///ADC1
1320    pub ADC1: ADC1,
1321    ///ADC2
1322    pub ADC2: ADC2,
1323    ///ADC3
1324    pub ADC3: ADC3,
1325    ///USART1
1326    pub USART1: USART1,
1327    ///USART6
1328    pub USART6: USART6,
1329    ///USART2
1330    pub USART2: USART2,
1331    ///USART3
1332    pub USART3: USART3,
1333    ///DAC
1334    pub DAC: DAC,
1335    ///PWR
1336    pub PWR: PWR,
1337    ///I2C1
1338    pub I2C1: I2C1,
1339    ///I2C3
1340    pub I2C3: I2C3,
1341    ///I2C2
1342    pub I2C2: I2C2,
1343    ///IWDG
1344    pub IWDG: IWDG,
1345    ///WWDG
1346    pub WWDG: WWDG,
1347    ///RTC
1348    pub RTC: RTC,
1349    ///UART4
1350    pub UART4: UART4,
1351    ///UART5
1352    pub UART5: UART5,
1353    ///ADC_Common
1354    pub ADC_COMMON: ADC_COMMON,
1355    ///TIM1
1356    pub TIM1: TIM1,
1357    ///TIM8
1358    pub TIM8: TIM8,
1359    ///TIM2
1360    pub TIM2: TIM2,
1361    ///TIM3
1362    pub TIM3: TIM3,
1363    ///TIM4
1364    pub TIM4: TIM4,
1365    ///TIM5
1366    pub TIM5: TIM5,
1367    ///TIM9
1368    pub TIM9: TIM9,
1369    ///TIM12
1370    pub TIM12: TIM12,
1371    ///TIM10
1372    pub TIM10: TIM10,
1373    ///TIM13
1374    pub TIM13: TIM13,
1375    ///TIM14
1376    pub TIM14: TIM14,
1377    ///TIM11
1378    pub TIM11: TIM11,
1379    ///TIM6
1380    pub TIM6: TIM6,
1381    ///TIM7
1382    pub TIM7: TIM7,
1383    ///Ethernet_MAC
1384    pub ETHERNET_MAC: ETHERNET_MAC,
1385    ///Ethernet_MMC
1386    pub ETHERNET_MMC: ETHERNET_MMC,
1387    ///Ethernet_PTP
1388    pub ETHERNET_PTP: ETHERNET_PTP,
1389    ///Ethernet_DMA
1390    pub ETHERNET_DMA: ETHERNET_DMA,
1391    ///CRC
1392    pub CRC: CRC,
1393    ///OTG_FS_GLOBAL
1394    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
1395    ///OTG_FS_HOST
1396    pub OTG_FS_HOST: OTG_FS_HOST,
1397    ///OTG_FS_DEVICE
1398    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
1399    ///OTG_FS_PWRCLK
1400    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
1401    ///CAN1
1402    pub CAN1: CAN1,
1403    ///CAN2
1404    pub CAN2: CAN2,
1405    ///FLASH
1406    pub FLASH: FLASH,
1407    ///EXTI
1408    pub EXTI: EXTI,
1409    ///OTG_HS_GLOBAL
1410    pub OTG_HS_GLOBAL: OTG_HS_GLOBAL,
1411    ///OTG_HS_HOST
1412    pub OTG_HS_HOST: OTG_HS_HOST,
1413    ///OTG_HS_DEVICE
1414    pub OTG_HS_DEVICE: OTG_HS_DEVICE,
1415    ///OTG_HS_PWRCLK
1416    pub OTG_HS_PWRCLK: OTG_HS_PWRCLK,
1417    ///HASH
1418    pub HASH: HASH,
1419    ///CRYP
1420    pub CRYP: CRYP,
1421}
1422impl Peripherals {
1423    /// Returns all the peripherals *once*.
1424    #[cfg(feature = "critical-section")]
1425    #[inline]
1426    pub fn take() -> Option<Self> {
1427        critical_section::with(|_| {
1428            if unsafe { DEVICE_PERIPHERALS } {
1429                return None;
1430            }
1431            Some(unsafe { Peripherals::steal() })
1432        })
1433    }
1434    /// Unchecked version of `Peripherals::take`.
1435    ///
1436    /// # Safety
1437    ///
1438    /// Each of the returned peripherals must be used at most once.
1439    #[inline]
1440    pub unsafe fn steal() -> Self {
1441        DEVICE_PERIPHERALS = true;
1442        Peripherals {
1443            RNG: RNG::steal(),
1444            DCMI: DCMI::steal(),
1445            FSMC: FSMC::steal(),
1446            DBGMCU: DBGMCU::steal(),
1447            DMA2: DMA2::steal(),
1448            DMA1: DMA1::steal(),
1449            RCC: RCC::steal(),
1450            GPIOI: GPIOI::steal(),
1451            GPIOH: GPIOH::steal(),
1452            GPIOG: GPIOG::steal(),
1453            GPIOF: GPIOF::steal(),
1454            GPIOE: GPIOE::steal(),
1455            GPIOD: GPIOD::steal(),
1456            GPIOC: GPIOC::steal(),
1457            GPIOJ: GPIOJ::steal(),
1458            GPIOK: GPIOK::steal(),
1459            GPIOB: GPIOB::steal(),
1460            GPIOA: GPIOA::steal(),
1461            SYSCFG: SYSCFG::steal(),
1462            SPI1: SPI1::steal(),
1463            SPI2: SPI2::steal(),
1464            SPI3: SPI3::steal(),
1465            I2S2EXT: I2S2EXT::steal(),
1466            I2S3EXT: I2S3EXT::steal(),
1467            SDIO: SDIO::steal(),
1468            ADC1: ADC1::steal(),
1469            ADC2: ADC2::steal(),
1470            ADC3: ADC3::steal(),
1471            USART1: USART1::steal(),
1472            USART6: USART6::steal(),
1473            USART2: USART2::steal(),
1474            USART3: USART3::steal(),
1475            DAC: DAC::steal(),
1476            PWR: PWR::steal(),
1477            I2C1: I2C1::steal(),
1478            I2C3: I2C3::steal(),
1479            I2C2: I2C2::steal(),
1480            IWDG: IWDG::steal(),
1481            WWDG: WWDG::steal(),
1482            RTC: RTC::steal(),
1483            UART4: UART4::steal(),
1484            UART5: UART5::steal(),
1485            ADC_COMMON: ADC_COMMON::steal(),
1486            TIM1: TIM1::steal(),
1487            TIM8: TIM8::steal(),
1488            TIM2: TIM2::steal(),
1489            TIM3: TIM3::steal(),
1490            TIM4: TIM4::steal(),
1491            TIM5: TIM5::steal(),
1492            TIM9: TIM9::steal(),
1493            TIM12: TIM12::steal(),
1494            TIM10: TIM10::steal(),
1495            TIM13: TIM13::steal(),
1496            TIM14: TIM14::steal(),
1497            TIM11: TIM11::steal(),
1498            TIM6: TIM6::steal(),
1499            TIM7: TIM7::steal(),
1500            ETHERNET_MAC: ETHERNET_MAC::steal(),
1501            ETHERNET_MMC: ETHERNET_MMC::steal(),
1502            ETHERNET_PTP: ETHERNET_PTP::steal(),
1503            ETHERNET_DMA: ETHERNET_DMA::steal(),
1504            CRC: CRC::steal(),
1505            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1506            OTG_FS_HOST: OTG_FS_HOST::steal(),
1507            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1508            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1509            CAN1: CAN1::steal(),
1510            CAN2: CAN2::steal(),
1511            FLASH: FLASH::steal(),
1512            EXTI: EXTI::steal(),
1513            OTG_HS_GLOBAL: OTG_HS_GLOBAL::steal(),
1514            OTG_HS_HOST: OTG_HS_HOST::steal(),
1515            OTG_HS_DEVICE: OTG_HS_DEVICE::steal(),
1516            OTG_HS_PWRCLK: OTG_HS_PWRCLK::steal(),
1517            HASH: HASH::steal(),
1518            CRYP: CRYP::steal(),
1519        }
1520    }
1521}
stm32f4_staging/stm32f407/mod.rs

stm32f4_staging/stm32f407/
mod.rs
