stm32f4_staging/stm32f407/dcmi/
mis.rs

1///Register `MIS` reader
2pub type R = crate::R<MISrs>;
3/**Capture complete masked interrupt status
4
5Value on reset: 0*/
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum FRAME_MIS {
9    ///0: No interrupt is generated after a complete capture
10    Disabled = 0,
11    ///1: An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER
12    Enabled = 1,
13}
14impl From<FRAME_MIS> for bool {
15    #[inline(always)]
16    fn from(variant: FRAME_MIS) -> Self {
17        variant as u8 != 0
18    }
19}
20///Field `FRAME_MIS` reader - Capture complete masked interrupt status
21pub type FRAME_MIS_R = crate::BitReader<FRAME_MIS>;
22impl FRAME_MIS_R {
23    ///Get enumerated values variant
24    #[inline(always)]
25    pub const fn variant(&self) -> FRAME_MIS {
26        match self.bits {
27            false => FRAME_MIS::Disabled,
28            true => FRAME_MIS::Enabled,
29        }
30    }
31    ///No interrupt is generated after a complete capture
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == FRAME_MIS::Disabled
35    }
36    ///An interrupt is generated at the end of each received frame/crop window (in crop mode) and the FRAME_IE bit is set in DCMI_IER
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == FRAME_MIS::Enabled
40    }
41}
42/**Overrun masked interrupt status
43
44Value on reset: 0*/
45#[cfg_attr(feature = "defmt", derive(defmt::Format))]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum OVR_MIS {
48    ///0: No interrupt is generated on overrun
49    Disabled = 0,
50    ///1: An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER
51    Enabled = 1,
52}
53impl From<OVR_MIS> for bool {
54    #[inline(always)]
55    fn from(variant: OVR_MIS) -> Self {
56        variant as u8 != 0
57    }
58}
59///Field `OVR_MIS` reader - Overrun masked interrupt status
60pub type OVR_MIS_R = crate::BitReader<OVR_MIS>;
61impl OVR_MIS_R {
62    ///Get enumerated values variant
63    #[inline(always)]
64    pub const fn variant(&self) -> OVR_MIS {
65        match self.bits {
66            false => OVR_MIS::Disabled,
67            true => OVR_MIS::Enabled,
68        }
69    }
70    ///No interrupt is generated on overrun
71    #[inline(always)]
72    pub fn is_disabled(&self) -> bool {
73        *self == OVR_MIS::Disabled
74    }
75    ///An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received and the OVR_IE bit is set in DCMI_IER
76    #[inline(always)]
77    pub fn is_enabled(&self) -> bool {
78        *self == OVR_MIS::Enabled
79    }
80}
81/**Synchronization error masked interrupt status
82
83Value on reset: 0*/
84#[cfg_attr(feature = "defmt", derive(defmt::Format))]
85#[derive(Clone, Copy, Debug, PartialEq, Eq)]
86pub enum ERR_MIS {
87    ///0: No interrupt is generated on a synchronization error
88    Disabled = 0,
89    ///1: An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set
90    Enabled = 1,
91}
92impl From<ERR_MIS> for bool {
93    #[inline(always)]
94    fn from(variant: ERR_MIS) -> Self {
95        variant as u8 != 0
96    }
97}
98///Field `ERR_MIS` reader - Synchronization error masked interrupt status
99pub type ERR_MIS_R = crate::BitReader<ERR_MIS>;
100impl ERR_MIS_R {
101    ///Get enumerated values variant
102    #[inline(always)]
103    pub const fn variant(&self) -> ERR_MIS {
104        match self.bits {
105            false => ERR_MIS::Disabled,
106            true => ERR_MIS::Enabled,
107        }
108    }
109    ///No interrupt is generated on a synchronization error
110    #[inline(always)]
111    pub fn is_disabled(&self) -> bool {
112        *self == ERR_MIS::Disabled
113    }
114    ///An interrupt is generated if the embedded synchronization codes are not received in the correct order and the ERR_IE bit in DCMI_IER is set
115    #[inline(always)]
116    pub fn is_enabled(&self) -> bool {
117        *self == ERR_MIS::Enabled
118    }
119}
120/**VSYNC masked interrupt status
121
122Value on reset: 0*/
123#[cfg_attr(feature = "defmt", derive(defmt::Format))]
124#[derive(Clone, Copy, Debug, PartialEq, Eq)]
125pub enum VSYNC_MIS {
126    ///0: No interrupt is generated on DCMI_VSYNC transitions
127    Disabled = 0,
128    ///1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER
129    Enabled = 1,
130}
131impl From<VSYNC_MIS> for bool {
132    #[inline(always)]
133    fn from(variant: VSYNC_MIS) -> Self {
134        variant as u8 != 0
135    }
136}
137///Field `VSYNC_MIS` reader - VSYNC masked interrupt status
138pub type VSYNC_MIS_R = crate::BitReader<VSYNC_MIS>;
139impl VSYNC_MIS_R {
140    ///Get enumerated values variant
141    #[inline(always)]
142    pub const fn variant(&self) -> VSYNC_MIS {
143        match self.bits {
144            false => VSYNC_MIS::Disabled,
145            true => VSYNC_MIS::Enabled,
146        }
147    }
148    ///No interrupt is generated on DCMI_VSYNC transitions
149    #[inline(always)]
150    pub fn is_disabled(&self) -> bool {
151        *self == VSYNC_MIS::Disabled
152    }
153    ///An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state and the VSYNC_IE bit is set in DCMI_IER
154    #[inline(always)]
155    pub fn is_enabled(&self) -> bool {
156        *self == VSYNC_MIS::Enabled
157    }
158}
159/**Line masked interrupt status
160
161Value on reset: 0*/
162#[cfg_attr(feature = "defmt", derive(defmt::Format))]
163#[derive(Clone, Copy, Debug, PartialEq, Eq)]
164pub enum LINE_MIS {
165    ///0: No interrupt generation when the line is received
166    Disabled = 0,
167    ///1: An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER
168    Enabled = 1,
169}
170impl From<LINE_MIS> for bool {
171    #[inline(always)]
172    fn from(variant: LINE_MIS) -> Self {
173        variant as u8 != 0
174    }
175}
176///Field `LINE_MIS` reader - Line masked interrupt status
177pub type LINE_MIS_R = crate::BitReader<LINE_MIS>;
178impl LINE_MIS_R {
179    ///Get enumerated values variant
180    #[inline(always)]
181    pub const fn variant(&self) -> LINE_MIS {
182        match self.bits {
183            false => LINE_MIS::Disabled,
184            true => LINE_MIS::Enabled,
185        }
186    }
187    ///No interrupt generation when the line is received
188    #[inline(always)]
189    pub fn is_disabled(&self) -> bool {
190        *self == LINE_MIS::Disabled
191    }
192    ///An Interrupt is generated when a line has been completely received and the LINE_IE bit is set in DCMI_IER
193    #[inline(always)]
194    pub fn is_enabled(&self) -> bool {
195        *self == LINE_MIS::Enabled
196    }
197}
198impl R {
199    ///Bit 0 - Capture complete masked interrupt status
200    #[inline(always)]
201    pub fn frame_mis(&self) -> FRAME_MIS_R {
202        FRAME_MIS_R::new((self.bits & 1) != 0)
203    }
204    ///Bit 1 - Overrun masked interrupt status
205    #[inline(always)]
206    pub fn ovr_mis(&self) -> OVR_MIS_R {
207        OVR_MIS_R::new(((self.bits >> 1) & 1) != 0)
208    }
209    ///Bit 2 - Synchronization error masked interrupt status
210    #[inline(always)]
211    pub fn err_mis(&self) -> ERR_MIS_R {
212        ERR_MIS_R::new(((self.bits >> 2) & 1) != 0)
213    }
214    ///Bit 3 - VSYNC masked interrupt status
215    #[inline(always)]
216    pub fn vsync_mis(&self) -> VSYNC_MIS_R {
217        VSYNC_MIS_R::new(((self.bits >> 3) & 1) != 0)
218    }
219    ///Bit 4 - Line masked interrupt status
220    #[inline(always)]
221    pub fn line_mis(&self) -> LINE_MIS_R {
222        LINE_MIS_R::new(((self.bits >> 4) & 1) != 0)
223    }
224}
225impl core::fmt::Debug for R {
226    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
227        f.debug_struct("MIS")
228            .field("line_mis", &self.line_mis())
229            .field("vsync_mis", &self.vsync_mis())
230            .field("err_mis", &self.err_mis())
231            .field("ovr_mis", &self.ovr_mis())
232            .field("frame_mis", &self.frame_mis())
233            .finish()
234    }
235}
236/**masked interrupt status register
237
238You can [`read`](crate::Reg::read) this register and get [`mis::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api).
239
240See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:MIS)*/
241pub struct MISrs;
242impl crate::RegisterSpec for MISrs {
243    type Ux = u32;
244}
245///`read()` method returns [`mis::R`](R) reader structure
246impl crate::Readable for MISrs {}
247///`reset()` method sets MIS to value 0
248impl crate::Resettable for MISrs {}
stm32f4_staging/stm32f407/dcmi/mis.rs

stm32f4_staging/stm32f407/dcmi/
mis.rs
