stm32f4_staging/stm32f407/dcmi/
ier.rs

1///Register `IER` reader
2pub type R = crate::R<IERrs>;
3///Register `IER` writer
4pub type W = crate::W<IERrs>;
5/**Capture complete interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum FRAME_IE {
11    ///0: No interrupt generation
12    Disabled = 0,
13    ///1: An interrupt is generated at the end of each received frame/crop window (in crop mode)
14    Enabled = 1,
15}
16impl From<FRAME_IE> for bool {
17    #[inline(always)]
18    fn from(variant: FRAME_IE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `FRAME_IE` reader - Capture complete interrupt enable
23pub type FRAME_IE_R = crate::BitReader<FRAME_IE>;
24impl FRAME_IE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> FRAME_IE {
28        match self.bits {
29            false => FRAME_IE::Disabled,
30            true => FRAME_IE::Enabled,
31        }
32    }
33    ///No interrupt generation
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == FRAME_IE::Disabled
37    }
38    ///An interrupt is generated at the end of each received frame/crop window (in crop mode)
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == FRAME_IE::Enabled
42    }
43}
44///Field `FRAME_IE` writer - Capture complete interrupt enable
45pub type FRAME_IE_W<'a, REG> = crate::BitWriter<'a, REG, FRAME_IE>;
46impl<'a, REG> FRAME_IE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///No interrupt generation
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(FRAME_IE::Disabled)
54    }
55    ///An interrupt is generated at the end of each received frame/crop window (in crop mode)
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(FRAME_IE::Enabled)
59    }
60}
61/**Overrun interrupt enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum OVR_IE {
67    ///0: No interrupt generation
68    Disabled = 0,
69    ///1: An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received
70    Enabled = 1,
71}
72impl From<OVR_IE> for bool {
73    #[inline(always)]
74    fn from(variant: OVR_IE) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `OVR_IE` reader - Overrun interrupt enable
79pub type OVR_IE_R = crate::BitReader<OVR_IE>;
80impl OVR_IE_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> OVR_IE {
84        match self.bits {
85            false => OVR_IE::Disabled,
86            true => OVR_IE::Enabled,
87        }
88    }
89    ///No interrupt generation
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == OVR_IE::Disabled
93    }
94    ///An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == OVR_IE::Enabled
98    }
99}
100///Field `OVR_IE` writer - Overrun interrupt enable
101pub type OVR_IE_W<'a, REG> = crate::BitWriter<'a, REG, OVR_IE>;
102impl<'a, REG> OVR_IE_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///No interrupt generation
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(OVR_IE::Disabled)
110    }
111    ///An interrupt is generated if the DMA was not able to transfer the last data before new data (32-bit) are received
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(OVR_IE::Enabled)
115    }
116}
117/**Synchronization error interrupt enable
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum ERR_IE {
123    ///0: No interrupt generation
124    Disabled = 0,
125    ///1: An interrupt is generated if the embedded synchronization codes are not received in the correct order
126    Enabled = 1,
127}
128impl From<ERR_IE> for bool {
129    #[inline(always)]
130    fn from(variant: ERR_IE) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `ERR_IE` reader - Synchronization error interrupt enable
135pub type ERR_IE_R = crate::BitReader<ERR_IE>;
136impl ERR_IE_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> ERR_IE {
140        match self.bits {
141            false => ERR_IE::Disabled,
142            true => ERR_IE::Enabled,
143        }
144    }
145    ///No interrupt generation
146    #[inline(always)]
147    pub fn is_disabled(&self) -> bool {
148        *self == ERR_IE::Disabled
149    }
150    ///An interrupt is generated if the embedded synchronization codes are not received in the correct order
151    #[inline(always)]
152    pub fn is_enabled(&self) -> bool {
153        *self == ERR_IE::Enabled
154    }
155}
156///Field `ERR_IE` writer - Synchronization error interrupt enable
157pub type ERR_IE_W<'a, REG> = crate::BitWriter<'a, REG, ERR_IE>;
158impl<'a, REG> ERR_IE_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///No interrupt generation
163    #[inline(always)]
164    pub fn disabled(self) -> &'a mut crate::W<REG> {
165        self.variant(ERR_IE::Disabled)
166    }
167    ///An interrupt is generated if the embedded synchronization codes are not received in the correct order
168    #[inline(always)]
169    pub fn enabled(self) -> &'a mut crate::W<REG> {
170        self.variant(ERR_IE::Enabled)
171    }
172}
173/**VSYNC interrupt enable
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum VSYNC_IE {
179    ///0: No interrupt generation
180    Disabled = 0,
181    ///1: An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state
182    Enabled = 1,
183}
184impl From<VSYNC_IE> for bool {
185    #[inline(always)]
186    fn from(variant: VSYNC_IE) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `VSYNC_IE` reader - VSYNC interrupt enable
191pub type VSYNC_IE_R = crate::BitReader<VSYNC_IE>;
192impl VSYNC_IE_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> VSYNC_IE {
196        match self.bits {
197            false => VSYNC_IE::Disabled,
198            true => VSYNC_IE::Enabled,
199        }
200    }
201    ///No interrupt generation
202    #[inline(always)]
203    pub fn is_disabled(&self) -> bool {
204        *self == VSYNC_IE::Disabled
205    }
206    ///An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state
207    #[inline(always)]
208    pub fn is_enabled(&self) -> bool {
209        *self == VSYNC_IE::Enabled
210    }
211}
212///Field `VSYNC_IE` writer - VSYNC interrupt enable
213pub type VSYNC_IE_W<'a, REG> = crate::BitWriter<'a, REG, VSYNC_IE>;
214impl<'a, REG> VSYNC_IE_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///No interrupt generation
219    #[inline(always)]
220    pub fn disabled(self) -> &'a mut crate::W<REG> {
221        self.variant(VSYNC_IE::Disabled)
222    }
223    ///An interrupt is generated on each DCMI_VSYNC transition from the inactive to the active state
224    #[inline(always)]
225    pub fn enabled(self) -> &'a mut crate::W<REG> {
226        self.variant(VSYNC_IE::Enabled)
227    }
228}
229/**Line interrupt enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum LINE_IE {
235    ///0: No interrupt generation when the line is received
236    Disabled = 0,
237    ///1: An Interrupt is generated when a line has been completely received
238    Enabled = 1,
239}
240impl From<LINE_IE> for bool {
241    #[inline(always)]
242    fn from(variant: LINE_IE) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `LINE_IE` reader - Line interrupt enable
247pub type LINE_IE_R = crate::BitReader<LINE_IE>;
248impl LINE_IE_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> LINE_IE {
252        match self.bits {
253            false => LINE_IE::Disabled,
254            true => LINE_IE::Enabled,
255        }
256    }
257    ///No interrupt generation when the line is received
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == LINE_IE::Disabled
261    }
262    ///An Interrupt is generated when a line has been completely received
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == LINE_IE::Enabled
266    }
267}
268///Field `LINE_IE` writer - Line interrupt enable
269pub type LINE_IE_W<'a, REG> = crate::BitWriter<'a, REG, LINE_IE>;
270impl<'a, REG> LINE_IE_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///No interrupt generation when the line is received
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(LINE_IE::Disabled)
278    }
279    ///An Interrupt is generated when a line has been completely received
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(LINE_IE::Enabled)
283    }
284}
285impl R {
286    ///Bit 0 - Capture complete interrupt enable
287    #[inline(always)]
288    pub fn frame_ie(&self) -> FRAME_IE_R {
289        FRAME_IE_R::new((self.bits & 1) != 0)
290    }
291    ///Bit 1 - Overrun interrupt enable
292    #[inline(always)]
293    pub fn ovr_ie(&self) -> OVR_IE_R {
294        OVR_IE_R::new(((self.bits >> 1) & 1) != 0)
295    }
296    ///Bit 2 - Synchronization error interrupt enable
297    #[inline(always)]
298    pub fn err_ie(&self) -> ERR_IE_R {
299        ERR_IE_R::new(((self.bits >> 2) & 1) != 0)
300    }
301    ///Bit 3 - VSYNC interrupt enable
302    #[inline(always)]
303    pub fn vsync_ie(&self) -> VSYNC_IE_R {
304        VSYNC_IE_R::new(((self.bits >> 3) & 1) != 0)
305    }
306    ///Bit 4 - Line interrupt enable
307    #[inline(always)]
308    pub fn line_ie(&self) -> LINE_IE_R {
309        LINE_IE_R::new(((self.bits >> 4) & 1) != 0)
310    }
311}
312impl core::fmt::Debug for R {
313    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
314        f.debug_struct("IER")
315            .field("line_ie", &self.line_ie())
316            .field("vsync_ie", &self.vsync_ie())
317            .field("err_ie", &self.err_ie())
318            .field("ovr_ie", &self.ovr_ie())
319            .field("frame_ie", &self.frame_ie())
320            .finish()
321    }
322}
323impl W {
324    ///Bit 0 - Capture complete interrupt enable
325    #[inline(always)]
326    pub fn frame_ie(&mut self) -> FRAME_IE_W<IERrs> {
327        FRAME_IE_W::new(self, 0)
328    }
329    ///Bit 1 - Overrun interrupt enable
330    #[inline(always)]
331    pub fn ovr_ie(&mut self) -> OVR_IE_W<IERrs> {
332        OVR_IE_W::new(self, 1)
333    }
334    ///Bit 2 - Synchronization error interrupt enable
335    #[inline(always)]
336    pub fn err_ie(&mut self) -> ERR_IE_W<IERrs> {
337        ERR_IE_W::new(self, 2)
338    }
339    ///Bit 3 - VSYNC interrupt enable
340    #[inline(always)]
341    pub fn vsync_ie(&mut self) -> VSYNC_IE_W<IERrs> {
342        VSYNC_IE_W::new(self, 3)
343    }
344    ///Bit 4 - Line interrupt enable
345    #[inline(always)]
346    pub fn line_ie(&mut self) -> LINE_IE_W<IERrs> {
347        LINE_IE_W::new(self, 4)
348    }
349}
350/**interrupt enable register
351
352You can [`read`](crate::Reg::read) this register and get [`ier::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
353
354See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:IER)*/
355pub struct IERrs;
356impl crate::RegisterSpec for IERrs {
357    type Ux = u32;
358}
359///`read()` method returns [`ier::R`](R) reader structure
360impl crate::Readable for IERrs {}
361///`write(|w| ..)` method takes [`ier::W`](W) writer structure
362impl crate::Writable for IERrs {
363    type Safety = crate::Unsafe;
364}
365///`reset()` method sets IER to value 0
366impl crate::Resettable for IERrs {}
stm32f4_staging/stm32f407/dcmi/ier.rs

stm32f4_staging/stm32f407/dcmi/
ier.rs
