stm32f4_staging/stm32f407/
dcmi.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr: CR,
6    sr: SR,
7    ris: RIS,
8    ier: IER,
9    mis: MIS,
10    icr: ICR,
11    escr: ESCR,
12    esur: ESUR,
13    cwstrt: CWSTRT,
14    cwsize: CWSIZE,
15    dr: DR,
16}
17impl RegisterBlock {
18    ///0x00 - control register 1
19    #[inline(always)]
20    pub const fn cr(&self) -> &CR {
21        &self.cr
22    }
23    ///0x04 - status register
24    #[inline(always)]
25    pub const fn sr(&self) -> &SR {
26        &self.sr
27    }
28    ///0x08 - raw interrupt status register
29    #[inline(always)]
30    pub const fn ris(&self) -> &RIS {
31        &self.ris
32    }
33    ///0x0c - interrupt enable register
34    #[inline(always)]
35    pub const fn ier(&self) -> &IER {
36        &self.ier
37    }
38    ///0x10 - masked interrupt status register
39    #[inline(always)]
40    pub const fn mis(&self) -> &MIS {
41        &self.mis
42    }
43    ///0x14 - interrupt clear register
44    #[inline(always)]
45    pub const fn icr(&self) -> &ICR {
46        &self.icr
47    }
48    ///0x18 - embedded synchronization code register
49    #[inline(always)]
50    pub const fn escr(&self) -> &ESCR {
51        &self.escr
52    }
53    ///0x1c - embedded synchronization unmask register
54    #[inline(always)]
55    pub const fn esur(&self) -> &ESUR {
56        &self.esur
57    }
58    ///0x20 - crop window start
59    #[inline(always)]
60    pub const fn cwstrt(&self) -> &CWSTRT {
61        &self.cwstrt
62    }
63    ///0x24 - crop window size
64    #[inline(always)]
65    pub const fn cwsize(&self) -> &CWSIZE {
66        &self.cwsize
67    }
68    ///0x28 - data register
69    #[inline(always)]
70    pub const fn dr(&self) -> &DR {
71        &self.dr
72    }
73}
74/**CR (rw) register accessor: control register 1
75
76You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
77
78See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:CR)
79
80For information about available fields see [`mod@cr`] module*/
81pub type CR = crate::Reg<cr::CRrs>;
82///control register 1
83pub mod cr;
84/**SR (r) register accessor: status register
85
86You can [`read`](crate::Reg::read) this register and get [`sr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
87
88See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:SR)
89
90For information about available fields see [`mod@sr`] module*/
91pub type SR = crate::Reg<sr::SRrs>;
92///status register
93pub mod sr;
94/**RIS (r) register accessor: raw interrupt status register
95
96You can [`read`](crate::Reg::read) this register and get [`ris::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
97
98See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:RIS)
99
100For information about available fields see [`mod@ris`] module*/
101pub type RIS = crate::Reg<ris::RISrs>;
102///raw interrupt status register
103pub mod ris;
104/**IER (rw) register accessor: interrupt enable register
105
106You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
107
108See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:IER)
109
110For information about available fields see [`mod@ier`] module*/
111pub type IER = crate::Reg<ier::IERrs>;
112///interrupt enable register
113pub mod ier;
114/**MIS (r) register accessor: masked interrupt status register
115
116You can [`read`](crate::Reg::read) this register and get [`mis::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
117
118See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:MIS)
119
120For information about available fields see [`mod@mis`] module*/
121pub type MIS = crate::Reg<mis::MISrs>;
122///masked interrupt status register
123pub mod mis;
124/**ICR (w) register accessor: interrupt clear register
125
126You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
127
128See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:ICR)
129
130For information about available fields see [`mod@icr`] module*/
131pub type ICR = crate::Reg<icr::ICRrs>;
132///interrupt clear register
133pub mod icr;
134/**ESCR (rw) register accessor: embedded synchronization code register
135
136You can [`read`](crate::Reg::read) this register and get [`escr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`escr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
137
138See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:ESCR)
139
140For information about available fields see [`mod@escr`] module*/
141pub type ESCR = crate::Reg<escr::ESCRrs>;
142///embedded synchronization code register
143pub mod escr;
144/**ESUR (rw) register accessor: embedded synchronization unmask register
145
146You can [`read`](crate::Reg::read) this register and get [`esur::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`esur::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
147
148See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:ESUR)
149
150For information about available fields see [`mod@esur`] module*/
151pub type ESUR = crate::Reg<esur::ESURrs>;
152///embedded synchronization unmask register
153pub mod esur;
154/**CWSTRT (rw) register accessor: crop window start
155
156You can [`read`](crate::Reg::read) this register and get [`cwstrt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwstrt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
157
158See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:CWSTRT)
159
160For information about available fields see [`mod@cwstrt`] module*/
161pub type CWSTRT = crate::Reg<cwstrt::CWSTRTrs>;
162///crop window start
163pub mod cwstrt;
164/**CWSIZE (rw) register accessor: crop window size
165
166You can [`read`](crate::Reg::read) this register and get [`cwsize::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cwsize::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
167
168See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:CWSIZE)
169
170For information about available fields see [`mod@cwsize`] module*/
171pub type CWSIZE = crate::Reg<cwsize::CWSIZErs>;
172///crop window size
173pub mod cwsize;
174/**DR (r) register accessor: data register
175
176You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
177
178See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F407.html#DCMI:DR)
179
180For information about available fields see [`mod@dr`] module*/
181pub type DR = crate::Reg<dr::DRrs>;
182///data register
183pub mod dr;
stm32f4_staging/stm32f407/dcmi.rs

stm32f4_staging/stm32f407/
dcmi.rs
