stm32f4_staging/stm32f401/
tim11.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    _reserved1: [u8; 0x08],
7    dier: DIER,
8    sr: SR,
9    egr: EGR,
10    _reserved_4_ccmr1: [u8; 0x04],
11    _reserved5: [u8; 0x04],
12    ccer: CCER,
13    cnt: CNT,
14    psc: PSC,
15    arr: ARR,
16    _reserved9: [u8; 0x04],
17    ccr: [CCR; 1],
18    _reserved10: [u8; 0x18],
19    or: OR,
20}
21impl RegisterBlock {
22    ///0x00 - control register 1
23    #[inline(always)]
24    pub const fn cr1(&self) -> &CR1 {
25        &self.cr1
26    }
27    ///0x0c - DMA/Interrupt enable register
28    #[inline(always)]
29    pub const fn dier(&self) -> &DIER {
30        &self.dier
31    }
32    ///0x10 - status register
33    #[inline(always)]
34    pub const fn sr(&self) -> &SR {
35        &self.sr
36    }
37    ///0x14 - event generation register
38    #[inline(always)]
39    pub const fn egr(&self) -> &EGR {
40        &self.egr
41    }
42    ///0x18 - capture/compare mode register 1 (input mode)
43    #[inline(always)]
44    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
45        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
46    }
47    ///0x18 - capture/compare mode register 1 (output mode)
48    #[inline(always)]
49    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
50        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
51    }
52    ///0x20 - capture/compare enable register
53    #[inline(always)]
54    pub const fn ccer(&self) -> &CCER {
55        &self.ccer
56    }
57    ///0x24 - counter
58    #[inline(always)]
59    pub const fn cnt(&self) -> &CNT {
60        &self.cnt
61    }
62    ///0x28 - prescaler
63    #[inline(always)]
64    pub const fn psc(&self) -> &PSC {
65        &self.psc
66    }
67    ///0x2c - auto-reload register
68    #[inline(always)]
69    pub const fn arr(&self) -> &ARR {
70        &self.arr
71    }
72    ///0x34 - capture/compare register
73    ///
74    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
75    #[inline(always)]
76    pub const fn ccr(&self, n: usize) -> &CCR {
77        &self.ccr[n]
78    }
79    ///Iterator for array of:
80    ///0x34 - capture/compare register
81    #[inline(always)]
82    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
83        self.ccr.iter()
84    }
85    ///0x34 - capture/compare register
86    #[inline(always)]
87    pub const fn ccr1(&self) -> &CCR {
88        self.ccr(0)
89    }
90    ///0x50 - option register
91    #[inline(always)]
92    pub const fn or(&self) -> &OR {
93        &self.or
94    }
95}
96pub use crate::stm32f401::tim10::arr;
97pub use crate::stm32f401::tim10::ccer;
98pub use crate::stm32f401::tim10::ccmr1_input;
99pub use crate::stm32f401::tim10::ccmr1_output;
100pub use crate::stm32f401::tim10::ccr;
101pub use crate::stm32f401::tim10::cnt;
102pub use crate::stm32f401::tim10::cr1;
103pub use crate::stm32f401::tim10::dier;
104pub use crate::stm32f401::tim10::egr;
105pub use crate::stm32f401::tim10::psc;
106pub use crate::stm32f401::tim10::sr;
107pub use crate::stm32f401::tim10::ARR;
108pub use crate::stm32f401::tim10::CCER;
109pub use crate::stm32f401::tim10::CCMR1_INPUT;
110pub use crate::stm32f401::tim10::CCMR1_OUTPUT;
111pub use crate::stm32f401::tim10::CCR;
112pub use crate::stm32f401::tim10::CNT;
113pub use crate::stm32f401::tim10::CR1;
114pub use crate::stm32f401::tim10::DIER;
115pub use crate::stm32f401::tim10::EGR;
116pub use crate::stm32f401::tim10::PSC;
117pub use crate::stm32f401::tim10::SR;
118/**OR (rw) register accessor: option register
119
120You can [`read`](crate::Reg::read) this register and get [`or::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`or::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
121
122See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#TIM11:OR)
123
124For information about available fields see [`mod@or`] module*/
125pub type OR = crate::Reg<or::ORrs>;
126///option register
127pub mod or;
stm32f4_staging/stm32f401/tim11.rs

stm32f4_staging/stm32f401/
tim11.rs
