stm32f4_staging/stm32f401/gpioh/
ospeedr.rs

1///Register `OSPEEDR` reader
2pub type R = crate::R<OSPEEDRrs>;
3///Register `OSPEEDR` writer
4pub type W = crate::W<OSPEEDRrs>;
5///Field `OSPEEDR(0-15)` reader - Port x configuration pin %s
6pub use crate::stm32f401::gpioa::ospeedr::OSPEEDR_R;
7///Field `OSPEEDR(0-15)` writer - Port x configuration pin %s
8pub use crate::stm32f401::gpioa::ospeedr::OSPEEDR_W;
9///Port x configuration pin %s
10pub use crate::stm32f401::gpioa::ospeedr::OUTPUT_SPEED;
11impl R {
12    ///Port x configuration pin (0-15)
13    ///
14    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
15    #[inline(always)]
16    pub fn ospeedr(&self, n: u8) -> OSPEEDR_R {
17        #[allow(clippy::no_effect)]
18        [(); 16][n as usize];
19        OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8)
20    }
21    ///Iterator for array of:
22    ///Port x configuration pin (0-15)
23    #[inline(always)]
24    pub fn ospeedr_iter(&self) -> impl Iterator<Item = OSPEEDR_R> + '_ {
25        (0..16).map(move |n| OSPEEDR_R::new(((self.bits >> (n * 2)) & 3) as u8))
26    }
27    ///Bits 0:1 - Port x configuration pin 0
28    #[inline(always)]
29    pub fn ospeedr0(&self) -> OSPEEDR_R {
30        OSPEEDR_R::new((self.bits & 3) as u8)
31    }
32    ///Bits 2:3 - Port x configuration pin 1
33    #[inline(always)]
34    pub fn ospeedr1(&self) -> OSPEEDR_R {
35        OSPEEDR_R::new(((self.bits >> 2) & 3) as u8)
36    }
37    ///Bits 4:5 - Port x configuration pin 2
38    #[inline(always)]
39    pub fn ospeedr2(&self) -> OSPEEDR_R {
40        OSPEEDR_R::new(((self.bits >> 4) & 3) as u8)
41    }
42    ///Bits 6:7 - Port x configuration pin 3
43    #[inline(always)]
44    pub fn ospeedr3(&self) -> OSPEEDR_R {
45        OSPEEDR_R::new(((self.bits >> 6) & 3) as u8)
46    }
47    ///Bits 8:9 - Port x configuration pin 4
48    #[inline(always)]
49    pub fn ospeedr4(&self) -> OSPEEDR_R {
50        OSPEEDR_R::new(((self.bits >> 8) & 3) as u8)
51    }
52    ///Bits 10:11 - Port x configuration pin 5
53    #[inline(always)]
54    pub fn ospeedr5(&self) -> OSPEEDR_R {
55        OSPEEDR_R::new(((self.bits >> 10) & 3) as u8)
56    }
57    ///Bits 12:13 - Port x configuration pin 6
58    #[inline(always)]
59    pub fn ospeedr6(&self) -> OSPEEDR_R {
60        OSPEEDR_R::new(((self.bits >> 12) & 3) as u8)
61    }
62    ///Bits 14:15 - Port x configuration pin 7
63    #[inline(always)]
64    pub fn ospeedr7(&self) -> OSPEEDR_R {
65        OSPEEDR_R::new(((self.bits >> 14) & 3) as u8)
66    }
67    ///Bits 16:17 - Port x configuration pin 8
68    #[inline(always)]
69    pub fn ospeedr8(&self) -> OSPEEDR_R {
70        OSPEEDR_R::new(((self.bits >> 16) & 3) as u8)
71    }
72    ///Bits 18:19 - Port x configuration pin 9
73    #[inline(always)]
74    pub fn ospeedr9(&self) -> OSPEEDR_R {
75        OSPEEDR_R::new(((self.bits >> 18) & 3) as u8)
76    }
77    ///Bits 20:21 - Port x configuration pin 10
78    #[inline(always)]
79    pub fn ospeedr10(&self) -> OSPEEDR_R {
80        OSPEEDR_R::new(((self.bits >> 20) & 3) as u8)
81    }
82    ///Bits 22:23 - Port x configuration pin 11
83    #[inline(always)]
84    pub fn ospeedr11(&self) -> OSPEEDR_R {
85        OSPEEDR_R::new(((self.bits >> 22) & 3) as u8)
86    }
87    ///Bits 24:25 - Port x configuration pin 12
88    #[inline(always)]
89    pub fn ospeedr12(&self) -> OSPEEDR_R {
90        OSPEEDR_R::new(((self.bits >> 24) & 3) as u8)
91    }
92    ///Bits 26:27 - Port x configuration pin 13
93    #[inline(always)]
94    pub fn ospeedr13(&self) -> OSPEEDR_R {
95        OSPEEDR_R::new(((self.bits >> 26) & 3) as u8)
96    }
97    ///Bits 28:29 - Port x configuration pin 14
98    #[inline(always)]
99    pub fn ospeedr14(&self) -> OSPEEDR_R {
100        OSPEEDR_R::new(((self.bits >> 28) & 3) as u8)
101    }
102    ///Bits 30:31 - Port x configuration pin 15
103    #[inline(always)]
104    pub fn ospeedr15(&self) -> OSPEEDR_R {
105        OSPEEDR_R::new(((self.bits >> 30) & 3) as u8)
106    }
107}
108impl core::fmt::Debug for R {
109    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
110        f.debug_struct("OSPEEDR")
111            .field("ospeedr0", &self.ospeedr0())
112            .field("ospeedr1", &self.ospeedr1())
113            .field("ospeedr2", &self.ospeedr2())
114            .field("ospeedr3", &self.ospeedr3())
115            .field("ospeedr4", &self.ospeedr4())
116            .field("ospeedr5", &self.ospeedr5())
117            .field("ospeedr6", &self.ospeedr6())
118            .field("ospeedr7", &self.ospeedr7())
119            .field("ospeedr8", &self.ospeedr8())
120            .field("ospeedr9", &self.ospeedr9())
121            .field("ospeedr10", &self.ospeedr10())
122            .field("ospeedr11", &self.ospeedr11())
123            .field("ospeedr12", &self.ospeedr12())
124            .field("ospeedr13", &self.ospeedr13())
125            .field("ospeedr14", &self.ospeedr14())
126            .field("ospeedr15", &self.ospeedr15())
127            .finish()
128    }
129}
130impl W {
131    ///Port x configuration pin (0-15)
132    ///
133    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OSPEEDR0` field.</div>
134    #[inline(always)]
135    pub fn ospeedr(&mut self, n: u8) -> OSPEEDR_W<OSPEEDRrs> {
136        #[allow(clippy::no_effect)]
137        [(); 16][n as usize];
138        OSPEEDR_W::new(self, n * 2)
139    }
140    ///Bits 0:1 - Port x configuration pin 0
141    #[inline(always)]
142    pub fn ospeedr0(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
143        OSPEEDR_W::new(self, 0)
144    }
145    ///Bits 2:3 - Port x configuration pin 1
146    #[inline(always)]
147    pub fn ospeedr1(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
148        OSPEEDR_W::new(self, 2)
149    }
150    ///Bits 4:5 - Port x configuration pin 2
151    #[inline(always)]
152    pub fn ospeedr2(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
153        OSPEEDR_W::new(self, 4)
154    }
155    ///Bits 6:7 - Port x configuration pin 3
156    #[inline(always)]
157    pub fn ospeedr3(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
158        OSPEEDR_W::new(self, 6)
159    }
160    ///Bits 8:9 - Port x configuration pin 4
161    #[inline(always)]
162    pub fn ospeedr4(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
163        OSPEEDR_W::new(self, 8)
164    }
165    ///Bits 10:11 - Port x configuration pin 5
166    #[inline(always)]
167    pub fn ospeedr5(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
168        OSPEEDR_W::new(self, 10)
169    }
170    ///Bits 12:13 - Port x configuration pin 6
171    #[inline(always)]
172    pub fn ospeedr6(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
173        OSPEEDR_W::new(self, 12)
174    }
175    ///Bits 14:15 - Port x configuration pin 7
176    #[inline(always)]
177    pub fn ospeedr7(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
178        OSPEEDR_W::new(self, 14)
179    }
180    ///Bits 16:17 - Port x configuration pin 8
181    #[inline(always)]
182    pub fn ospeedr8(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
183        OSPEEDR_W::new(self, 16)
184    }
185    ///Bits 18:19 - Port x configuration pin 9
186    #[inline(always)]
187    pub fn ospeedr9(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
188        OSPEEDR_W::new(self, 18)
189    }
190    ///Bits 20:21 - Port x configuration pin 10
191    #[inline(always)]
192    pub fn ospeedr10(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
193        OSPEEDR_W::new(self, 20)
194    }
195    ///Bits 22:23 - Port x configuration pin 11
196    #[inline(always)]
197    pub fn ospeedr11(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
198        OSPEEDR_W::new(self, 22)
199    }
200    ///Bits 24:25 - Port x configuration pin 12
201    #[inline(always)]
202    pub fn ospeedr12(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
203        OSPEEDR_W::new(self, 24)
204    }
205    ///Bits 26:27 - Port x configuration pin 13
206    #[inline(always)]
207    pub fn ospeedr13(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
208        OSPEEDR_W::new(self, 26)
209    }
210    ///Bits 28:29 - Port x configuration pin 14
211    #[inline(always)]
212    pub fn ospeedr14(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
213        OSPEEDR_W::new(self, 28)
214    }
215    ///Bits 30:31 - Port x configuration pin 15
216    #[inline(always)]
217    pub fn ospeedr15(&mut self) -> OSPEEDR_W<OSPEEDRrs> {
218        OSPEEDR_W::new(self, 30)
219    }
220}
221/**GPIO port output speed register
222
223You can [`read`](crate::Reg::read) this register and get [`ospeedr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ospeedr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
224
225See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F401.html#GPIOH:OSPEEDR)*/
226pub struct OSPEEDRrs;
227impl crate::RegisterSpec for OSPEEDRrs {
228    type Ux = u32;
229}
230///`read()` method returns [`ospeedr::R`](R) reader structure
231impl crate::Readable for OSPEEDRrs {}
232///`write(|w| ..)` method takes [`ospeedr::W`](W) writer structure
233impl crate::Writable for OSPEEDRrs {
234    type Safety = crate::Unsafe;
235}
236///`reset()` method sets OSPEEDR to value 0
237impl crate::Resettable for OSPEEDRrs {}
stm32f4_staging/stm32f401/gpioh/ospeedr.rs

stm32f4_staging/stm32f401/gpioh/
ospeedr.rs
