[−][src]Struct stm32f3xx_hal_v2::pac::can::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub mcr: Reg<u32, _MCR>,
    pub msr: Reg<u32, _MSR>,
    pub tsr: Reg<u32, _TSR>,
    pub rfr: [Reg<u32, _RFR>; 2],
    pub ier: Reg<u32, _IER>,
    pub esr: Reg<u32, _ESR>,
    pub btr: Reg<u32, _BTR>,
    pub tx: [TX; 3],
    pub rx: [RX; 2],
    pub fmr: Reg<u32, _FMR>,
    pub fm1r: Reg<u32, _FM1R>,
    pub fs1r: Reg<u32, _FS1R>,
    pub ffa1r: Reg<u32, _FFA1R>,
    pub fa1r: Reg<u32, _FA1R>,
    pub fb: [FB; 28],
    // some fields omitted
}

Register block

Fields

mcr: Reg<u32, _MCR>

0x00 - master control register

msr: Reg<u32, _MSR>

0x04 - master status register

tsr: Reg<u32, _TSR>

0x08 - transmit status register

rfr: [Reg<u32, _RFR>; 2]

0x0c - receive FIFO 0 register

ier: Reg<u32, _IER>

0x14 - interrupt enable register

esr: Reg<u32, _ESR>

0x18 - error status register

btr: Reg<u32, _BTR>

0x1c - bit timing register

tx: [TX; 3]

0x180 - CAN Transmit cluster

rx: [RX; 2]

0x1b0 - CAN Receive cluster

fmr: Reg<u32, _FMR>

0x200 - filter master register

fm1r: Reg<u32, _FM1R>

0x204 - filter mode register

fs1r: Reg<u32, _FS1R>

0x20c - filter scale register

ffa1r: Reg<u32, _FFA1R>

0x214 - filter FIFO assignment register

fa1r: Reg<u32, _FA1R>

0x21c - CAN filter activation register

fb: [FB; 28]

0x240 - CAN Filter Bank cluster

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