Expand description
Controller area network
Modules§
- btr
- bit timing register
- esr
- error status register
- f0r1
- Filter bank 0 register 1
- f0r2
- Filter bank 0 register 2
- f1r1
- Filter bank 1 register 1
- f1r2
- Filter bank 1 register 2
- f2r1
- Filter bank 2 register 1
- f2r2
- Filter bank 2 register 2
- f3r1
- Filter bank 3 register 1
- f3r2
- Filter bank 3 register 2
- f4r1
- Filter bank 4 register 1
- f4r2
- Filter bank 4 register 2
- f5r1
- Filter bank 5 register 1
- f5r2
- Filter bank 5 register 2
- f6r1
- Filter bank 6 register 1
- f6r2
- Filter bank 6 register 2
- f7r1
- Filter bank 7 register 1
- f7r2
- Filter bank 7 register 2
- f8r1
- Filter bank 8 register 1
- f8r2
- Filter bank 8 register 2
- f9r1
- Filter bank 9 register 1
- f9r2
- Filter bank 9 register 2
- f10r1
- Filter bank 10 register 1
- f10r2
- Filter bank 10 register 2
- f11r1
- Filter bank 11 register 1
- f11r2
- Filter bank 11 register 2
- f12r1
- Filter bank 4 register 1
- f12r2
- Filter bank 12 register 2
- f13r1
- Filter bank 13 register 1
- f13r2
- Filter bank 13 register 2
- f14r1
- Filter bank 14 register 1
- f14r2
- Filter bank 14 register 2
- f15r1
- Filter bank 15 register 1
- f15r2
- Filter bank 15 register 2
- f16r1
- Filter bank 16 register 1
- f16r2
- Filter bank 16 register 2
- f17r1
- Filter bank 17 register 1
- f17r2
- Filter bank 17 register 2
- f18r1
- Filter bank 18 register 1
- f18r2
- Filter bank 18 register 2
- f19r1
- Filter bank 19 register 1
- f19r2
- Filter bank 19 register 2
- f20r1
- Filter bank 20 register 1
- f20r2
- Filter bank 20 register 2
- f21r1
- Filter bank 21 register 1
- f21r2
- Filter bank 21 register 2
- f22r1
- Filter bank 22 register 1
- f22r2
- Filter bank 22 register 2
- f23r1
- Filter bank 23 register 1
- f23r2
- Filter bank 23 register 2
- f24r1
- Filter bank 24 register 1
- f24r2
- Filter bank 24 register 2
- f25r1
- Filter bank 25 register 1
- f25r2
- Filter bank 25 register 2
- f26r1
- Filter bank 26 register 1
- f26r2
- Filter bank 26 register 2
- f27r1
- Filter bank 27 register 1
- f27r2
- Filter bank 27 register 2
- fa1r
- CAN filter activation register
- ffa1r
- filter FIFO assignment register
- fm1r
- filter mode register
- fmr
- filter master register
- fs1r
- filter scale register
- ier
- interrupt enable register
- mcr
- master control register
- msr
- master status register
- rdh0r
- receive FIFO mailbox data high register
- rdh1r
- receive FIFO mailbox data high register
- rdl0r
- receive FIFO mailbox data low register
- rdl1r
- receive FIFO mailbox data low register
- rdt0r
- receive FIFO mailbox data length control and time stamp register
- rdt1r
- receive FIFO mailbox data length control and time stamp register
- rf0r
- receive FIFO 0 register
- rf1r
- receive FIFO 1 register
- ri0r
- receive FIFO mailbox identifier register
- ri1r
- receive FIFO mailbox identifier register
- tdh0r
- mailbox data high register
- tdh1r
- mailbox data high register
- tdh2r
- mailbox data high register
- tdl0r
- mailbox data low register
- tdl1r
- mailbox data low register
- tdl2r
- mailbox data low register
- tdt0r
- mailbox data length control and time stamp register
- tdt1r
- mailbox data length control and time stamp register
- tdt2r
- mailbox data length control and time stamp register
- ti0r
- TX mailbox identifier register
- ti1r
- TX mailbox identifier register
- ti2r
- TX mailbox identifier register
- tsr
- transmit status register
Structs§
- BTR
- bit timing register
- ESR
- error status register
- F0R1
- Filter bank 0 register 1
- F0R2
- Filter bank 0 register 2
- F1R1
- Filter bank 1 register 1
- F1R2
- Filter bank 1 register 2
- F2R1
- Filter bank 2 register 1
- F2R2
- Filter bank 2 register 2
- F3R1
- Filter bank 3 register 1
- F3R2
- Filter bank 3 register 2
- F4R1
- Filter bank 4 register 1
- F4R2
- Filter bank 4 register 2
- F5R1
- Filter bank 5 register 1
- F5R2
- Filter bank 5 register 2
- F6R1
- Filter bank 6 register 1
- F6R2
- Filter bank 6 register 2
- F7R1
- Filter bank 7 register 1
- F7R2
- Filter bank 7 register 2
- F8R1
- Filter bank 8 register 1
- F8R2
- Filter bank 8 register 2
- F9R1
- Filter bank 9 register 1
- F9R2
- Filter bank 9 register 2
- F10R1
- Filter bank 10 register 1
- F10R2
- Filter bank 10 register 2
- F11R1
- Filter bank 11 register 1
- F11R2
- Filter bank 11 register 2
- F12R1
- Filter bank 4 register 1
- F12R2
- Filter bank 12 register 2
- F13R1
- Filter bank 13 register 1
- F13R2
- Filter bank 13 register 2
- F14R1
- Filter bank 14 register 1
- F14R2
- Filter bank 14 register 2
- F15R1
- Filter bank 15 register 1
- F15R2
- Filter bank 15 register 2
- F16R1
- Filter bank 16 register 1
- F16R2
- Filter bank 16 register 2
- F17R1
- Filter bank 17 register 1
- F17R2
- Filter bank 17 register 2
- F18R1
- Filter bank 18 register 1
- F18R2
- Filter bank 18 register 2
- F19R1
- Filter bank 19 register 1
- F19R2
- Filter bank 19 register 2
- F20R1
- Filter bank 20 register 1
- F20R2
- Filter bank 20 register 2
- F21R1
- Filter bank 21 register 1
- F21R2
- Filter bank 21 register 2
- F22R1
- Filter bank 22 register 1
- F22R2
- Filter bank 22 register 2
- F23R1
- Filter bank 23 register 1
- F23R2
- Filter bank 23 register 2
- F24R1
- Filter bank 24 register 1
- F24R2
- Filter bank 24 register 2
- F25R1
- Filter bank 25 register 1
- F25R2
- Filter bank 25 register 2
- F26R1
- Filter bank 26 register 1
- F26R2
- Filter bank 26 register 2
- F27R1
- Filter bank 27 register 1
- F27R2
- Filter bank 27 register 2
- FA1R
- CAN filter activation register
- FFA1R
- filter FIFO assignment register
- FM1R
- filter mode register
- FMR
- filter master register
- FS1R
- filter scale register
- IER
- interrupt enable register
- MCR
- master control register
- MSR
- master status register
- RDH0R
- receive FIFO mailbox data high register
- RDH1R
- receive FIFO mailbox data high register
- RDL0R
- receive FIFO mailbox data low register
- RDL1R
- receive FIFO mailbox data low register
- RDT0R
- receive FIFO mailbox data length control and time stamp register
- RDT1R
- receive FIFO mailbox data length control and time stamp register
- RF0R
- receive FIFO 0 register
- RF1R
- receive FIFO 1 register
- RI0R
- receive FIFO mailbox identifier register
- RI1R
- receive FIFO mailbox identifier register
- Register
Block - Register block
- TDH0R
- mailbox data high register
- TDH1R
- mailbox data high register
- TDH2R
- mailbox data high register
- TDL0R
- mailbox data low register
- TDL1R
- mailbox data low register
- TDL2R
- mailbox data low register
- TDT0R
- mailbox data length control and time stamp register
- TDT1R
- mailbox data length control and time stamp register
- TDT2R
- mailbox data length control and time stamp register
- TI0R
- TX mailbox identifier register
- TI1R
- TX mailbox identifier register
- TI2R
- TX mailbox identifier register
- TSR
- transmit status register