Struct stm32f30x::tim8::RegisterBlock
[−]
[src]
#[repr(C)]pub struct RegisterBlock { pub cr1: CR1, pub cr2: CR2, pub smcr: SMCR, pub dier: DIER, pub sr: SR, pub egr: EGR, pub ccmr1_output: CCMR1_OUTPUT, pub ccmr2_output: CCMR2_OUTPUT, pub ccer: CCER, pub cnt: CNT, pub psc: PSC, pub arr: ARR, pub rcr: RCR, pub ccr1: CCR1, pub ccr2: CCR2, pub ccr3: CCR3, pub ccr4: CCR4, pub bdtr: BDTR, pub dcr: DCR, pub dmar: DMAR, pub ccmr3_output: CCMR3_OUTPUT, pub ccr5: CCR5, pub ccr6: CCR6, pub or: OR, // some fields omitted }
Register block
Fields
cr1: CR1
0x00 - control register 1
cr2: CR2
0x04 - control register 2
smcr: SMCR
0x08 - slave mode control register
dier: DIER
0x0c - DMA/Interrupt enable register
sr: SR
0x10 - status register
egr: EGR
0x14 - event generation register
ccmr1_output: CCMR1_OUTPUT
0x18 - capture/compare mode register (output mode)
ccmr2_output: CCMR2_OUTPUT
0x1c - capture/compare mode register (output mode)
ccer: CCER
0x20 - capture/compare enable register
cnt: CNT
0x24 - counter
psc: PSC
0x28 - prescaler
arr: ARR
0x2c - auto-reload register
rcr: RCR
0x30 - repetition counter register
ccr1: CCR1
0x34 - capture/compare register 1
ccr2: CCR2
0x38 - capture/compare register 2
ccr3: CCR3
0x3c - capture/compare register 3
ccr4: CCR4
0x40 - capture/compare register 4
bdtr: BDTR
0x44 - break and dead-time register
dcr: DCR
0x48 - DMA control register
dmar: DMAR
0x4c - DMA address for full transfer
ccmr3_output: CCMR3_OUTPUT
0x54 - capture/compare mode register 3 (output mode)
ccr5: CCR5
0x58 - capture/compare register 5
ccr6: CCR6
0x5c - capture/compare register 6
or: OR
0x60 - option registers