stm32f30x_memory_map/
dbgmcu.rs

1# [ doc = "Debug support" ]
2# [ repr ( C ) ]
3pub struct Dbgmcu {
4    # [ doc = "0x00 - MCU Device ID Code Register" ]
5    pub idcode: Idcode,
6    # [ doc = "0x04 - Debug MCU Configuration Register" ]
7    pub cr: Cr,
8    # [ doc = "0x08 - APB Low Freeze Register" ]
9    pub apb1fz: Apb1fz,
10    # [ doc = "0x0c - APB High Freeze Register" ]
11    pub apb2fz: Apb2fz,
12}
13
14# [ repr ( C ) ]
15pub struct Idcode {
16    register: ::volatile_register::RO<u32>,
17}
18
19impl Idcode {
20    pub fn read_bits(&self) -> u32 {
21        self.register.read()
22    }
23    pub fn read(&self) -> IdcodeR {
24        IdcodeR { bits: self.register.read() }
25    }
26}
27
28# [ derive ( Clone , Copy ) ]
29# [ repr ( C ) ]
30pub struct IdcodeR {
31    bits: u32,
32}
33
34impl IdcodeR {
35    # [ doc = "Bits 0:11 - Device Identifier" ]
36    pub fn dev_id(&self) -> u16 {
37        const MASK: u32 = 4095;
38        const OFFSET: u8 = 0u8;
39        ((self.bits >> OFFSET) & MASK) as u16
40    }
41    # [ doc = "Bits 16:31 - Revision Identifier" ]
42    pub fn rev_id(&self) -> u16 {
43        const MASK: u32 = 65535;
44        const OFFSET: u8 = 16u8;
45        ((self.bits >> OFFSET) & MASK) as u16
46    }
47}
48
49# [ repr ( C ) ]
50pub struct Cr {
51    register: ::volatile_register::RW<u32>,
52}
53
54impl Cr {
55    pub fn read_bits(&self) -> u32 {
56        self.register.read()
57    }
58    pub unsafe fn modify_bits<F>(&mut self, f: F)
59        where F: FnOnce(&mut u32)
60    {
61        let mut bits = self.register.read();
62        f(&mut bits);
63        self.register.write(bits);
64    }
65    pub unsafe fn write_bits(&mut self, bits: u32) {
66        self.register.write(bits);
67    }
68    pub fn modify<F>(&mut self, f: F)
69        where for<'w> F: FnOnce(&CrR, &'w mut CrW) -> &'w mut CrW
70    {
71        let bits = self.register.read();
72        let r = CrR { bits: bits };
73        let mut w = CrW { bits: bits };
74        f(&r, &mut w);
75        self.register.write(w.bits);
76    }
77    pub fn read(&self) -> CrR {
78        CrR { bits: self.register.read() }
79    }
80    pub fn write<F>(&mut self, f: F)
81        where F: FnOnce(&mut CrW) -> &mut CrW
82    {
83        let mut w = CrW::reset_value();
84        f(&mut w);
85        self.register.write(w.bits);
86    }
87}
88
89# [ derive ( Clone , Copy ) ]
90# [ repr ( C ) ]
91pub struct CrR {
92    bits: u32,
93}
94
95impl CrR {
96    # [ doc = "Bit 0 - Debug Sleep mode" ]
97    pub fn dbg_sleep(&self) -> bool {
98        const OFFSET: u8 = 0u8;
99        self.bits & (1 << OFFSET) != 0
100    }
101    # [ doc = "Bit 1 - Debug Stop Mode" ]
102    pub fn dbg_stop(&self) -> bool {
103        const OFFSET: u8 = 1u8;
104        self.bits & (1 << OFFSET) != 0
105    }
106    # [ doc = "Bit 2 - Debug Standby Mode" ]
107    pub fn dbg_standby(&self) -> bool {
108        const OFFSET: u8 = 2u8;
109        self.bits & (1 << OFFSET) != 0
110    }
111    # [ doc = "Bit 5 - Trace pin assignment control" ]
112    pub fn trace_ioen(&self) -> bool {
113        const OFFSET: u8 = 5u8;
114        self.bits & (1 << OFFSET) != 0
115    }
116    # [ doc = "Bits 6:7 - Trace pin assignment control" ]
117    pub fn trace_mode(&self) -> u8 {
118        const MASK: u32 = 3;
119        const OFFSET: u8 = 6u8;
120        ((self.bits >> OFFSET) & MASK) as u8
121    }
122}
123
124# [ derive ( Clone , Copy ) ]
125# [ repr ( C ) ]
126pub struct CrW {
127    bits: u32,
128}
129
130impl CrW {
131    # [ doc = r" Reset value" ]
132    pub fn reset_value() -> Self {
133        CrW { bits: 0 }
134    }
135    # [ doc = "Bit 0 - Debug Sleep mode" ]
136    pub fn dbg_sleep(&mut self, value: bool) -> &mut Self {
137        const OFFSET: u8 = 0u8;
138        if value {
139            self.bits |= 1 << OFFSET;
140        } else {
141            self.bits &= !(1 << OFFSET);
142        }
143        self
144    }
145    # [ doc = "Bit 1 - Debug Stop Mode" ]
146    pub fn dbg_stop(&mut self, value: bool) -> &mut Self {
147        const OFFSET: u8 = 1u8;
148        if value {
149            self.bits |= 1 << OFFSET;
150        } else {
151            self.bits &= !(1 << OFFSET);
152        }
153        self
154    }
155    # [ doc = "Bit 2 - Debug Standby Mode" ]
156    pub fn dbg_standby(&mut self, value: bool) -> &mut Self {
157        const OFFSET: u8 = 2u8;
158        if value {
159            self.bits |= 1 << OFFSET;
160        } else {
161            self.bits &= !(1 << OFFSET);
162        }
163        self
164    }
165    # [ doc = "Bit 5 - Trace pin assignment control" ]
166    pub fn trace_ioen(&mut self, value: bool) -> &mut Self {
167        const OFFSET: u8 = 5u8;
168        if value {
169            self.bits |= 1 << OFFSET;
170        } else {
171            self.bits &= !(1 << OFFSET);
172        }
173        self
174    }
175    # [ doc = "Bits 6:7 - Trace pin assignment control" ]
176    pub fn trace_mode(&mut self, value: u8) -> &mut Self {
177        const OFFSET: u8 = 6u8;
178        const MASK: u8 = 3;
179        self.bits &= !((MASK as u32) << OFFSET);
180        self.bits |= ((value & MASK) as u32) << OFFSET;
181        self
182    }
183}
184
185# [ repr ( C ) ]
186pub struct Apb1fz {
187    register: ::volatile_register::RW<u32>,
188}
189
190impl Apb1fz {
191    pub fn read_bits(&self) -> u32 {
192        self.register.read()
193    }
194    pub unsafe fn modify_bits<F>(&mut self, f: F)
195        where F: FnOnce(&mut u32)
196    {
197        let mut bits = self.register.read();
198        f(&mut bits);
199        self.register.write(bits);
200    }
201    pub unsafe fn write_bits(&mut self, bits: u32) {
202        self.register.write(bits);
203    }
204    pub fn modify<F>(&mut self, f: F)
205        where for<'w> F: FnOnce(&Apb1fzR, &'w mut Apb1fzW) -> &'w mut Apb1fzW
206    {
207        let bits = self.register.read();
208        let r = Apb1fzR { bits: bits };
209        let mut w = Apb1fzW { bits: bits };
210        f(&r, &mut w);
211        self.register.write(w.bits);
212    }
213    pub fn read(&self) -> Apb1fzR {
214        Apb1fzR { bits: self.register.read() }
215    }
216    pub fn write<F>(&mut self, f: F)
217        where F: FnOnce(&mut Apb1fzW) -> &mut Apb1fzW
218    {
219        let mut w = Apb1fzW::reset_value();
220        f(&mut w);
221        self.register.write(w.bits);
222    }
223}
224
225# [ derive ( Clone , Copy ) ]
226# [ repr ( C ) ]
227pub struct Apb1fzR {
228    bits: u32,
229}
230
231impl Apb1fzR {
232    # [ doc = "Bit 0 - Debug Timer 2 stopped when Core is halted" ]
233    pub fn dbg_tim2_stop(&self) -> bool {
234        const OFFSET: u8 = 0u8;
235        self.bits & (1 << OFFSET) != 0
236    }
237    # [ doc = "Bit 1 - Debug Timer 3 stopped when Core is halted" ]
238    pub fn dbg_tim3_stop(&self) -> bool {
239        const OFFSET: u8 = 1u8;
240        self.bits & (1 << OFFSET) != 0
241    }
242    # [ doc = "Bit 2 - Debug Timer 4 stopped when Core is halted" ]
243    pub fn dbg_tim4_stop(&self) -> bool {
244        const OFFSET: u8 = 2u8;
245        self.bits & (1 << OFFSET) != 0
246    }
247    # [ doc = "Bit 3 - Debug Timer 5 stopped when Core is halted" ]
248    pub fn dbg_tim5_stop(&self) -> bool {
249        const OFFSET: u8 = 3u8;
250        self.bits & (1 << OFFSET) != 0
251    }
252    # [ doc = "Bit 4 - Debug Timer 6 stopped when Core is halted" ]
253    pub fn dbg_tim6_stop(&self) -> bool {
254        const OFFSET: u8 = 4u8;
255        self.bits & (1 << OFFSET) != 0
256    }
257    # [ doc = "Bit 5 - Debug Timer 7 stopped when Core is halted" ]
258    pub fn dbg_tim7_stop(&self) -> bool {
259        const OFFSET: u8 = 5u8;
260        self.bits & (1 << OFFSET) != 0
261    }
262    # [ doc = "Bit 6 - Debug Timer 12 stopped when Core is halted" ]
263    pub fn dbg_tim12_stop(&self) -> bool {
264        const OFFSET: u8 = 6u8;
265        self.bits & (1 << OFFSET) != 0
266    }
267    # [ doc = "Bit 7 - Debug Timer 13 stopped when Core is halted" ]
268    pub fn dbg_tim13_stop(&self) -> bool {
269        const OFFSET: u8 = 7u8;
270        self.bits & (1 << OFFSET) != 0
271    }
272    # [ doc = "Bit 8 - Debug Timer 14 stopped when Core is halted" ]
273    pub fn dbg_timer14_stop(&self) -> bool {
274        const OFFSET: u8 = 8u8;
275        self.bits & (1 << OFFSET) != 0
276    }
277    # [ doc = "Bit 9 - Debug Timer 18 stopped when Core is halted" ]
278    pub fn dbg_tim18_stop(&self) -> bool {
279        const OFFSET: u8 = 9u8;
280        self.bits & (1 << OFFSET) != 0
281    }
282    # [ doc = "Bit 10 - Debug RTC stopped when Core is halted" ]
283    pub fn dbg_rtc_stop(&self) -> bool {
284        const OFFSET: u8 = 10u8;
285        self.bits & (1 << OFFSET) != 0
286    }
287    # [ doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted" ]
288    pub fn dbg_wwdg_stop(&self) -> bool {
289        const OFFSET: u8 = 11u8;
290        self.bits & (1 << OFFSET) != 0
291    }
292    # [ doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted" ]
293    pub fn dbg_iwdg_stop(&self) -> bool {
294        const OFFSET: u8 = 12u8;
295        self.bits & (1 << OFFSET) != 0
296    }
297    # [ doc = "Bit 21 - SMBUS timeout mode stopped when Core is halted" ]
298    pub fn i2c1_smbus_timeout(&self) -> bool {
299        const OFFSET: u8 = 21u8;
300        self.bits & (1 << OFFSET) != 0
301    }
302    # [ doc = "Bit 22 - SMBUS timeout mode stopped when Core is halted" ]
303    pub fn i2c2_smbus_timeout(&self) -> bool {
304        const OFFSET: u8 = 22u8;
305        self.bits & (1 << OFFSET) != 0
306    }
307    # [ doc = "Bit 25 - Debug CAN stopped when core is halted" ]
308    pub fn dbg_can_stop(&self) -> bool {
309        const OFFSET: u8 = 25u8;
310        self.bits & (1 << OFFSET) != 0
311    }
312}
313
314# [ derive ( Clone , Copy ) ]
315# [ repr ( C ) ]
316pub struct Apb1fzW {
317    bits: u32,
318}
319
320impl Apb1fzW {
321    # [ doc = r" Reset value" ]
322    pub fn reset_value() -> Self {
323        Apb1fzW { bits: 0 }
324    }
325    # [ doc = "Bit 0 - Debug Timer 2 stopped when Core is halted" ]
326    pub fn dbg_tim2_stop(&mut self, value: bool) -> &mut Self {
327        const OFFSET: u8 = 0u8;
328        if value {
329            self.bits |= 1 << OFFSET;
330        } else {
331            self.bits &= !(1 << OFFSET);
332        }
333        self
334    }
335    # [ doc = "Bit 1 - Debug Timer 3 stopped when Core is halted" ]
336    pub fn dbg_tim3_stop(&mut self, value: bool) -> &mut Self {
337        const OFFSET: u8 = 1u8;
338        if value {
339            self.bits |= 1 << OFFSET;
340        } else {
341            self.bits &= !(1 << OFFSET);
342        }
343        self
344    }
345    # [ doc = "Bit 2 - Debug Timer 4 stopped when Core is halted" ]
346    pub fn dbg_tim4_stop(&mut self, value: bool) -> &mut Self {
347        const OFFSET: u8 = 2u8;
348        if value {
349            self.bits |= 1 << OFFSET;
350        } else {
351            self.bits &= !(1 << OFFSET);
352        }
353        self
354    }
355    # [ doc = "Bit 3 - Debug Timer 5 stopped when Core is halted" ]
356    pub fn dbg_tim5_stop(&mut self, value: bool) -> &mut Self {
357        const OFFSET: u8 = 3u8;
358        if value {
359            self.bits |= 1 << OFFSET;
360        } else {
361            self.bits &= !(1 << OFFSET);
362        }
363        self
364    }
365    # [ doc = "Bit 4 - Debug Timer 6 stopped when Core is halted" ]
366    pub fn dbg_tim6_stop(&mut self, value: bool) -> &mut Self {
367        const OFFSET: u8 = 4u8;
368        if value {
369            self.bits |= 1 << OFFSET;
370        } else {
371            self.bits &= !(1 << OFFSET);
372        }
373        self
374    }
375    # [ doc = "Bit 5 - Debug Timer 7 stopped when Core is halted" ]
376    pub fn dbg_tim7_stop(&mut self, value: bool) -> &mut Self {
377        const OFFSET: u8 = 5u8;
378        if value {
379            self.bits |= 1 << OFFSET;
380        } else {
381            self.bits &= !(1 << OFFSET);
382        }
383        self
384    }
385    # [ doc = "Bit 6 - Debug Timer 12 stopped when Core is halted" ]
386    pub fn dbg_tim12_stop(&mut self, value: bool) -> &mut Self {
387        const OFFSET: u8 = 6u8;
388        if value {
389            self.bits |= 1 << OFFSET;
390        } else {
391            self.bits &= !(1 << OFFSET);
392        }
393        self
394    }
395    # [ doc = "Bit 7 - Debug Timer 13 stopped when Core is halted" ]
396    pub fn dbg_tim13_stop(&mut self, value: bool) -> &mut Self {
397        const OFFSET: u8 = 7u8;
398        if value {
399            self.bits |= 1 << OFFSET;
400        } else {
401            self.bits &= !(1 << OFFSET);
402        }
403        self
404    }
405    # [ doc = "Bit 8 - Debug Timer 14 stopped when Core is halted" ]
406    pub fn dbg_timer14_stop(&mut self, value: bool) -> &mut Self {
407        const OFFSET: u8 = 8u8;
408        if value {
409            self.bits |= 1 << OFFSET;
410        } else {
411            self.bits &= !(1 << OFFSET);
412        }
413        self
414    }
415    # [ doc = "Bit 9 - Debug Timer 18 stopped when Core is halted" ]
416    pub fn dbg_tim18_stop(&mut self, value: bool) -> &mut Self {
417        const OFFSET: u8 = 9u8;
418        if value {
419            self.bits |= 1 << OFFSET;
420        } else {
421            self.bits &= !(1 << OFFSET);
422        }
423        self
424    }
425    # [ doc = "Bit 10 - Debug RTC stopped when Core is halted" ]
426    pub fn dbg_rtc_stop(&mut self, value: bool) -> &mut Self {
427        const OFFSET: u8 = 10u8;
428        if value {
429            self.bits |= 1 << OFFSET;
430        } else {
431            self.bits &= !(1 << OFFSET);
432        }
433        self
434    }
435    # [ doc = "Bit 11 - Debug Window Wachdog stopped when Core is halted" ]
436    pub fn dbg_wwdg_stop(&mut self, value: bool) -> &mut Self {
437        const OFFSET: u8 = 11u8;
438        if value {
439            self.bits |= 1 << OFFSET;
440        } else {
441            self.bits &= !(1 << OFFSET);
442        }
443        self
444    }
445    # [ doc = "Bit 12 - Debug Independent Wachdog stopped when Core is halted" ]
446    pub fn dbg_iwdg_stop(&mut self, value: bool) -> &mut Self {
447        const OFFSET: u8 = 12u8;
448        if value {
449            self.bits |= 1 << OFFSET;
450        } else {
451            self.bits &= !(1 << OFFSET);
452        }
453        self
454    }
455    # [ doc = "Bit 21 - SMBUS timeout mode stopped when Core is halted" ]
456    pub fn i2c1_smbus_timeout(&mut self, value: bool) -> &mut Self {
457        const OFFSET: u8 = 21u8;
458        if value {
459            self.bits |= 1 << OFFSET;
460        } else {
461            self.bits &= !(1 << OFFSET);
462        }
463        self
464    }
465    # [ doc = "Bit 22 - SMBUS timeout mode stopped when Core is halted" ]
466    pub fn i2c2_smbus_timeout(&mut self, value: bool) -> &mut Self {
467        const OFFSET: u8 = 22u8;
468        if value {
469            self.bits |= 1 << OFFSET;
470        } else {
471            self.bits &= !(1 << OFFSET);
472        }
473        self
474    }
475    # [ doc = "Bit 25 - Debug CAN stopped when core is halted" ]
476    pub fn dbg_can_stop(&mut self, value: bool) -> &mut Self {
477        const OFFSET: u8 = 25u8;
478        if value {
479            self.bits |= 1 << OFFSET;
480        } else {
481            self.bits &= !(1 << OFFSET);
482        }
483        self
484    }
485}
486
487# [ repr ( C ) ]
488pub struct Apb2fz {
489    register: ::volatile_register::RW<u32>,
490}
491
492impl Apb2fz {
493    pub fn read_bits(&self) -> u32 {
494        self.register.read()
495    }
496    pub unsafe fn modify_bits<F>(&mut self, f: F)
497        where F: FnOnce(&mut u32)
498    {
499        let mut bits = self.register.read();
500        f(&mut bits);
501        self.register.write(bits);
502    }
503    pub unsafe fn write_bits(&mut self, bits: u32) {
504        self.register.write(bits);
505    }
506    pub fn modify<F>(&mut self, f: F)
507        where for<'w> F: FnOnce(&Apb2fzR, &'w mut Apb2fzW) -> &'w mut Apb2fzW
508    {
509        let bits = self.register.read();
510        let r = Apb2fzR { bits: bits };
511        let mut w = Apb2fzW { bits: bits };
512        f(&r, &mut w);
513        self.register.write(w.bits);
514    }
515    pub fn read(&self) -> Apb2fzR {
516        Apb2fzR { bits: self.register.read() }
517    }
518    pub fn write<F>(&mut self, f: F)
519        where F: FnOnce(&mut Apb2fzW) -> &mut Apb2fzW
520    {
521        let mut w = Apb2fzW::reset_value();
522        f(&mut w);
523        self.register.write(w.bits);
524    }
525}
526
527# [ derive ( Clone , Copy ) ]
528# [ repr ( C ) ]
529pub struct Apb2fzR {
530    bits: u32,
531}
532
533impl Apb2fzR {
534    # [ doc = "Bit 2 - Debug Timer 15 stopped when Core is halted" ]
535    pub fn dbg_tim15_stop(&self) -> bool {
536        const OFFSET: u8 = 2u8;
537        self.bits & (1 << OFFSET) != 0
538    }
539    # [ doc = "Bit 3 - Debug Timer 16 stopped when Core is halted" ]
540    pub fn dbg_tim16_stop(&self) -> bool {
541        const OFFSET: u8 = 3u8;
542        self.bits & (1 << OFFSET) != 0
543    }
544    # [ doc = "Bit 4 - Debug Timer 17 stopped when Core is halted" ]
545    pub fn dbg_tim17_sto(&self) -> bool {
546        const OFFSET: u8 = 4u8;
547        self.bits & (1 << OFFSET) != 0
548    }
549    # [ doc = "Bit 5 - Debug Timer 19 stopped when Core is halted" ]
550    pub fn dbg_tim19_stop(&self) -> bool {
551        const OFFSET: u8 = 5u8;
552        self.bits & (1 << OFFSET) != 0
553    }
554}
555
556# [ derive ( Clone , Copy ) ]
557# [ repr ( C ) ]
558pub struct Apb2fzW {
559    bits: u32,
560}
561
562impl Apb2fzW {
563    # [ doc = r" Reset value" ]
564    pub fn reset_value() -> Self {
565        Apb2fzW { bits: 0 }
566    }
567    # [ doc = "Bit 2 - Debug Timer 15 stopped when Core is halted" ]
568    pub fn dbg_tim15_stop(&mut self, value: bool) -> &mut Self {
569        const OFFSET: u8 = 2u8;
570        if value {
571            self.bits |= 1 << OFFSET;
572        } else {
573            self.bits &= !(1 << OFFSET);
574        }
575        self
576    }
577    # [ doc = "Bit 3 - Debug Timer 16 stopped when Core is halted" ]
578    pub fn dbg_tim16_stop(&mut self, value: bool) -> &mut Self {
579        const OFFSET: u8 = 3u8;
580        if value {
581            self.bits |= 1 << OFFSET;
582        } else {
583            self.bits &= !(1 << OFFSET);
584        }
585        self
586    }
587    # [ doc = "Bit 4 - Debug Timer 17 stopped when Core is halted" ]
588    pub fn dbg_tim17_sto(&mut self, value: bool) -> &mut Self {
589        const OFFSET: u8 = 4u8;
590        if value {
591            self.bits |= 1 << OFFSET;
592        } else {
593            self.bits &= !(1 << OFFSET);
594        }
595        self
596    }
597    # [ doc = "Bit 5 - Debug Timer 19 stopped when Core is halted" ]
598    pub fn dbg_tim19_stop(&mut self, value: bool) -> &mut Self {
599        const OFFSET: u8 = 5u8;
600        if value {
601            self.bits |= 1 << OFFSET;
602        } else {
603            self.bits &= !(1 << OFFSET);
604        }
605        self
606    }
607}
stm32f30x_memory_map/dbgmcu.rs

stm32f30x_memory_map/
dbgmcu.rs
