1# [ doc = "Serial peripheral interface/Inter-IC sound" ]
2# [ repr ( C ) ]
3pub struct Spi {
4 # [ doc = "0x00 - control register 1" ]
5 pub cr1: Cr1,
6 # [ doc = "0x04 - control register 2" ]
7 pub cr2: Cr2,
8 # [ doc = "0x08 - status register" ]
9 pub sr: Sr,
10 # [ doc = "0x0c - data register" ]
11 pub dr: Dr,
12 # [ doc = "0x10 - CRC polynomial register" ]
13 pub crcpr: Crcpr,
14 # [ doc = "0x14 - RX CRC register" ]
15 pub rxcrcr: Rxcrcr,
16 # [ doc = "0x18 - TX CRC register" ]
17 pub txcrcr: Txcrcr,
18 # [ doc = "0x1c - I2S configuration register" ]
19 pub i2scfgr: I2scfgr,
20 # [ doc = "0x20 - I2S prescaler register" ]
21 pub i2spr: I2spr,
22}
23
24# [ repr ( C ) ]
25pub struct Cr1 {
26 register: ::volatile_register::RW<u32>,
27}
28
29impl Cr1 {
30 pub fn read_bits(&self) -> u32 {
31 self.register.read()
32 }
33 pub unsafe fn modify_bits<F>(&mut self, f: F)
34 where F: FnOnce(&mut u32)
35 {
36 let mut bits = self.register.read();
37 f(&mut bits);
38 self.register.write(bits);
39 }
40 pub unsafe fn write_bits(&mut self, bits: u32) {
41 self.register.write(bits);
42 }
43 pub fn modify<F>(&mut self, f: F)
44 where for<'w> F: FnOnce(&Cr1R, &'w mut Cr1W) -> &'w mut Cr1W
45 {
46 let bits = self.register.read();
47 let r = Cr1R { bits: bits };
48 let mut w = Cr1W { bits: bits };
49 f(&r, &mut w);
50 self.register.write(w.bits);
51 }
52 pub fn read(&self) -> Cr1R {
53 Cr1R { bits: self.register.read() }
54 }
55 pub fn write<F>(&mut self, f: F)
56 where F: FnOnce(&mut Cr1W) -> &mut Cr1W
57 {
58 let mut w = Cr1W::reset_value();
59 f(&mut w);
60 self.register.write(w.bits);
61 }
62}
63
64# [ derive ( Clone , Copy ) ]
65# [ repr ( C ) ]
66pub struct Cr1R {
67 bits: u32,
68}
69
70impl Cr1R {
71 # [ doc = "Bit 15 - Bidirectional data mode enable" ]
72 pub fn bidimode(&self) -> bool {
73 const OFFSET: u8 = 15u8;
74 self.bits & (1 << OFFSET) != 0
75 }
76 # [ doc = "Bit 14 - Output enable in bidirectional mode" ]
77 pub fn bidioe(&self) -> bool {
78 const OFFSET: u8 = 14u8;
79 self.bits & (1 << OFFSET) != 0
80 }
81 # [ doc = "Bit 13 - Hardware CRC calculation enable" ]
82 pub fn crcen(&self) -> bool {
83 const OFFSET: u8 = 13u8;
84 self.bits & (1 << OFFSET) != 0
85 }
86 # [ doc = "Bit 12 - CRC transfer next" ]
87 pub fn crcnext(&self) -> bool {
88 const OFFSET: u8 = 12u8;
89 self.bits & (1 << OFFSET) != 0
90 }
91 # [ doc = "Bit 11 - Data frame format" ]
92 pub fn dff(&self) -> bool {
93 const OFFSET: u8 = 11u8;
94 self.bits & (1 << OFFSET) != 0
95 }
96 # [ doc = "Bit 10 - Receive only" ]
97 pub fn rxonly(&self) -> bool {
98 const OFFSET: u8 = 10u8;
99 self.bits & (1 << OFFSET) != 0
100 }
101 # [ doc = "Bit 9 - Software slave management" ]
102 pub fn ssm(&self) -> bool {
103 const OFFSET: u8 = 9u8;
104 self.bits & (1 << OFFSET) != 0
105 }
106 # [ doc = "Bit 8 - Internal slave select" ]
107 pub fn ssi(&self) -> bool {
108 const OFFSET: u8 = 8u8;
109 self.bits & (1 << OFFSET) != 0
110 }
111 # [ doc = "Bit 7 - Frame format" ]
112 pub fn lsbfirst(&self) -> bool {
113 const OFFSET: u8 = 7u8;
114 self.bits & (1 << OFFSET) != 0
115 }
116 # [ doc = "Bit 6 - SPI enable" ]
117 pub fn spe(&self) -> bool {
118 const OFFSET: u8 = 6u8;
119 self.bits & (1 << OFFSET) != 0
120 }
121 # [ doc = "Bits 3:5 - Baud rate control" ]
122 pub fn br(&self) -> u8 {
123 const MASK: u32 = 7;
124 const OFFSET: u8 = 3u8;
125 ((self.bits >> OFFSET) & MASK) as u8
126 }
127 # [ doc = "Bit 2 - Master selection" ]
128 pub fn mstr(&self) -> bool {
129 const OFFSET: u8 = 2u8;
130 self.bits & (1 << OFFSET) != 0
131 }
132 # [ doc = "Bit 1 - Clock polarity" ]
133 pub fn cpol(&self) -> bool {
134 const OFFSET: u8 = 1u8;
135 self.bits & (1 << OFFSET) != 0
136 }
137 # [ doc = "Bit 0 - Clock phase" ]
138 pub fn cpha(&self) -> bool {
139 const OFFSET: u8 = 0u8;
140 self.bits & (1 << OFFSET) != 0
141 }
142}
143
144# [ derive ( Clone , Copy ) ]
145# [ repr ( C ) ]
146pub struct Cr1W {
147 bits: u32,
148}
149
150impl Cr1W {
151 # [ doc = r" Reset value" ]
152 pub fn reset_value() -> Self {
153 Cr1W { bits: 0 }
154 }
155 # [ doc = "Bit 15 - Bidirectional data mode enable" ]
156 pub fn bidimode(&mut self, value: bool) -> &mut Self {
157 const OFFSET: u8 = 15u8;
158 if value {
159 self.bits |= 1 << OFFSET;
160 } else {
161 self.bits &= !(1 << OFFSET);
162 }
163 self
164 }
165 # [ doc = "Bit 14 - Output enable in bidirectional mode" ]
166 pub fn bidioe(&mut self, value: bool) -> &mut Self {
167 const OFFSET: u8 = 14u8;
168 if value {
169 self.bits |= 1 << OFFSET;
170 } else {
171 self.bits &= !(1 << OFFSET);
172 }
173 self
174 }
175 # [ doc = "Bit 13 - Hardware CRC calculation enable" ]
176 pub fn crcen(&mut self, value: bool) -> &mut Self {
177 const OFFSET: u8 = 13u8;
178 if value {
179 self.bits |= 1 << OFFSET;
180 } else {
181 self.bits &= !(1 << OFFSET);
182 }
183 self
184 }
185 # [ doc = "Bit 12 - CRC transfer next" ]
186 pub fn crcnext(&mut self, value: bool) -> &mut Self {
187 const OFFSET: u8 = 12u8;
188 if value {
189 self.bits |= 1 << OFFSET;
190 } else {
191 self.bits &= !(1 << OFFSET);
192 }
193 self
194 }
195 # [ doc = "Bit 11 - Data frame format" ]
196 pub fn dff(&mut self, value: bool) -> &mut Self {
197 const OFFSET: u8 = 11u8;
198 if value {
199 self.bits |= 1 << OFFSET;
200 } else {
201 self.bits &= !(1 << OFFSET);
202 }
203 self
204 }
205 # [ doc = "Bit 10 - Receive only" ]
206 pub fn rxonly(&mut self, value: bool) -> &mut Self {
207 const OFFSET: u8 = 10u8;
208 if value {
209 self.bits |= 1 << OFFSET;
210 } else {
211 self.bits &= !(1 << OFFSET);
212 }
213 self
214 }
215 # [ doc = "Bit 9 - Software slave management" ]
216 pub fn ssm(&mut self, value: bool) -> &mut Self {
217 const OFFSET: u8 = 9u8;
218 if value {
219 self.bits |= 1 << OFFSET;
220 } else {
221 self.bits &= !(1 << OFFSET);
222 }
223 self
224 }
225 # [ doc = "Bit 8 - Internal slave select" ]
226 pub fn ssi(&mut self, value: bool) -> &mut Self {
227 const OFFSET: u8 = 8u8;
228 if value {
229 self.bits |= 1 << OFFSET;
230 } else {
231 self.bits &= !(1 << OFFSET);
232 }
233 self
234 }
235 # [ doc = "Bit 7 - Frame format" ]
236 pub fn lsbfirst(&mut self, value: bool) -> &mut Self {
237 const OFFSET: u8 = 7u8;
238 if value {
239 self.bits |= 1 << OFFSET;
240 } else {
241 self.bits &= !(1 << OFFSET);
242 }
243 self
244 }
245 # [ doc = "Bit 6 - SPI enable" ]
246 pub fn spe(&mut self, value: bool) -> &mut Self {
247 const OFFSET: u8 = 6u8;
248 if value {
249 self.bits |= 1 << OFFSET;
250 } else {
251 self.bits &= !(1 << OFFSET);
252 }
253 self
254 }
255 # [ doc = "Bits 3:5 - Baud rate control" ]
256 pub fn br(&mut self, value: u8) -> &mut Self {
257 const OFFSET: u8 = 3u8;
258 const MASK: u8 = 7;
259 self.bits &= !((MASK as u32) << OFFSET);
260 self.bits |= ((value & MASK) as u32) << OFFSET;
261 self
262 }
263 # [ doc = "Bit 2 - Master selection" ]
264 pub fn mstr(&mut self, value: bool) -> &mut Self {
265 const OFFSET: u8 = 2u8;
266 if value {
267 self.bits |= 1 << OFFSET;
268 } else {
269 self.bits &= !(1 << OFFSET);
270 }
271 self
272 }
273 # [ doc = "Bit 1 - Clock polarity" ]
274 pub fn cpol(&mut self, value: bool) -> &mut Self {
275 const OFFSET: u8 = 1u8;
276 if value {
277 self.bits |= 1 << OFFSET;
278 } else {
279 self.bits &= !(1 << OFFSET);
280 }
281 self
282 }
283 # [ doc = "Bit 0 - Clock phase" ]
284 pub fn cpha(&mut self, value: bool) -> &mut Self {
285 const OFFSET: u8 = 0u8;
286 if value {
287 self.bits |= 1 << OFFSET;
288 } else {
289 self.bits &= !(1 << OFFSET);
290 }
291 self
292 }
293}
294
295# [ repr ( C ) ]
296pub struct Cr2 {
297 register: ::volatile_register::RW<u32>,
298}
299
300impl Cr2 {
301 pub fn read_bits(&self) -> u32 {
302 self.register.read()
303 }
304 pub unsafe fn modify_bits<F>(&mut self, f: F)
305 where F: FnOnce(&mut u32)
306 {
307 let mut bits = self.register.read();
308 f(&mut bits);
309 self.register.write(bits);
310 }
311 pub unsafe fn write_bits(&mut self, bits: u32) {
312 self.register.write(bits);
313 }
314 pub fn modify<F>(&mut self, f: F)
315 where for<'w> F: FnOnce(&Cr2R, &'w mut Cr2W) -> &'w mut Cr2W
316 {
317 let bits = self.register.read();
318 let r = Cr2R { bits: bits };
319 let mut w = Cr2W { bits: bits };
320 f(&r, &mut w);
321 self.register.write(w.bits);
322 }
323 pub fn read(&self) -> Cr2R {
324 Cr2R { bits: self.register.read() }
325 }
326 pub fn write<F>(&mut self, f: F)
327 where F: FnOnce(&mut Cr2W) -> &mut Cr2W
328 {
329 let mut w = Cr2W::reset_value();
330 f(&mut w);
331 self.register.write(w.bits);
332 }
333}
334
335# [ derive ( Clone , Copy ) ]
336# [ repr ( C ) ]
337pub struct Cr2R {
338 bits: u32,
339}
340
341impl Cr2R {
342 # [ doc = "Bit 0 - Rx buffer DMA enable" ]
343 pub fn rxdmaen(&self) -> bool {
344 const OFFSET: u8 = 0u8;
345 self.bits & (1 << OFFSET) != 0
346 }
347 # [ doc = "Bit 1 - Tx buffer DMA enable" ]
348 pub fn txdmaen(&self) -> bool {
349 const OFFSET: u8 = 1u8;
350 self.bits & (1 << OFFSET) != 0
351 }
352 # [ doc = "Bit 2 - SS output enable" ]
353 pub fn ssoe(&self) -> bool {
354 const OFFSET: u8 = 2u8;
355 self.bits & (1 << OFFSET) != 0
356 }
357 # [ doc = "Bit 3 - NSS pulse management" ]
358 pub fn nssp(&self) -> bool {
359 const OFFSET: u8 = 3u8;
360 self.bits & (1 << OFFSET) != 0
361 }
362 # [ doc = "Bit 4 - Frame format" ]
363 pub fn frf(&self) -> bool {
364 const OFFSET: u8 = 4u8;
365 self.bits & (1 << OFFSET) != 0
366 }
367 # [ doc = "Bit 5 - Error interrupt enable" ]
368 pub fn errie(&self) -> bool {
369 const OFFSET: u8 = 5u8;
370 self.bits & (1 << OFFSET) != 0
371 }
372 # [ doc = "Bit 6 - RX buffer not empty interrupt enable" ]
373 pub fn rxneie(&self) -> bool {
374 const OFFSET: u8 = 6u8;
375 self.bits & (1 << OFFSET) != 0
376 }
377 # [ doc = "Bit 7 - Tx buffer empty interrupt enable" ]
378 pub fn txeie(&self) -> bool {
379 const OFFSET: u8 = 7u8;
380 self.bits & (1 << OFFSET) != 0
381 }
382 # [ doc = "Bits 8:11 - Data size" ]
383 pub fn ds(&self) -> u8 {
384 const MASK: u32 = 15;
385 const OFFSET: u8 = 8u8;
386 ((self.bits >> OFFSET) & MASK) as u8
387 }
388 # [ doc = "Bit 12 - FIFO reception threshold" ]
389 pub fn frxth(&self) -> bool {
390 const OFFSET: u8 = 12u8;
391 self.bits & (1 << OFFSET) != 0
392 }
393 # [ doc = "Bit 13 - Last DMA transfer for reception" ]
394 pub fn ldma_rx(&self) -> bool {
395 const OFFSET: u8 = 13u8;
396 self.bits & (1 << OFFSET) != 0
397 }
398 # [ doc = "Bit 14 - Last DMA transfer for transmission" ]
399 pub fn ldma_tx(&self) -> bool {
400 const OFFSET: u8 = 14u8;
401 self.bits & (1 << OFFSET) != 0
402 }
403}
404
405# [ derive ( Clone , Copy ) ]
406# [ repr ( C ) ]
407pub struct Cr2W {
408 bits: u32,
409}
410
411impl Cr2W {
412 # [ doc = r" Reset value" ]
413 pub fn reset_value() -> Self {
414 Cr2W { bits: 0 }
415 }
416 # [ doc = "Bit 0 - Rx buffer DMA enable" ]
417 pub fn rxdmaen(&mut self, value: bool) -> &mut Self {
418 const OFFSET: u8 = 0u8;
419 if value {
420 self.bits |= 1 << OFFSET;
421 } else {
422 self.bits &= !(1 << OFFSET);
423 }
424 self
425 }
426 # [ doc = "Bit 1 - Tx buffer DMA enable" ]
427 pub fn txdmaen(&mut self, value: bool) -> &mut Self {
428 const OFFSET: u8 = 1u8;
429 if value {
430 self.bits |= 1 << OFFSET;
431 } else {
432 self.bits &= !(1 << OFFSET);
433 }
434 self
435 }
436 # [ doc = "Bit 2 - SS output enable" ]
437 pub fn ssoe(&mut self, value: bool) -> &mut Self {
438 const OFFSET: u8 = 2u8;
439 if value {
440 self.bits |= 1 << OFFSET;
441 } else {
442 self.bits &= !(1 << OFFSET);
443 }
444 self
445 }
446 # [ doc = "Bit 3 - NSS pulse management" ]
447 pub fn nssp(&mut self, value: bool) -> &mut Self {
448 const OFFSET: u8 = 3u8;
449 if value {
450 self.bits |= 1 << OFFSET;
451 } else {
452 self.bits &= !(1 << OFFSET);
453 }
454 self
455 }
456 # [ doc = "Bit 4 - Frame format" ]
457 pub fn frf(&mut self, value: bool) -> &mut Self {
458 const OFFSET: u8 = 4u8;
459 if value {
460 self.bits |= 1 << OFFSET;
461 } else {
462 self.bits &= !(1 << OFFSET);
463 }
464 self
465 }
466 # [ doc = "Bit 5 - Error interrupt enable" ]
467 pub fn errie(&mut self, value: bool) -> &mut Self {
468 const OFFSET: u8 = 5u8;
469 if value {
470 self.bits |= 1 << OFFSET;
471 } else {
472 self.bits &= !(1 << OFFSET);
473 }
474 self
475 }
476 # [ doc = "Bit 6 - RX buffer not empty interrupt enable" ]
477 pub fn rxneie(&mut self, value: bool) -> &mut Self {
478 const OFFSET: u8 = 6u8;
479 if value {
480 self.bits |= 1 << OFFSET;
481 } else {
482 self.bits &= !(1 << OFFSET);
483 }
484 self
485 }
486 # [ doc = "Bit 7 - Tx buffer empty interrupt enable" ]
487 pub fn txeie(&mut self, value: bool) -> &mut Self {
488 const OFFSET: u8 = 7u8;
489 if value {
490 self.bits |= 1 << OFFSET;
491 } else {
492 self.bits &= !(1 << OFFSET);
493 }
494 self
495 }
496 # [ doc = "Bits 8:11 - Data size" ]
497 pub fn ds(&mut self, value: u8) -> &mut Self {
498 const OFFSET: u8 = 8u8;
499 const MASK: u8 = 15;
500 self.bits &= !((MASK as u32) << OFFSET);
501 self.bits |= ((value & MASK) as u32) << OFFSET;
502 self
503 }
504 # [ doc = "Bit 12 - FIFO reception threshold" ]
505 pub fn frxth(&mut self, value: bool) -> &mut Self {
506 const OFFSET: u8 = 12u8;
507 if value {
508 self.bits |= 1 << OFFSET;
509 } else {
510 self.bits &= !(1 << OFFSET);
511 }
512 self
513 }
514 # [ doc = "Bit 13 - Last DMA transfer for reception" ]
515 pub fn ldma_rx(&mut self, value: bool) -> &mut Self {
516 const OFFSET: u8 = 13u8;
517 if value {
518 self.bits |= 1 << OFFSET;
519 } else {
520 self.bits &= !(1 << OFFSET);
521 }
522 self
523 }
524 # [ doc = "Bit 14 - Last DMA transfer for transmission" ]
525 pub fn ldma_tx(&mut self, value: bool) -> &mut Self {
526 const OFFSET: u8 = 14u8;
527 if value {
528 self.bits |= 1 << OFFSET;
529 } else {
530 self.bits &= !(1 << OFFSET);
531 }
532 self
533 }
534}
535
536# [ repr ( C ) ]
537pub struct Sr {
538 register: ::volatile_register::RW<u32>,
539}
540
541impl Sr {
542 pub fn read_bits(&self) -> u32 {
543 self.register.read()
544 }
545 pub unsafe fn modify_bits<F>(&mut self, f: F)
546 where F: FnOnce(&mut u32)
547 {
548 let mut bits = self.register.read();
549 f(&mut bits);
550 self.register.write(bits);
551 }
552 pub unsafe fn write_bits(&mut self, bits: u32) {
553 self.register.write(bits);
554 }
555 pub fn modify<F>(&mut self, f: F)
556 where for<'w> F: FnOnce(&SrR, &'w mut SrW) -> &'w mut SrW
557 {
558 let bits = self.register.read();
559 let r = SrR { bits: bits };
560 let mut w = SrW { bits: bits };
561 f(&r, &mut w);
562 self.register.write(w.bits);
563 }
564 pub fn read(&self) -> SrR {
565 SrR { bits: self.register.read() }
566 }
567 pub fn write<F>(&mut self, f: F)
568 where F: FnOnce(&mut SrW) -> &mut SrW
569 {
570 let mut w = SrW::reset_value();
571 f(&mut w);
572 self.register.write(w.bits);
573 }
574}
575
576# [ derive ( Clone , Copy ) ]
577# [ repr ( C ) ]
578pub struct SrR {
579 bits: u32,
580}
581
582impl SrR {
583 # [ doc = "Bit 0 - Receive buffer not empty" ]
584 pub fn rxne(&self) -> bool {
585 const OFFSET: u8 = 0u8;
586 self.bits & (1 << OFFSET) != 0
587 }
588 # [ doc = "Bit 1 - Transmit buffer empty" ]
589 pub fn txe(&self) -> bool {
590 const OFFSET: u8 = 1u8;
591 self.bits & (1 << OFFSET) != 0
592 }
593 # [ doc = "Bit 2 - Channel side" ]
594 pub fn chside(&self) -> bool {
595 const OFFSET: u8 = 2u8;
596 self.bits & (1 << OFFSET) != 0
597 }
598 # [ doc = "Bit 3 - Underrun flag" ]
599 pub fn udr(&self) -> bool {
600 const OFFSET: u8 = 3u8;
601 self.bits & (1 << OFFSET) != 0
602 }
603 # [ doc = "Bit 4 - CRC error flag" ]
604 pub fn crcerr(&self) -> bool {
605 const OFFSET: u8 = 4u8;
606 self.bits & (1 << OFFSET) != 0
607 }
608 # [ doc = "Bit 5 - Mode fault" ]
609 pub fn modf(&self) -> bool {
610 const OFFSET: u8 = 5u8;
611 self.bits & (1 << OFFSET) != 0
612 }
613 # [ doc = "Bit 6 - Overrun flag" ]
614 pub fn ovr(&self) -> bool {
615 const OFFSET: u8 = 6u8;
616 self.bits & (1 << OFFSET) != 0
617 }
618 # [ doc = "Bit 7 - Busy flag" ]
619 pub fn bsy(&self) -> bool {
620 const OFFSET: u8 = 7u8;
621 self.bits & (1 << OFFSET) != 0
622 }
623 # [ doc = "Bit 8 - TI frame format error" ]
624 pub fn tifrfe(&self) -> bool {
625 const OFFSET: u8 = 8u8;
626 self.bits & (1 << OFFSET) != 0
627 }
628 # [ doc = "Bits 9:10 - FIFO reception level" ]
629 pub fn frlvl(&self) -> u8 {
630 const MASK: u32 = 3;
631 const OFFSET: u8 = 9u8;
632 ((self.bits >> OFFSET) & MASK) as u8
633 }
634 # [ doc = "Bits 11:12 - FIFO transmission level" ]
635 pub fn ftlvl(&self) -> u8 {
636 const MASK: u32 = 3;
637 const OFFSET: u8 = 11u8;
638 ((self.bits >> OFFSET) & MASK) as u8
639 }
640}
641
642# [ derive ( Clone , Copy ) ]
643# [ repr ( C ) ]
644pub struct SrW {
645 bits: u32,
646}
647
648impl SrW {
649 # [ doc = r" Reset value" ]
650 pub fn reset_value() -> Self {
651 SrW { bits: 2 }
652 }
653 # [ doc = "Bit 4 - CRC error flag" ]
654 pub fn crcerr(&mut self, value: bool) -> &mut Self {
655 const OFFSET: u8 = 4u8;
656 if value {
657 self.bits |= 1 << OFFSET;
658 } else {
659 self.bits &= !(1 << OFFSET);
660 }
661 self
662 }
663}
664
665# [ repr ( C ) ]
666pub struct Dr {
667 register: ::volatile_register::RW<u32>,
668}
669
670impl Dr {
671 pub fn read_bits(&self) -> u32 {
672 self.register.read()
673 }
674 pub unsafe fn modify_bits<F>(&mut self, f: F)
675 where F: FnOnce(&mut u32)
676 {
677 let mut bits = self.register.read();
678 f(&mut bits);
679 self.register.write(bits);
680 }
681 pub unsafe fn write_bits(&mut self, bits: u32) {
682 self.register.write(bits);
683 }
684 pub fn modify<F>(&mut self, f: F)
685 where for<'w> F: FnOnce(&DrR, &'w mut DrW) -> &'w mut DrW
686 {
687 let bits = self.register.read();
688 let r = DrR { bits: bits };
689 let mut w = DrW { bits: bits };
690 f(&r, &mut w);
691 self.register.write(w.bits);
692 }
693 pub fn read(&self) -> DrR {
694 DrR { bits: self.register.read() }
695 }
696 pub fn write<F>(&mut self, f: F)
697 where F: FnOnce(&mut DrW) -> &mut DrW
698 {
699 let mut w = DrW::reset_value();
700 f(&mut w);
701 self.register.write(w.bits);
702 }
703}
704
705# [ derive ( Clone , Copy ) ]
706# [ repr ( C ) ]
707pub struct DrR {
708 bits: u32,
709}
710
711impl DrR {
712 # [ doc = "Bits 0:15 - Data register" ]
713 pub fn dr(&self) -> u16 {
714 const MASK: u32 = 65535;
715 const OFFSET: u8 = 0u8;
716 ((self.bits >> OFFSET) & MASK) as u16
717 }
718}
719
720# [ derive ( Clone , Copy ) ]
721# [ repr ( C ) ]
722pub struct DrW {
723 bits: u32,
724}
725
726impl DrW {
727 # [ doc = r" Reset value" ]
728 pub fn reset_value() -> Self {
729 DrW { bits: 0 }
730 }
731 # [ doc = "Bits 0:15 - Data register" ]
732 pub fn dr(&mut self, value: u16) -> &mut Self {
733 const OFFSET: u8 = 0u8;
734 const MASK: u16 = 65535;
735 self.bits &= !((MASK as u32) << OFFSET);
736 self.bits |= ((value & MASK) as u32) << OFFSET;
737 self
738 }
739}
740
741# [ repr ( C ) ]
742pub struct Crcpr {
743 register: ::volatile_register::RW<u32>,
744}
745
746impl Crcpr {
747 pub fn read_bits(&self) -> u32 {
748 self.register.read()
749 }
750 pub unsafe fn modify_bits<F>(&mut self, f: F)
751 where F: FnOnce(&mut u32)
752 {
753 let mut bits = self.register.read();
754 f(&mut bits);
755 self.register.write(bits);
756 }
757 pub unsafe fn write_bits(&mut self, bits: u32) {
758 self.register.write(bits);
759 }
760 pub fn modify<F>(&mut self, f: F)
761 where for<'w> F: FnOnce(&CrcprR, &'w mut CrcprW) -> &'w mut CrcprW
762 {
763 let bits = self.register.read();
764 let r = CrcprR { bits: bits };
765 let mut w = CrcprW { bits: bits };
766 f(&r, &mut w);
767 self.register.write(w.bits);
768 }
769 pub fn read(&self) -> CrcprR {
770 CrcprR { bits: self.register.read() }
771 }
772 pub fn write<F>(&mut self, f: F)
773 where F: FnOnce(&mut CrcprW) -> &mut CrcprW
774 {
775 let mut w = CrcprW::reset_value();
776 f(&mut w);
777 self.register.write(w.bits);
778 }
779}
780
781# [ derive ( Clone , Copy ) ]
782# [ repr ( C ) ]
783pub struct CrcprR {
784 bits: u32,
785}
786
787impl CrcprR {
788 # [ doc = "Bits 0:15 - CRC polynomial register" ]
789 pub fn crcpoly(&self) -> u16 {
790 const MASK: u32 = 65535;
791 const OFFSET: u8 = 0u8;
792 ((self.bits >> OFFSET) & MASK) as u16
793 }
794}
795
796# [ derive ( Clone , Copy ) ]
797# [ repr ( C ) ]
798pub struct CrcprW {
799 bits: u32,
800}
801
802impl CrcprW {
803 # [ doc = r" Reset value" ]
804 pub fn reset_value() -> Self {
805 CrcprW { bits: 7 }
806 }
807 # [ doc = "Bits 0:15 - CRC polynomial register" ]
808 pub fn crcpoly(&mut self, value: u16) -> &mut Self {
809 const OFFSET: u8 = 0u8;
810 const MASK: u16 = 65535;
811 self.bits &= !((MASK as u32) << OFFSET);
812 self.bits |= ((value & MASK) as u32) << OFFSET;
813 self
814 }
815}
816
817# [ repr ( C ) ]
818pub struct Rxcrcr {
819 register: ::volatile_register::RO<u32>,
820}
821
822impl Rxcrcr {
823 pub fn read_bits(&self) -> u32 {
824 self.register.read()
825 }
826 pub fn read(&self) -> RxcrcrR {
827 RxcrcrR { bits: self.register.read() }
828 }
829}
830
831# [ derive ( Clone , Copy ) ]
832# [ repr ( C ) ]
833pub struct RxcrcrR {
834 bits: u32,
835}
836
837impl RxcrcrR {
838 # [ doc = "Bits 0:15 - Rx CRC register" ]
839 pub fn rx_crc(&self) -> u16 {
840 const MASK: u32 = 65535;
841 const OFFSET: u8 = 0u8;
842 ((self.bits >> OFFSET) & MASK) as u16
843 }
844}
845
846# [ repr ( C ) ]
847pub struct Txcrcr {
848 register: ::volatile_register::RO<u32>,
849}
850
851impl Txcrcr {
852 pub fn read_bits(&self) -> u32 {
853 self.register.read()
854 }
855 pub fn read(&self) -> TxcrcrR {
856 TxcrcrR { bits: self.register.read() }
857 }
858}
859
860# [ derive ( Clone , Copy ) ]
861# [ repr ( C ) ]
862pub struct TxcrcrR {
863 bits: u32,
864}
865
866impl TxcrcrR {
867 # [ doc = "Bits 0:15 - Tx CRC register" ]
868 pub fn tx_crc(&self) -> u16 {
869 const MASK: u32 = 65535;
870 const OFFSET: u8 = 0u8;
871 ((self.bits >> OFFSET) & MASK) as u16
872 }
873}
874
875# [ repr ( C ) ]
876pub struct I2scfgr {
877 register: ::volatile_register::RW<u32>,
878}
879
880impl I2scfgr {
881 pub fn read_bits(&self) -> u32 {
882 self.register.read()
883 }
884 pub unsafe fn modify_bits<F>(&mut self, f: F)
885 where F: FnOnce(&mut u32)
886 {
887 let mut bits = self.register.read();
888 f(&mut bits);
889 self.register.write(bits);
890 }
891 pub unsafe fn write_bits(&mut self, bits: u32) {
892 self.register.write(bits);
893 }
894 pub fn modify<F>(&mut self, f: F)
895 where for<'w> F: FnOnce(&I2scfgrR, &'w mut I2scfgrW) -> &'w mut I2scfgrW
896 {
897 let bits = self.register.read();
898 let r = I2scfgrR { bits: bits };
899 let mut w = I2scfgrW { bits: bits };
900 f(&r, &mut w);
901 self.register.write(w.bits);
902 }
903 pub fn read(&self) -> I2scfgrR {
904 I2scfgrR { bits: self.register.read() }
905 }
906 pub fn write<F>(&mut self, f: F)
907 where F: FnOnce(&mut I2scfgrW) -> &mut I2scfgrW
908 {
909 let mut w = I2scfgrW::reset_value();
910 f(&mut w);
911 self.register.write(w.bits);
912 }
913}
914
915# [ derive ( Clone , Copy ) ]
916# [ repr ( C ) ]
917pub struct I2scfgrR {
918 bits: u32,
919}
920
921impl I2scfgrR {
922 # [ doc = "Bit 11 - I2S mode selection" ]
923 pub fn i2smod(&self) -> bool {
924 const OFFSET: u8 = 11u8;
925 self.bits & (1 << OFFSET) != 0
926 }
927 # [ doc = "Bit 10 - I2S Enable" ]
928 pub fn i2se(&self) -> bool {
929 const OFFSET: u8 = 10u8;
930 self.bits & (1 << OFFSET) != 0
931 }
932 # [ doc = "Bits 8:9 - I2S configuration mode" ]
933 pub fn i2scfg(&self) -> u8 {
934 const MASK: u32 = 3;
935 const OFFSET: u8 = 8u8;
936 ((self.bits >> OFFSET) & MASK) as u8
937 }
938 # [ doc = "Bit 7 - PCM frame synchronization" ]
939 pub fn pcmsync(&self) -> bool {
940 const OFFSET: u8 = 7u8;
941 self.bits & (1 << OFFSET) != 0
942 }
943 # [ doc = "Bits 4:5 - I2S standard selection" ]
944 pub fn i2sstd(&self) -> u8 {
945 const MASK: u32 = 3;
946 const OFFSET: u8 = 4u8;
947 ((self.bits >> OFFSET) & MASK) as u8
948 }
949 # [ doc = "Bit 3 - Steady state clock polarity" ]
950 pub fn ckpol(&self) -> bool {
951 const OFFSET: u8 = 3u8;
952 self.bits & (1 << OFFSET) != 0
953 }
954 # [ doc = "Bits 1:2 - Data length to be transferred" ]
955 pub fn datlen(&self) -> u8 {
956 const MASK: u32 = 3;
957 const OFFSET: u8 = 1u8;
958 ((self.bits >> OFFSET) & MASK) as u8
959 }
960 # [ doc = "Bit 0 - Channel length (number of bits per audio channel)" ]
961 pub fn chlen(&self) -> bool {
962 const OFFSET: u8 = 0u8;
963 self.bits & (1 << OFFSET) != 0
964 }
965}
966
967# [ derive ( Clone , Copy ) ]
968# [ repr ( C ) ]
969pub struct I2scfgrW {
970 bits: u32,
971}
972
973impl I2scfgrW {
974 # [ doc = r" Reset value" ]
975 pub fn reset_value() -> Self {
976 I2scfgrW { bits: 0 }
977 }
978 # [ doc = "Bit 11 - I2S mode selection" ]
979 pub fn i2smod(&mut self, value: bool) -> &mut Self {
980 const OFFSET: u8 = 11u8;
981 if value {
982 self.bits |= 1 << OFFSET;
983 } else {
984 self.bits &= !(1 << OFFSET);
985 }
986 self
987 }
988 # [ doc = "Bit 10 - I2S Enable" ]
989 pub fn i2se(&mut self, value: bool) -> &mut Self {
990 const OFFSET: u8 = 10u8;
991 if value {
992 self.bits |= 1 << OFFSET;
993 } else {
994 self.bits &= !(1 << OFFSET);
995 }
996 self
997 }
998 # [ doc = "Bits 8:9 - I2S configuration mode" ]
999 pub fn i2scfg(&mut self, value: u8) -> &mut Self {
1000 const OFFSET: u8 = 8u8;
1001 const MASK: u8 = 3;
1002 self.bits &= !((MASK as u32) << OFFSET);
1003 self.bits |= ((value & MASK) as u32) << OFFSET;
1004 self
1005 }
1006 # [ doc = "Bit 7 - PCM frame synchronization" ]
1007 pub fn pcmsync(&mut self, value: bool) -> &mut Self {
1008 const OFFSET: u8 = 7u8;
1009 if value {
1010 self.bits |= 1 << OFFSET;
1011 } else {
1012 self.bits &= !(1 << OFFSET);
1013 }
1014 self
1015 }
1016 # [ doc = "Bits 4:5 - I2S standard selection" ]
1017 pub fn i2sstd(&mut self, value: u8) -> &mut Self {
1018 const OFFSET: u8 = 4u8;
1019 const MASK: u8 = 3;
1020 self.bits &= !((MASK as u32) << OFFSET);
1021 self.bits |= ((value & MASK) as u32) << OFFSET;
1022 self
1023 }
1024 # [ doc = "Bit 3 - Steady state clock polarity" ]
1025 pub fn ckpol(&mut self, value: bool) -> &mut Self {
1026 const OFFSET: u8 = 3u8;
1027 if value {
1028 self.bits |= 1 << OFFSET;
1029 } else {
1030 self.bits &= !(1 << OFFSET);
1031 }
1032 self
1033 }
1034 # [ doc = "Bits 1:2 - Data length to be transferred" ]
1035 pub fn datlen(&mut self, value: u8) -> &mut Self {
1036 const OFFSET: u8 = 1u8;
1037 const MASK: u8 = 3;
1038 self.bits &= !((MASK as u32) << OFFSET);
1039 self.bits |= ((value & MASK) as u32) << OFFSET;
1040 self
1041 }
1042 # [ doc = "Bit 0 - Channel length (number of bits per audio channel)" ]
1043 pub fn chlen(&mut self, value: bool) -> &mut Self {
1044 const OFFSET: u8 = 0u8;
1045 if value {
1046 self.bits |= 1 << OFFSET;
1047 } else {
1048 self.bits &= !(1 << OFFSET);
1049 }
1050 self
1051 }
1052}
1053
1054# [ repr ( C ) ]
1055pub struct I2spr {
1056 register: ::volatile_register::RW<u32>,
1057}
1058
1059impl I2spr {
1060 pub fn read_bits(&self) -> u32 {
1061 self.register.read()
1062 }
1063 pub unsafe fn modify_bits<F>(&mut self, f: F)
1064 where F: FnOnce(&mut u32)
1065 {
1066 let mut bits = self.register.read();
1067 f(&mut bits);
1068 self.register.write(bits);
1069 }
1070 pub unsafe fn write_bits(&mut self, bits: u32) {
1071 self.register.write(bits);
1072 }
1073 pub fn modify<F>(&mut self, f: F)
1074 where for<'w> F: FnOnce(&I2sprR, &'w mut I2sprW) -> &'w mut I2sprW
1075 {
1076 let bits = self.register.read();
1077 let r = I2sprR { bits: bits };
1078 let mut w = I2sprW { bits: bits };
1079 f(&r, &mut w);
1080 self.register.write(w.bits);
1081 }
1082 pub fn read(&self) -> I2sprR {
1083 I2sprR { bits: self.register.read() }
1084 }
1085 pub fn write<F>(&mut self, f: F)
1086 where F: FnOnce(&mut I2sprW) -> &mut I2sprW
1087 {
1088 let mut w = I2sprW::reset_value();
1089 f(&mut w);
1090 self.register.write(w.bits);
1091 }
1092}
1093
1094# [ derive ( Clone , Copy ) ]
1095# [ repr ( C ) ]
1096pub struct I2sprR {
1097 bits: u32,
1098}
1099
1100impl I2sprR {
1101 # [ doc = "Bit 9 - Master clock output enable" ]
1102 pub fn mckoe(&self) -> bool {
1103 const OFFSET: u8 = 9u8;
1104 self.bits & (1 << OFFSET) != 0
1105 }
1106 # [ doc = "Bit 8 - Odd factor for the prescaler" ]
1107 pub fn odd(&self) -> bool {
1108 const OFFSET: u8 = 8u8;
1109 self.bits & (1 << OFFSET) != 0
1110 }
1111 # [ doc = "Bits 0:7 - I2S Linear prescaler" ]
1112 pub fn i2sdiv(&self) -> u8 {
1113 const MASK: u32 = 255;
1114 const OFFSET: u8 = 0u8;
1115 ((self.bits >> OFFSET) & MASK) as u8
1116 }
1117}
1118
1119# [ derive ( Clone , Copy ) ]
1120# [ repr ( C ) ]
1121pub struct I2sprW {
1122 bits: u32,
1123}
1124
1125impl I2sprW {
1126 # [ doc = r" Reset value" ]
1127 pub fn reset_value() -> Self {
1128 I2sprW { bits: 16 }
1129 }
1130 # [ doc = "Bit 9 - Master clock output enable" ]
1131 pub fn mckoe(&mut self, value: bool) -> &mut Self {
1132 const OFFSET: u8 = 9u8;
1133 if value {
1134 self.bits |= 1 << OFFSET;
1135 } else {
1136 self.bits &= !(1 << OFFSET);
1137 }
1138 self
1139 }
1140 # [ doc = "Bit 8 - Odd factor for the prescaler" ]
1141 pub fn odd(&mut self, value: bool) -> &mut Self {
1142 const OFFSET: u8 = 8u8;
1143 if value {
1144 self.bits |= 1 << OFFSET;
1145 } else {
1146 self.bits &= !(1 << OFFSET);
1147 }
1148 self
1149 }
1150 # [ doc = "Bits 0:7 - I2S Linear prescaler" ]
1151 pub fn i2sdiv(&mut self, value: u8) -> &mut Self {
1152 const OFFSET: u8 = 0u8;
1153 const MASK: u8 = 255;
1154 self.bits &= !((MASK as u32) << OFFSET);
1155 self.bits |= ((value & MASK) as u32) << OFFSET;
1156 self
1157 }
1158}