1# [ doc = "Reset and clock control" ]
2# [ repr ( C ) ]
3pub struct Rcc {
4 # [ doc = "0x00 - Clock control register" ]
5 pub cr: Cr,
6 # [ doc = "0x04 - Clock configuration register (RCC_CFGR)" ]
7 pub cfgr: Cfgr,
8 # [ doc = "0x08 - Clock interrupt register (RCC_CIR)" ]
9 pub cir: Cir,
10 # [ doc = "0x0c - APB2 peripheral reset register (RCC_APB2RSTR)" ]
11 pub apb2rstr: Apb2rstr,
12 # [ doc = "0x10 - APB1 peripheral reset register (RCC_APB1RSTR)" ]
13 pub apb1rstr: Apb1rstr,
14 # [ doc = "0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)" ]
15 pub ahbenr: Ahbenr,
16 # [ doc = "0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)" ]
17 pub apb2enr: Apb2enr,
18 # [ doc = "0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)" ]
19 pub apb1enr: Apb1enr,
20 # [ doc = "0x20 - Backup domain control register (RCC_BDCR)" ]
21 pub bdcr: Bdcr,
22 # [ doc = "0x24 - Control/status register (RCC_CSR)" ]
23 pub csr: Csr,
24 # [ doc = "0x28 - AHB peripheral reset register" ]
25 pub ahbrstr: Ahbrstr,
26 # [ doc = "0x2c - Clock configuration register 2" ]
27 pub cfgr2: Cfgr2,
28 # [ doc = "0x30 - Clock configuration register 3" ]
29 pub cfgr3: Cfgr3,
30}
31
32# [ repr ( C ) ]
33pub struct Cr {
34 register: ::volatile_register::RW<u32>,
35}
36
37impl Cr {
38 pub fn read_bits(&self) -> u32 {
39 self.register.read()
40 }
41 pub unsafe fn modify_bits<F>(&mut self, f: F)
42 where F: FnOnce(&mut u32)
43 {
44 let mut bits = self.register.read();
45 f(&mut bits);
46 self.register.write(bits);
47 }
48 pub unsafe fn write_bits(&mut self, bits: u32) {
49 self.register.write(bits);
50 }
51 pub fn modify<F>(&mut self, f: F)
52 where for<'w> F: FnOnce(&CrR, &'w mut CrW) -> &'w mut CrW
53 {
54 let bits = self.register.read();
55 let r = CrR { bits: bits };
56 let mut w = CrW { bits: bits };
57 f(&r, &mut w);
58 self.register.write(w.bits);
59 }
60 pub fn read(&self) -> CrR {
61 CrR { bits: self.register.read() }
62 }
63 pub fn write<F>(&mut self, f: F)
64 where F: FnOnce(&mut CrW) -> &mut CrW
65 {
66 let mut w = CrW::reset_value();
67 f(&mut w);
68 self.register.write(w.bits);
69 }
70}
71
72# [ derive ( Clone , Copy ) ]
73# [ repr ( C ) ]
74pub struct CrR {
75 bits: u32,
76}
77
78impl CrR {
79 # [ doc = "Bit 0 - Internal High Speed clock enable" ]
80 pub fn hsion(&self) -> bool {
81 const OFFSET: u8 = 0u8;
82 self.bits & (1 << OFFSET) != 0
83 }
84 # [ doc = "Bit 1 - Internal High Speed clock ready flag" ]
85 pub fn hsirdy(&self) -> bool {
86 const OFFSET: u8 = 1u8;
87 self.bits & (1 << OFFSET) != 0
88 }
89 # [ doc = "Bits 3:7 - Internal High Speed clock trimming" ]
90 pub fn hsitrim(&self) -> u8 {
91 const MASK: u32 = 31;
92 const OFFSET: u8 = 3u8;
93 ((self.bits >> OFFSET) & MASK) as u8
94 }
95 # [ doc = "Bits 8:15 - Internal High Speed clock Calibration" ]
96 pub fn hsical(&self) -> u8 {
97 const MASK: u32 = 255;
98 const OFFSET: u8 = 8u8;
99 ((self.bits >> OFFSET) & MASK) as u8
100 }
101 # [ doc = "Bit 16 - External High Speed clock enable" ]
102 pub fn hseon(&self) -> bool {
103 const OFFSET: u8 = 16u8;
104 self.bits & (1 << OFFSET) != 0
105 }
106 # [ doc = "Bit 17 - External High Speed clock ready flag" ]
107 pub fn hserdy(&self) -> bool {
108 const OFFSET: u8 = 17u8;
109 self.bits & (1 << OFFSET) != 0
110 }
111 # [ doc = "Bit 18 - External High Speed clock Bypass" ]
112 pub fn hsebyp(&self) -> bool {
113 const OFFSET: u8 = 18u8;
114 self.bits & (1 << OFFSET) != 0
115 }
116 # [ doc = "Bit 19 - Clock Security System enable" ]
117 pub fn csson(&self) -> bool {
118 const OFFSET: u8 = 19u8;
119 self.bits & (1 << OFFSET) != 0
120 }
121 # [ doc = "Bit 24 - PLL enable" ]
122 pub fn pllon(&self) -> bool {
123 const OFFSET: u8 = 24u8;
124 self.bits & (1 << OFFSET) != 0
125 }
126 # [ doc = "Bit 25 - PLL clock ready flag" ]
127 pub fn pllrdy(&self) -> bool {
128 const OFFSET: u8 = 25u8;
129 self.bits & (1 << OFFSET) != 0
130 }
131}
132
133# [ derive ( Clone , Copy ) ]
134# [ repr ( C ) ]
135pub struct CrW {
136 bits: u32,
137}
138
139impl CrW {
140 # [ doc = r" Reset value" ]
141 pub fn reset_value() -> Self {
142 CrW { bits: 131 }
143 }
144 # [ doc = "Bit 0 - Internal High Speed clock enable" ]
145 pub fn hsion(&mut self, value: bool) -> &mut Self {
146 const OFFSET: u8 = 0u8;
147 if value {
148 self.bits |= 1 << OFFSET;
149 } else {
150 self.bits &= !(1 << OFFSET);
151 }
152 self
153 }
154 # [ doc = "Bits 3:7 - Internal High Speed clock trimming" ]
155 pub fn hsitrim(&mut self, value: u8) -> &mut Self {
156 const OFFSET: u8 = 3u8;
157 const MASK: u8 = 31;
158 self.bits &= !((MASK as u32) << OFFSET);
159 self.bits |= ((value & MASK) as u32) << OFFSET;
160 self
161 }
162 # [ doc = "Bit 16 - External High Speed clock enable" ]
163 pub fn hseon(&mut self, value: bool) -> &mut Self {
164 const OFFSET: u8 = 16u8;
165 if value {
166 self.bits |= 1 << OFFSET;
167 } else {
168 self.bits &= !(1 << OFFSET);
169 }
170 self
171 }
172 # [ doc = "Bit 18 - External High Speed clock Bypass" ]
173 pub fn hsebyp(&mut self, value: bool) -> &mut Self {
174 const OFFSET: u8 = 18u8;
175 if value {
176 self.bits |= 1 << OFFSET;
177 } else {
178 self.bits &= !(1 << OFFSET);
179 }
180 self
181 }
182 # [ doc = "Bit 19 - Clock Security System enable" ]
183 pub fn csson(&mut self, value: bool) -> &mut Self {
184 const OFFSET: u8 = 19u8;
185 if value {
186 self.bits |= 1 << OFFSET;
187 } else {
188 self.bits &= !(1 << OFFSET);
189 }
190 self
191 }
192 # [ doc = "Bit 24 - PLL enable" ]
193 pub fn pllon(&mut self, value: bool) -> &mut Self {
194 const OFFSET: u8 = 24u8;
195 if value {
196 self.bits |= 1 << OFFSET;
197 } else {
198 self.bits &= !(1 << OFFSET);
199 }
200 self
201 }
202}
203
204# [ repr ( C ) ]
205pub struct Cfgr {
206 register: ::volatile_register::RW<u32>,
207}
208
209impl Cfgr {
210 pub fn read_bits(&self) -> u32 {
211 self.register.read()
212 }
213 pub unsafe fn modify_bits<F>(&mut self, f: F)
214 where F: FnOnce(&mut u32)
215 {
216 let mut bits = self.register.read();
217 f(&mut bits);
218 self.register.write(bits);
219 }
220 pub unsafe fn write_bits(&mut self, bits: u32) {
221 self.register.write(bits);
222 }
223 pub fn modify<F>(&mut self, f: F)
224 where for<'w> F: FnOnce(&CfgrR, &'w mut CfgrW) -> &'w mut CfgrW
225 {
226 let bits = self.register.read();
227 let r = CfgrR { bits: bits };
228 let mut w = CfgrW { bits: bits };
229 f(&r, &mut w);
230 self.register.write(w.bits);
231 }
232 pub fn read(&self) -> CfgrR {
233 CfgrR { bits: self.register.read() }
234 }
235 pub fn write<F>(&mut self, f: F)
236 where F: FnOnce(&mut CfgrW) -> &mut CfgrW
237 {
238 let mut w = CfgrW::reset_value();
239 f(&mut w);
240 self.register.write(w.bits);
241 }
242}
243
244# [ derive ( Clone , Copy ) ]
245# [ repr ( C ) ]
246pub struct CfgrR {
247 bits: u32,
248}
249
250impl CfgrR {
251 # [ doc = "Bits 0:1 - System clock Switch" ]
252 pub fn sw(&self) -> u8 {
253 const MASK: u32 = 3;
254 const OFFSET: u8 = 0u8;
255 ((self.bits >> OFFSET) & MASK) as u8
256 }
257 # [ doc = "Bits 2:3 - System Clock Switch Status" ]
258 pub fn sws(&self) -> u8 {
259 const MASK: u32 = 3;
260 const OFFSET: u8 = 2u8;
261 ((self.bits >> OFFSET) & MASK) as u8
262 }
263 # [ doc = "Bits 4:7 - AHB prescaler" ]
264 pub fn hpre(&self) -> u8 {
265 const MASK: u32 = 15;
266 const OFFSET: u8 = 4u8;
267 ((self.bits >> OFFSET) & MASK) as u8
268 }
269 # [ doc = "Bits 8:10 - APB Low speed prescaler (APB1)" ]
270 pub fn ppre1(&self) -> u8 {
271 const MASK: u32 = 7;
272 const OFFSET: u8 = 8u8;
273 ((self.bits >> OFFSET) & MASK) as u8
274 }
275 # [ doc = "Bits 11:13 - APB high speed prescaler (APB2)" ]
276 pub fn ppre2(&self) -> u8 {
277 const MASK: u32 = 7;
278 const OFFSET: u8 = 11u8;
279 ((self.bits >> OFFSET) & MASK) as u8
280 }
281 # [ doc = "Bit 16 - PLL entry clock source" ]
282 pub fn pllsrc(&self) -> bool {
283 const OFFSET: u8 = 16u8;
284 self.bits & (1 << OFFSET) != 0
285 }
286 # [ doc = "Bit 17 - HSE divider for PLL entry" ]
287 pub fn pllxtpre(&self) -> bool {
288 const OFFSET: u8 = 17u8;
289 self.bits & (1 << OFFSET) != 0
290 }
291 # [ doc = "Bits 18:21 - PLL Multiplication Factor" ]
292 pub fn pllmul(&self) -> u8 {
293 const MASK: u32 = 15;
294 const OFFSET: u8 = 18u8;
295 ((self.bits >> OFFSET) & MASK) as u8
296 }
297 # [ doc = "Bit 22 - USB prescaler" ]
298 pub fn usbpres(&self) -> bool {
299 const OFFSET: u8 = 22u8;
300 self.bits & (1 << OFFSET) != 0
301 }
302 # [ doc = "Bits 24:26 - Microcontroller clock output" ]
303 pub fn mco(&self) -> u8 {
304 const MASK: u32 = 7;
305 const OFFSET: u8 = 24u8;
306 ((self.bits >> OFFSET) & MASK) as u8
307 }
308 # [ doc = "Bit 28 - Microcontroller Clock Output Flag" ]
309 pub fn mcof(&self) -> bool {
310 const OFFSET: u8 = 28u8;
311 self.bits & (1 << OFFSET) != 0
312 }
313 # [ doc = "Bit 23 - I2S external clock source selection" ]
314 pub fn i2ssrc(&self) -> bool {
315 const OFFSET: u8 = 23u8;
316 self.bits & (1 << OFFSET) != 0
317 }
318}
319
320# [ derive ( Clone , Copy ) ]
321# [ repr ( C ) ]
322pub struct CfgrW {
323 bits: u32,
324}
325
326impl CfgrW {
327 # [ doc = r" Reset value" ]
328 pub fn reset_value() -> Self {
329 CfgrW { bits: 0 }
330 }
331 # [ doc = "Bits 0:1 - System clock Switch" ]
332 pub fn sw(&mut self, value: u8) -> &mut Self {
333 const OFFSET: u8 = 0u8;
334 const MASK: u8 = 3;
335 self.bits &= !((MASK as u32) << OFFSET);
336 self.bits |= ((value & MASK) as u32) << OFFSET;
337 self
338 }
339 # [ doc = "Bits 4:7 - AHB prescaler" ]
340 pub fn hpre(&mut self, value: u8) -> &mut Self {
341 const OFFSET: u8 = 4u8;
342 const MASK: u8 = 15;
343 self.bits &= !((MASK as u32) << OFFSET);
344 self.bits |= ((value & MASK) as u32) << OFFSET;
345 self
346 }
347 # [ doc = "Bits 8:10 - APB Low speed prescaler (APB1)" ]
348 pub fn ppre1(&mut self, value: u8) -> &mut Self {
349 const OFFSET: u8 = 8u8;
350 const MASK: u8 = 7;
351 self.bits &= !((MASK as u32) << OFFSET);
352 self.bits |= ((value & MASK) as u32) << OFFSET;
353 self
354 }
355 # [ doc = "Bits 11:13 - APB high speed prescaler (APB2)" ]
356 pub fn ppre2(&mut self, value: u8) -> &mut Self {
357 const OFFSET: u8 = 11u8;
358 const MASK: u8 = 7;
359 self.bits &= !((MASK as u32) << OFFSET);
360 self.bits |= ((value & MASK) as u32) << OFFSET;
361 self
362 }
363 # [ doc = "Bit 16 - PLL entry clock source" ]
364 pub fn pllsrc(&mut self, value: bool) -> &mut Self {
365 const OFFSET: u8 = 16u8;
366 if value {
367 self.bits |= 1 << OFFSET;
368 } else {
369 self.bits &= !(1 << OFFSET);
370 }
371 self
372 }
373 # [ doc = "Bit 17 - HSE divider for PLL entry" ]
374 pub fn pllxtpre(&mut self, value: bool) -> &mut Self {
375 const OFFSET: u8 = 17u8;
376 if value {
377 self.bits |= 1 << OFFSET;
378 } else {
379 self.bits &= !(1 << OFFSET);
380 }
381 self
382 }
383 # [ doc = "Bits 18:21 - PLL Multiplication Factor" ]
384 pub fn pllmul(&mut self, value: u8) -> &mut Self {
385 const OFFSET: u8 = 18u8;
386 const MASK: u8 = 15;
387 self.bits &= !((MASK as u32) << OFFSET);
388 self.bits |= ((value & MASK) as u32) << OFFSET;
389 self
390 }
391 # [ doc = "Bit 22 - USB prescaler" ]
392 pub fn usbpres(&mut self, value: bool) -> &mut Self {
393 const OFFSET: u8 = 22u8;
394 if value {
395 self.bits |= 1 << OFFSET;
396 } else {
397 self.bits &= !(1 << OFFSET);
398 }
399 self
400 }
401 # [ doc = "Bits 24:26 - Microcontroller clock output" ]
402 pub fn mco(&mut self, value: u8) -> &mut Self {
403 const OFFSET: u8 = 24u8;
404 const MASK: u8 = 7;
405 self.bits &= !((MASK as u32) << OFFSET);
406 self.bits |= ((value & MASK) as u32) << OFFSET;
407 self
408 }
409 # [ doc = "Bit 23 - I2S external clock source selection" ]
410 pub fn i2ssrc(&mut self, value: bool) -> &mut Self {
411 const OFFSET: u8 = 23u8;
412 if value {
413 self.bits |= 1 << OFFSET;
414 } else {
415 self.bits &= !(1 << OFFSET);
416 }
417 self
418 }
419}
420
421# [ repr ( C ) ]
422pub struct Cir {
423 register: ::volatile_register::RW<u32>,
424}
425
426impl Cir {
427 pub fn read_bits(&self) -> u32 {
428 self.register.read()
429 }
430 pub unsafe fn modify_bits<F>(&mut self, f: F)
431 where F: FnOnce(&mut u32)
432 {
433 let mut bits = self.register.read();
434 f(&mut bits);
435 self.register.write(bits);
436 }
437 pub unsafe fn write_bits(&mut self, bits: u32) {
438 self.register.write(bits);
439 }
440 pub fn modify<F>(&mut self, f: F)
441 where for<'w> F: FnOnce(&CirR, &'w mut CirW) -> &'w mut CirW
442 {
443 let bits = self.register.read();
444 let r = CirR { bits: bits };
445 let mut w = CirW { bits: bits };
446 f(&r, &mut w);
447 self.register.write(w.bits);
448 }
449 pub fn read(&self) -> CirR {
450 CirR { bits: self.register.read() }
451 }
452 pub fn write<F>(&mut self, f: F)
453 where F: FnOnce(&mut CirW) -> &mut CirW
454 {
455 let mut w = CirW::reset_value();
456 f(&mut w);
457 self.register.write(w.bits);
458 }
459}
460
461# [ derive ( Clone , Copy ) ]
462# [ repr ( C ) ]
463pub struct CirR {
464 bits: u32,
465}
466
467impl CirR {
468 # [ doc = "Bit 0 - LSI Ready Interrupt flag" ]
469 pub fn lsirdyf(&self) -> bool {
470 const OFFSET: u8 = 0u8;
471 self.bits & (1 << OFFSET) != 0
472 }
473 # [ doc = "Bit 1 - LSE Ready Interrupt flag" ]
474 pub fn lserdyf(&self) -> bool {
475 const OFFSET: u8 = 1u8;
476 self.bits & (1 << OFFSET) != 0
477 }
478 # [ doc = "Bit 2 - HSI Ready Interrupt flag" ]
479 pub fn hsirdyf(&self) -> bool {
480 const OFFSET: u8 = 2u8;
481 self.bits & (1 << OFFSET) != 0
482 }
483 # [ doc = "Bit 3 - HSE Ready Interrupt flag" ]
484 pub fn hserdyf(&self) -> bool {
485 const OFFSET: u8 = 3u8;
486 self.bits & (1 << OFFSET) != 0
487 }
488 # [ doc = "Bit 4 - PLL Ready Interrupt flag" ]
489 pub fn pllrdyf(&self) -> bool {
490 const OFFSET: u8 = 4u8;
491 self.bits & (1 << OFFSET) != 0
492 }
493 # [ doc = "Bit 7 - Clock Security System Interrupt flag" ]
494 pub fn cssf(&self) -> bool {
495 const OFFSET: u8 = 7u8;
496 self.bits & (1 << OFFSET) != 0
497 }
498 # [ doc = "Bit 8 - LSI Ready Interrupt Enable" ]
499 pub fn lsirdyie(&self) -> bool {
500 const OFFSET: u8 = 8u8;
501 self.bits & (1 << OFFSET) != 0
502 }
503 # [ doc = "Bit 9 - LSE Ready Interrupt Enable" ]
504 pub fn lserdyie(&self) -> bool {
505 const OFFSET: u8 = 9u8;
506 self.bits & (1 << OFFSET) != 0
507 }
508 # [ doc = "Bit 10 - HSI Ready Interrupt Enable" ]
509 pub fn hsirdyie(&self) -> bool {
510 const OFFSET: u8 = 10u8;
511 self.bits & (1 << OFFSET) != 0
512 }
513 # [ doc = "Bit 11 - HSE Ready Interrupt Enable" ]
514 pub fn hserdyie(&self) -> bool {
515 const OFFSET: u8 = 11u8;
516 self.bits & (1 << OFFSET) != 0
517 }
518 # [ doc = "Bit 12 - PLL Ready Interrupt Enable" ]
519 pub fn pllrdyie(&self) -> bool {
520 const OFFSET: u8 = 12u8;
521 self.bits & (1 << OFFSET) != 0
522 }
523}
524
525# [ derive ( Clone , Copy ) ]
526# [ repr ( C ) ]
527pub struct CirW {
528 bits: u32,
529}
530
531impl CirW {
532 # [ doc = r" Reset value" ]
533 pub fn reset_value() -> Self {
534 CirW { bits: 0 }
535 }
536 # [ doc = "Bit 8 - LSI Ready Interrupt Enable" ]
537 pub fn lsirdyie(&mut self, value: bool) -> &mut Self {
538 const OFFSET: u8 = 8u8;
539 if value {
540 self.bits |= 1 << OFFSET;
541 } else {
542 self.bits &= !(1 << OFFSET);
543 }
544 self
545 }
546 # [ doc = "Bit 9 - LSE Ready Interrupt Enable" ]
547 pub fn lserdyie(&mut self, value: bool) -> &mut Self {
548 const OFFSET: u8 = 9u8;
549 if value {
550 self.bits |= 1 << OFFSET;
551 } else {
552 self.bits &= !(1 << OFFSET);
553 }
554 self
555 }
556 # [ doc = "Bit 10 - HSI Ready Interrupt Enable" ]
557 pub fn hsirdyie(&mut self, value: bool) -> &mut Self {
558 const OFFSET: u8 = 10u8;
559 if value {
560 self.bits |= 1 << OFFSET;
561 } else {
562 self.bits &= !(1 << OFFSET);
563 }
564 self
565 }
566 # [ doc = "Bit 11 - HSE Ready Interrupt Enable" ]
567 pub fn hserdyie(&mut self, value: bool) -> &mut Self {
568 const OFFSET: u8 = 11u8;
569 if value {
570 self.bits |= 1 << OFFSET;
571 } else {
572 self.bits &= !(1 << OFFSET);
573 }
574 self
575 }
576 # [ doc = "Bit 12 - PLL Ready Interrupt Enable" ]
577 pub fn pllrdyie(&mut self, value: bool) -> &mut Self {
578 const OFFSET: u8 = 12u8;
579 if value {
580 self.bits |= 1 << OFFSET;
581 } else {
582 self.bits &= !(1 << OFFSET);
583 }
584 self
585 }
586 # [ doc = "Bit 16 - LSI Ready Interrupt Clear" ]
587 pub fn lsirdyc(&mut self, value: bool) -> &mut Self {
588 const OFFSET: u8 = 16u8;
589 if value {
590 self.bits |= 1 << OFFSET;
591 } else {
592 self.bits &= !(1 << OFFSET);
593 }
594 self
595 }
596 # [ doc = "Bit 17 - LSE Ready Interrupt Clear" ]
597 pub fn lserdyc(&mut self, value: bool) -> &mut Self {
598 const OFFSET: u8 = 17u8;
599 if value {
600 self.bits |= 1 << OFFSET;
601 } else {
602 self.bits &= !(1 << OFFSET);
603 }
604 self
605 }
606 # [ doc = "Bit 18 - HSI Ready Interrupt Clear" ]
607 pub fn hsirdyc(&mut self, value: bool) -> &mut Self {
608 const OFFSET: u8 = 18u8;
609 if value {
610 self.bits |= 1 << OFFSET;
611 } else {
612 self.bits &= !(1 << OFFSET);
613 }
614 self
615 }
616 # [ doc = "Bit 19 - HSE Ready Interrupt Clear" ]
617 pub fn hserdyc(&mut self, value: bool) -> &mut Self {
618 const OFFSET: u8 = 19u8;
619 if value {
620 self.bits |= 1 << OFFSET;
621 } else {
622 self.bits &= !(1 << OFFSET);
623 }
624 self
625 }
626 # [ doc = "Bit 20 - PLL Ready Interrupt Clear" ]
627 pub fn pllrdyc(&mut self, value: bool) -> &mut Self {
628 const OFFSET: u8 = 20u8;
629 if value {
630 self.bits |= 1 << OFFSET;
631 } else {
632 self.bits &= !(1 << OFFSET);
633 }
634 self
635 }
636 # [ doc = "Bit 23 - Clock security system interrupt clear" ]
637 pub fn cssc(&mut self, value: bool) -> &mut Self {
638 const OFFSET: u8 = 23u8;
639 if value {
640 self.bits |= 1 << OFFSET;
641 } else {
642 self.bits &= !(1 << OFFSET);
643 }
644 self
645 }
646}
647
648# [ repr ( C ) ]
649pub struct Apb2rstr {
650 register: ::volatile_register::RW<u32>,
651}
652
653impl Apb2rstr {
654 pub fn read_bits(&self) -> u32 {
655 self.register.read()
656 }
657 pub unsafe fn modify_bits<F>(&mut self, f: F)
658 where F: FnOnce(&mut u32)
659 {
660 let mut bits = self.register.read();
661 f(&mut bits);
662 self.register.write(bits);
663 }
664 pub unsafe fn write_bits(&mut self, bits: u32) {
665 self.register.write(bits);
666 }
667 pub fn modify<F>(&mut self, f: F)
668 where for<'w> F: FnOnce(&Apb2rstrR, &'w mut Apb2rstrW)
669 -> &'w mut Apb2rstrW
670 {
671 let bits = self.register.read();
672 let r = Apb2rstrR { bits: bits };
673 let mut w = Apb2rstrW { bits: bits };
674 f(&r, &mut w);
675 self.register.write(w.bits);
676 }
677 pub fn read(&self) -> Apb2rstrR {
678 Apb2rstrR { bits: self.register.read() }
679 }
680 pub fn write<F>(&mut self, f: F)
681 where F: FnOnce(&mut Apb2rstrW) -> &mut Apb2rstrW
682 {
683 let mut w = Apb2rstrW::reset_value();
684 f(&mut w);
685 self.register.write(w.bits);
686 }
687}
688
689# [ derive ( Clone , Copy ) ]
690# [ repr ( C ) ]
691pub struct Apb2rstrR {
692 bits: u32,
693}
694
695impl Apb2rstrR {
696 # [ doc = "Bit 0 - SYSCFG and COMP reset" ]
697 pub fn syscfgrst(&self) -> bool {
698 const OFFSET: u8 = 0u8;
699 self.bits & (1 << OFFSET) != 0
700 }
701 # [ doc = "Bit 11 - TIM1 timer reset" ]
702 pub fn tim1rst(&self) -> bool {
703 const OFFSET: u8 = 11u8;
704 self.bits & (1 << OFFSET) != 0
705 }
706 # [ doc = "Bit 12 - SPI 1 reset" ]
707 pub fn spi1rst(&self) -> bool {
708 const OFFSET: u8 = 12u8;
709 self.bits & (1 << OFFSET) != 0
710 }
711 # [ doc = "Bit 13 - TIM8 timer reset" ]
712 pub fn tim8rst(&self) -> bool {
713 const OFFSET: u8 = 13u8;
714 self.bits & (1 << OFFSET) != 0
715 }
716 # [ doc = "Bit 14 - USART1 reset" ]
717 pub fn usart1rst(&self) -> bool {
718 const OFFSET: u8 = 14u8;
719 self.bits & (1 << OFFSET) != 0
720 }
721 # [ doc = "Bit 16 - TIM15 timer reset" ]
722 pub fn tim15rst(&self) -> bool {
723 const OFFSET: u8 = 16u8;
724 self.bits & (1 << OFFSET) != 0
725 }
726 # [ doc = "Bit 17 - TIM16 timer reset" ]
727 pub fn tim16rst(&self) -> bool {
728 const OFFSET: u8 = 17u8;
729 self.bits & (1 << OFFSET) != 0
730 }
731 # [ doc = "Bit 18 - TIM17 timer reset" ]
732 pub fn tim17rst(&self) -> bool {
733 const OFFSET: u8 = 18u8;
734 self.bits & (1 << OFFSET) != 0
735 }
736}
737
738# [ derive ( Clone , Copy ) ]
739# [ repr ( C ) ]
740pub struct Apb2rstrW {
741 bits: u32,
742}
743
744impl Apb2rstrW {
745 # [ doc = r" Reset value" ]
746 pub fn reset_value() -> Self {
747 Apb2rstrW { bits: 0 }
748 }
749 # [ doc = "Bit 0 - SYSCFG and COMP reset" ]
750 pub fn syscfgrst(&mut self, value: bool) -> &mut Self {
751 const OFFSET: u8 = 0u8;
752 if value {
753 self.bits |= 1 << OFFSET;
754 } else {
755 self.bits &= !(1 << OFFSET);
756 }
757 self
758 }
759 # [ doc = "Bit 11 - TIM1 timer reset" ]
760 pub fn tim1rst(&mut self, value: bool) -> &mut Self {
761 const OFFSET: u8 = 11u8;
762 if value {
763 self.bits |= 1 << OFFSET;
764 } else {
765 self.bits &= !(1 << OFFSET);
766 }
767 self
768 }
769 # [ doc = "Bit 12 - SPI 1 reset" ]
770 pub fn spi1rst(&mut self, value: bool) -> &mut Self {
771 const OFFSET: u8 = 12u8;
772 if value {
773 self.bits |= 1 << OFFSET;
774 } else {
775 self.bits &= !(1 << OFFSET);
776 }
777 self
778 }
779 # [ doc = "Bit 13 - TIM8 timer reset" ]
780 pub fn tim8rst(&mut self, value: bool) -> &mut Self {
781 const OFFSET: u8 = 13u8;
782 if value {
783 self.bits |= 1 << OFFSET;
784 } else {
785 self.bits &= !(1 << OFFSET);
786 }
787 self
788 }
789 # [ doc = "Bit 14 - USART1 reset" ]
790 pub fn usart1rst(&mut self, value: bool) -> &mut Self {
791 const OFFSET: u8 = 14u8;
792 if value {
793 self.bits |= 1 << OFFSET;
794 } else {
795 self.bits &= !(1 << OFFSET);
796 }
797 self
798 }
799 # [ doc = "Bit 16 - TIM15 timer reset" ]
800 pub fn tim15rst(&mut self, value: bool) -> &mut Self {
801 const OFFSET: u8 = 16u8;
802 if value {
803 self.bits |= 1 << OFFSET;
804 } else {
805 self.bits &= !(1 << OFFSET);
806 }
807 self
808 }
809 # [ doc = "Bit 17 - TIM16 timer reset" ]
810 pub fn tim16rst(&mut self, value: bool) -> &mut Self {
811 const OFFSET: u8 = 17u8;
812 if value {
813 self.bits |= 1 << OFFSET;
814 } else {
815 self.bits &= !(1 << OFFSET);
816 }
817 self
818 }
819 # [ doc = "Bit 18 - TIM17 timer reset" ]
820 pub fn tim17rst(&mut self, value: bool) -> &mut Self {
821 const OFFSET: u8 = 18u8;
822 if value {
823 self.bits |= 1 << OFFSET;
824 } else {
825 self.bits &= !(1 << OFFSET);
826 }
827 self
828 }
829}
830
831# [ repr ( C ) ]
832pub struct Apb1rstr {
833 register: ::volatile_register::RW<u32>,
834}
835
836impl Apb1rstr {
837 pub fn read_bits(&self) -> u32 {
838 self.register.read()
839 }
840 pub unsafe fn modify_bits<F>(&mut self, f: F)
841 where F: FnOnce(&mut u32)
842 {
843 let mut bits = self.register.read();
844 f(&mut bits);
845 self.register.write(bits);
846 }
847 pub unsafe fn write_bits(&mut self, bits: u32) {
848 self.register.write(bits);
849 }
850 pub fn modify<F>(&mut self, f: F)
851 where for<'w> F: FnOnce(&Apb1rstrR, &'w mut Apb1rstrW)
852 -> &'w mut Apb1rstrW
853 {
854 let bits = self.register.read();
855 let r = Apb1rstrR { bits: bits };
856 let mut w = Apb1rstrW { bits: bits };
857 f(&r, &mut w);
858 self.register.write(w.bits);
859 }
860 pub fn read(&self) -> Apb1rstrR {
861 Apb1rstrR { bits: self.register.read() }
862 }
863 pub fn write<F>(&mut self, f: F)
864 where F: FnOnce(&mut Apb1rstrW) -> &mut Apb1rstrW
865 {
866 let mut w = Apb1rstrW::reset_value();
867 f(&mut w);
868 self.register.write(w.bits);
869 }
870}
871
872# [ derive ( Clone , Copy ) ]
873# [ repr ( C ) ]
874pub struct Apb1rstrR {
875 bits: u32,
876}
877
878impl Apb1rstrR {
879 # [ doc = "Bit 0 - Timer 2 reset" ]
880 pub fn tim2rst(&self) -> bool {
881 const OFFSET: u8 = 0u8;
882 self.bits & (1 << OFFSET) != 0
883 }
884 # [ doc = "Bit 1 - Timer 3 reset" ]
885 pub fn tim3rst(&self) -> bool {
886 const OFFSET: u8 = 1u8;
887 self.bits & (1 << OFFSET) != 0
888 }
889 # [ doc = "Bit 2 - Timer 14 reset" ]
890 pub fn tim4rst(&self) -> bool {
891 const OFFSET: u8 = 2u8;
892 self.bits & (1 << OFFSET) != 0
893 }
894 # [ doc = "Bit 4 - Timer 6 reset" ]
895 pub fn tim6rst(&self) -> bool {
896 const OFFSET: u8 = 4u8;
897 self.bits & (1 << OFFSET) != 0
898 }
899 # [ doc = "Bit 5 - Timer 7 reset" ]
900 pub fn tim7rst(&self) -> bool {
901 const OFFSET: u8 = 5u8;
902 self.bits & (1 << OFFSET) != 0
903 }
904 # [ doc = "Bit 11 - Window watchdog reset" ]
905 pub fn wwdgrst(&self) -> bool {
906 const OFFSET: u8 = 11u8;
907 self.bits & (1 << OFFSET) != 0
908 }
909 # [ doc = "Bit 14 - SPI2 reset" ]
910 pub fn spi2rst(&self) -> bool {
911 const OFFSET: u8 = 14u8;
912 self.bits & (1 << OFFSET) != 0
913 }
914 # [ doc = "Bit 15 - SPI3 reset" ]
915 pub fn spi3rst(&self) -> bool {
916 const OFFSET: u8 = 15u8;
917 self.bits & (1 << OFFSET) != 0
918 }
919 # [ doc = "Bit 17 - USART 2 reset" ]
920 pub fn usart2rst(&self) -> bool {
921 const OFFSET: u8 = 17u8;
922 self.bits & (1 << OFFSET) != 0
923 }
924 # [ doc = "Bit 18 - USART3 reset" ]
925 pub fn usart3rst(&self) -> bool {
926 const OFFSET: u8 = 18u8;
927 self.bits & (1 << OFFSET) != 0
928 }
929 # [ doc = "Bit 19 - UART 4 reset" ]
930 pub fn uart4rst(&self) -> bool {
931 const OFFSET: u8 = 19u8;
932 self.bits & (1 << OFFSET) != 0
933 }
934 # [ doc = "Bit 20 - UART 5 reset" ]
935 pub fn uart5rst(&self) -> bool {
936 const OFFSET: u8 = 20u8;
937 self.bits & (1 << OFFSET) != 0
938 }
939 # [ doc = "Bit 21 - I2C1 reset" ]
940 pub fn i2c1rst(&self) -> bool {
941 const OFFSET: u8 = 21u8;
942 self.bits & (1 << OFFSET) != 0
943 }
944 # [ doc = "Bit 22 - I2C2 reset" ]
945 pub fn i2c2rst(&self) -> bool {
946 const OFFSET: u8 = 22u8;
947 self.bits & (1 << OFFSET) != 0
948 }
949 # [ doc = "Bit 23 - USB reset" ]
950 pub fn usbrst(&self) -> bool {
951 const OFFSET: u8 = 23u8;
952 self.bits & (1 << OFFSET) != 0
953 }
954 # [ doc = "Bit 25 - CAN reset" ]
955 pub fn canrst(&self) -> bool {
956 const OFFSET: u8 = 25u8;
957 self.bits & (1 << OFFSET) != 0
958 }
959 # [ doc = "Bit 28 - Power interface reset" ]
960 pub fn pwrrst(&self) -> bool {
961 const OFFSET: u8 = 28u8;
962 self.bits & (1 << OFFSET) != 0
963 }
964 # [ doc = "Bit 29 - DAC interface reset" ]
965 pub fn dacrst(&self) -> bool {
966 const OFFSET: u8 = 29u8;
967 self.bits & (1 << OFFSET) != 0
968 }
969}
970
971# [ derive ( Clone , Copy ) ]
972# [ repr ( C ) ]
973pub struct Apb1rstrW {
974 bits: u32,
975}
976
977impl Apb1rstrW {
978 # [ doc = r" Reset value" ]
979 pub fn reset_value() -> Self {
980 Apb1rstrW { bits: 0 }
981 }
982 # [ doc = "Bit 0 - Timer 2 reset" ]
983 pub fn tim2rst(&mut self, value: bool) -> &mut Self {
984 const OFFSET: u8 = 0u8;
985 if value {
986 self.bits |= 1 << OFFSET;
987 } else {
988 self.bits &= !(1 << OFFSET);
989 }
990 self
991 }
992 # [ doc = "Bit 1 - Timer 3 reset" ]
993 pub fn tim3rst(&mut self, value: bool) -> &mut Self {
994 const OFFSET: u8 = 1u8;
995 if value {
996 self.bits |= 1 << OFFSET;
997 } else {
998 self.bits &= !(1 << OFFSET);
999 }
1000 self
1001 }
1002 # [ doc = "Bit 2 - Timer 14 reset" ]
1003 pub fn tim4rst(&mut self, value: bool) -> &mut Self {
1004 const OFFSET: u8 = 2u8;
1005 if value {
1006 self.bits |= 1 << OFFSET;
1007 } else {
1008 self.bits &= !(1 << OFFSET);
1009 }
1010 self
1011 }
1012 # [ doc = "Bit 4 - Timer 6 reset" ]
1013 pub fn tim6rst(&mut self, value: bool) -> &mut Self {
1014 const OFFSET: u8 = 4u8;
1015 if value {
1016 self.bits |= 1 << OFFSET;
1017 } else {
1018 self.bits &= !(1 << OFFSET);
1019 }
1020 self
1021 }
1022 # [ doc = "Bit 5 - Timer 7 reset" ]
1023 pub fn tim7rst(&mut self, value: bool) -> &mut Self {
1024 const OFFSET: u8 = 5u8;
1025 if value {
1026 self.bits |= 1 << OFFSET;
1027 } else {
1028 self.bits &= !(1 << OFFSET);
1029 }
1030 self
1031 }
1032 # [ doc = "Bit 11 - Window watchdog reset" ]
1033 pub fn wwdgrst(&mut self, value: bool) -> &mut Self {
1034 const OFFSET: u8 = 11u8;
1035 if value {
1036 self.bits |= 1 << OFFSET;
1037 } else {
1038 self.bits &= !(1 << OFFSET);
1039 }
1040 self
1041 }
1042 # [ doc = "Bit 14 - SPI2 reset" ]
1043 pub fn spi2rst(&mut self, value: bool) -> &mut Self {
1044 const OFFSET: u8 = 14u8;
1045 if value {
1046 self.bits |= 1 << OFFSET;
1047 } else {
1048 self.bits &= !(1 << OFFSET);
1049 }
1050 self
1051 }
1052 # [ doc = "Bit 15 - SPI3 reset" ]
1053 pub fn spi3rst(&mut self, value: bool) -> &mut Self {
1054 const OFFSET: u8 = 15u8;
1055 if value {
1056 self.bits |= 1 << OFFSET;
1057 } else {
1058 self.bits &= !(1 << OFFSET);
1059 }
1060 self
1061 }
1062 # [ doc = "Bit 17 - USART 2 reset" ]
1063 pub fn usart2rst(&mut self, value: bool) -> &mut Self {
1064 const OFFSET: u8 = 17u8;
1065 if value {
1066 self.bits |= 1 << OFFSET;
1067 } else {
1068 self.bits &= !(1 << OFFSET);
1069 }
1070 self
1071 }
1072 # [ doc = "Bit 18 - USART3 reset" ]
1073 pub fn usart3rst(&mut self, value: bool) -> &mut Self {
1074 const OFFSET: u8 = 18u8;
1075 if value {
1076 self.bits |= 1 << OFFSET;
1077 } else {
1078 self.bits &= !(1 << OFFSET);
1079 }
1080 self
1081 }
1082 # [ doc = "Bit 19 - UART 4 reset" ]
1083 pub fn uart4rst(&mut self, value: bool) -> &mut Self {
1084 const OFFSET: u8 = 19u8;
1085 if value {
1086 self.bits |= 1 << OFFSET;
1087 } else {
1088 self.bits &= !(1 << OFFSET);
1089 }
1090 self
1091 }
1092 # [ doc = "Bit 20 - UART 5 reset" ]
1093 pub fn uart5rst(&mut self, value: bool) -> &mut Self {
1094 const OFFSET: u8 = 20u8;
1095 if value {
1096 self.bits |= 1 << OFFSET;
1097 } else {
1098 self.bits &= !(1 << OFFSET);
1099 }
1100 self
1101 }
1102 # [ doc = "Bit 21 - I2C1 reset" ]
1103 pub fn i2c1rst(&mut self, value: bool) -> &mut Self {
1104 const OFFSET: u8 = 21u8;
1105 if value {
1106 self.bits |= 1 << OFFSET;
1107 } else {
1108 self.bits &= !(1 << OFFSET);
1109 }
1110 self
1111 }
1112 # [ doc = "Bit 22 - I2C2 reset" ]
1113 pub fn i2c2rst(&mut self, value: bool) -> &mut Self {
1114 const OFFSET: u8 = 22u8;
1115 if value {
1116 self.bits |= 1 << OFFSET;
1117 } else {
1118 self.bits &= !(1 << OFFSET);
1119 }
1120 self
1121 }
1122 # [ doc = "Bit 23 - USB reset" ]
1123 pub fn usbrst(&mut self, value: bool) -> &mut Self {
1124 const OFFSET: u8 = 23u8;
1125 if value {
1126 self.bits |= 1 << OFFSET;
1127 } else {
1128 self.bits &= !(1 << OFFSET);
1129 }
1130 self
1131 }
1132 # [ doc = "Bit 25 - CAN reset" ]
1133 pub fn canrst(&mut self, value: bool) -> &mut Self {
1134 const OFFSET: u8 = 25u8;
1135 if value {
1136 self.bits |= 1 << OFFSET;
1137 } else {
1138 self.bits &= !(1 << OFFSET);
1139 }
1140 self
1141 }
1142 # [ doc = "Bit 28 - Power interface reset" ]
1143 pub fn pwrrst(&mut self, value: bool) -> &mut Self {
1144 const OFFSET: u8 = 28u8;
1145 if value {
1146 self.bits |= 1 << OFFSET;
1147 } else {
1148 self.bits &= !(1 << OFFSET);
1149 }
1150 self
1151 }
1152 # [ doc = "Bit 29 - DAC interface reset" ]
1153 pub fn dacrst(&mut self, value: bool) -> &mut Self {
1154 const OFFSET: u8 = 29u8;
1155 if value {
1156 self.bits |= 1 << OFFSET;
1157 } else {
1158 self.bits &= !(1 << OFFSET);
1159 }
1160 self
1161 }
1162}
1163
1164# [ repr ( C ) ]
1165pub struct Ahbenr {
1166 register: ::volatile_register::RW<u32>,
1167}
1168
1169impl Ahbenr {
1170 pub fn read_bits(&self) -> u32 {
1171 self.register.read()
1172 }
1173 pub unsafe fn modify_bits<F>(&mut self, f: F)
1174 where F: FnOnce(&mut u32)
1175 {
1176 let mut bits = self.register.read();
1177 f(&mut bits);
1178 self.register.write(bits);
1179 }
1180 pub unsafe fn write_bits(&mut self, bits: u32) {
1181 self.register.write(bits);
1182 }
1183 pub fn modify<F>(&mut self, f: F)
1184 where for<'w> F: FnOnce(&AhbenrR, &'w mut AhbenrW) -> &'w mut AhbenrW
1185 {
1186 let bits = self.register.read();
1187 let r = AhbenrR { bits: bits };
1188 let mut w = AhbenrW { bits: bits };
1189 f(&r, &mut w);
1190 self.register.write(w.bits);
1191 }
1192 pub fn read(&self) -> AhbenrR {
1193 AhbenrR { bits: self.register.read() }
1194 }
1195 pub fn write<F>(&mut self, f: F)
1196 where F: FnOnce(&mut AhbenrW) -> &mut AhbenrW
1197 {
1198 let mut w = AhbenrW::reset_value();
1199 f(&mut w);
1200 self.register.write(w.bits);
1201 }
1202}
1203
1204# [ derive ( Clone , Copy ) ]
1205# [ repr ( C ) ]
1206pub struct AhbenrR {
1207 bits: u32,
1208}
1209
1210impl AhbenrR {
1211 # [ doc = "Bit 0 - DMA1 clock enable" ]
1212 pub fn dmaen(&self) -> bool {
1213 const OFFSET: u8 = 0u8;
1214 self.bits & (1 << OFFSET) != 0
1215 }
1216 # [ doc = "Bit 1 - DMA2 clock enable" ]
1217 pub fn dma2en(&self) -> bool {
1218 const OFFSET: u8 = 1u8;
1219 self.bits & (1 << OFFSET) != 0
1220 }
1221 # [ doc = "Bit 2 - SRAM interface clock enable" ]
1222 pub fn sramen(&self) -> bool {
1223 const OFFSET: u8 = 2u8;
1224 self.bits & (1 << OFFSET) != 0
1225 }
1226 # [ doc = "Bit 4 - FLITF clock enable" ]
1227 pub fn flitfen(&self) -> bool {
1228 const OFFSET: u8 = 4u8;
1229 self.bits & (1 << OFFSET) != 0
1230 }
1231 # [ doc = "Bit 6 - CRC clock enable" ]
1232 pub fn crcen(&self) -> bool {
1233 const OFFSET: u8 = 6u8;
1234 self.bits & (1 << OFFSET) != 0
1235 }
1236 # [ doc = "Bit 17 - I/O port A clock enable" ]
1237 pub fn iopaen(&self) -> bool {
1238 const OFFSET: u8 = 17u8;
1239 self.bits & (1 << OFFSET) != 0
1240 }
1241 # [ doc = "Bit 18 - I/O port B clock enable" ]
1242 pub fn iopben(&self) -> bool {
1243 const OFFSET: u8 = 18u8;
1244 self.bits & (1 << OFFSET) != 0
1245 }
1246 # [ doc = "Bit 19 - I/O port C clock enable" ]
1247 pub fn iopcen(&self) -> bool {
1248 const OFFSET: u8 = 19u8;
1249 self.bits & (1 << OFFSET) != 0
1250 }
1251 # [ doc = "Bit 20 - I/O port D clock enable" ]
1252 pub fn iopden(&self) -> bool {
1253 const OFFSET: u8 = 20u8;
1254 self.bits & (1 << OFFSET) != 0
1255 }
1256 # [ doc = "Bit 21 - I/O port E clock enable" ]
1257 pub fn iopeen(&self) -> bool {
1258 const OFFSET: u8 = 21u8;
1259 self.bits & (1 << OFFSET) != 0
1260 }
1261 # [ doc = "Bit 22 - I/O port F clock enable" ]
1262 pub fn iopfen(&self) -> bool {
1263 const OFFSET: u8 = 22u8;
1264 self.bits & (1 << OFFSET) != 0
1265 }
1266 # [ doc = "Bit 24 - Touch sensing controller clock enable" ]
1267 pub fn tscen(&self) -> bool {
1268 const OFFSET: u8 = 24u8;
1269 self.bits & (1 << OFFSET) != 0
1270 }
1271 # [ doc = "Bit 28 - ADC1 and ADC2 clock enable" ]
1272 pub fn adc12en(&self) -> bool {
1273 const OFFSET: u8 = 28u8;
1274 self.bits & (1 << OFFSET) != 0
1275 }
1276 # [ doc = "Bit 29 - ADC3 and ADC4 clock enable" ]
1277 pub fn adc34en(&self) -> bool {
1278 const OFFSET: u8 = 29u8;
1279 self.bits & (1 << OFFSET) != 0
1280 }
1281}
1282
1283# [ derive ( Clone , Copy ) ]
1284# [ repr ( C ) ]
1285pub struct AhbenrW {
1286 bits: u32,
1287}
1288
1289impl AhbenrW {
1290 # [ doc = r" Reset value" ]
1291 pub fn reset_value() -> Self {
1292 AhbenrW { bits: 20 }
1293 }
1294 # [ doc = "Bit 0 - DMA1 clock enable" ]
1295 pub fn dmaen(&mut self, value: bool) -> &mut Self {
1296 const OFFSET: u8 = 0u8;
1297 if value {
1298 self.bits |= 1 << OFFSET;
1299 } else {
1300 self.bits &= !(1 << OFFSET);
1301 }
1302 self
1303 }
1304 # [ doc = "Bit 1 - DMA2 clock enable" ]
1305 pub fn dma2en(&mut self, value: bool) -> &mut Self {
1306 const OFFSET: u8 = 1u8;
1307 if value {
1308 self.bits |= 1 << OFFSET;
1309 } else {
1310 self.bits &= !(1 << OFFSET);
1311 }
1312 self
1313 }
1314 # [ doc = "Bit 2 - SRAM interface clock enable" ]
1315 pub fn sramen(&mut self, value: bool) -> &mut Self {
1316 const OFFSET: u8 = 2u8;
1317 if value {
1318 self.bits |= 1 << OFFSET;
1319 } else {
1320 self.bits &= !(1 << OFFSET);
1321 }
1322 self
1323 }
1324 # [ doc = "Bit 4 - FLITF clock enable" ]
1325 pub fn flitfen(&mut self, value: bool) -> &mut Self {
1326 const OFFSET: u8 = 4u8;
1327 if value {
1328 self.bits |= 1 << OFFSET;
1329 } else {
1330 self.bits &= !(1 << OFFSET);
1331 }
1332 self
1333 }
1334 # [ doc = "Bit 6 - CRC clock enable" ]
1335 pub fn crcen(&mut self, value: bool) -> &mut Self {
1336 const OFFSET: u8 = 6u8;
1337 if value {
1338 self.bits |= 1 << OFFSET;
1339 } else {
1340 self.bits &= !(1 << OFFSET);
1341 }
1342 self
1343 }
1344 # [ doc = "Bit 17 - I/O port A clock enable" ]
1345 pub fn iopaen(&mut self, value: bool) -> &mut Self {
1346 const OFFSET: u8 = 17u8;
1347 if value {
1348 self.bits |= 1 << OFFSET;
1349 } else {
1350 self.bits &= !(1 << OFFSET);
1351 }
1352 self
1353 }
1354 # [ doc = "Bit 18 - I/O port B clock enable" ]
1355 pub fn iopben(&mut self, value: bool) -> &mut Self {
1356 const OFFSET: u8 = 18u8;
1357 if value {
1358 self.bits |= 1 << OFFSET;
1359 } else {
1360 self.bits &= !(1 << OFFSET);
1361 }
1362 self
1363 }
1364 # [ doc = "Bit 19 - I/O port C clock enable" ]
1365 pub fn iopcen(&mut self, value: bool) -> &mut Self {
1366 const OFFSET: u8 = 19u8;
1367 if value {
1368 self.bits |= 1 << OFFSET;
1369 } else {
1370 self.bits &= !(1 << OFFSET);
1371 }
1372 self
1373 }
1374 # [ doc = "Bit 20 - I/O port D clock enable" ]
1375 pub fn iopden(&mut self, value: bool) -> &mut Self {
1376 const OFFSET: u8 = 20u8;
1377 if value {
1378 self.bits |= 1 << OFFSET;
1379 } else {
1380 self.bits &= !(1 << OFFSET);
1381 }
1382 self
1383 }
1384 # [ doc = "Bit 21 - I/O port E clock enable" ]
1385 pub fn iopeen(&mut self, value: bool) -> &mut Self {
1386 const OFFSET: u8 = 21u8;
1387 if value {
1388 self.bits |= 1 << OFFSET;
1389 } else {
1390 self.bits &= !(1 << OFFSET);
1391 }
1392 self
1393 }
1394 # [ doc = "Bit 22 - I/O port F clock enable" ]
1395 pub fn iopfen(&mut self, value: bool) -> &mut Self {
1396 const OFFSET: u8 = 22u8;
1397 if value {
1398 self.bits |= 1 << OFFSET;
1399 } else {
1400 self.bits &= !(1 << OFFSET);
1401 }
1402 self
1403 }
1404 # [ doc = "Bit 24 - Touch sensing controller clock enable" ]
1405 pub fn tscen(&mut self, value: bool) -> &mut Self {
1406 const OFFSET: u8 = 24u8;
1407 if value {
1408 self.bits |= 1 << OFFSET;
1409 } else {
1410 self.bits &= !(1 << OFFSET);
1411 }
1412 self
1413 }
1414 # [ doc = "Bit 28 - ADC1 and ADC2 clock enable" ]
1415 pub fn adc12en(&mut self, value: bool) -> &mut Self {
1416 const OFFSET: u8 = 28u8;
1417 if value {
1418 self.bits |= 1 << OFFSET;
1419 } else {
1420 self.bits &= !(1 << OFFSET);
1421 }
1422 self
1423 }
1424 # [ doc = "Bit 29 - ADC3 and ADC4 clock enable" ]
1425 pub fn adc34en(&mut self, value: bool) -> &mut Self {
1426 const OFFSET: u8 = 29u8;
1427 if value {
1428 self.bits |= 1 << OFFSET;
1429 } else {
1430 self.bits &= !(1 << OFFSET);
1431 }
1432 self
1433 }
1434}
1435
1436# [ repr ( C ) ]
1437pub struct Apb2enr {
1438 register: ::volatile_register::RW<u32>,
1439}
1440
1441impl Apb2enr {
1442 pub fn read_bits(&self) -> u32 {
1443 self.register.read()
1444 }
1445 pub unsafe fn modify_bits<F>(&mut self, f: F)
1446 where F: FnOnce(&mut u32)
1447 {
1448 let mut bits = self.register.read();
1449 f(&mut bits);
1450 self.register.write(bits);
1451 }
1452 pub unsafe fn write_bits(&mut self, bits: u32) {
1453 self.register.write(bits);
1454 }
1455 pub fn modify<F>(&mut self, f: F)
1456 where for<'w> F: FnOnce(&Apb2enrR, &'w mut Apb2enrW) -> &'w mut Apb2enrW
1457 {
1458 let bits = self.register.read();
1459 let r = Apb2enrR { bits: bits };
1460 let mut w = Apb2enrW { bits: bits };
1461 f(&r, &mut w);
1462 self.register.write(w.bits);
1463 }
1464 pub fn read(&self) -> Apb2enrR {
1465 Apb2enrR { bits: self.register.read() }
1466 }
1467 pub fn write<F>(&mut self, f: F)
1468 where F: FnOnce(&mut Apb2enrW) -> &mut Apb2enrW
1469 {
1470 let mut w = Apb2enrW::reset_value();
1471 f(&mut w);
1472 self.register.write(w.bits);
1473 }
1474}
1475
1476# [ derive ( Clone , Copy ) ]
1477# [ repr ( C ) ]
1478pub struct Apb2enrR {
1479 bits: u32,
1480}
1481
1482impl Apb2enrR {
1483 # [ doc = "Bit 0 - SYSCFG clock enable" ]
1484 pub fn syscfgen(&self) -> bool {
1485 const OFFSET: u8 = 0u8;
1486 self.bits & (1 << OFFSET) != 0
1487 }
1488 # [ doc = "Bit 11 - TIM1 Timer clock enable" ]
1489 pub fn tim1en(&self) -> bool {
1490 const OFFSET: u8 = 11u8;
1491 self.bits & (1 << OFFSET) != 0
1492 }
1493 # [ doc = "Bit 12 - SPI 1 clock enable" ]
1494 pub fn spi1en(&self) -> bool {
1495 const OFFSET: u8 = 12u8;
1496 self.bits & (1 << OFFSET) != 0
1497 }
1498 # [ doc = "Bit 13 - TIM8 Timer clock enable" ]
1499 pub fn tim8en(&self) -> bool {
1500 const OFFSET: u8 = 13u8;
1501 self.bits & (1 << OFFSET) != 0
1502 }
1503 # [ doc = "Bit 14 - USART1 clock enable" ]
1504 pub fn usart1en(&self) -> bool {
1505 const OFFSET: u8 = 14u8;
1506 self.bits & (1 << OFFSET) != 0
1507 }
1508 # [ doc = "Bit 16 - TIM15 timer clock enable" ]
1509 pub fn tim15en(&self) -> bool {
1510 const OFFSET: u8 = 16u8;
1511 self.bits & (1 << OFFSET) != 0
1512 }
1513 # [ doc = "Bit 17 - TIM16 timer clock enable" ]
1514 pub fn tim16en(&self) -> bool {
1515 const OFFSET: u8 = 17u8;
1516 self.bits & (1 << OFFSET) != 0
1517 }
1518 # [ doc = "Bit 18 - TIM17 timer clock enable" ]
1519 pub fn tim17en(&self) -> bool {
1520 const OFFSET: u8 = 18u8;
1521 self.bits & (1 << OFFSET) != 0
1522 }
1523}
1524
1525# [ derive ( Clone , Copy ) ]
1526# [ repr ( C ) ]
1527pub struct Apb2enrW {
1528 bits: u32,
1529}
1530
1531impl Apb2enrW {
1532 # [ doc = r" Reset value" ]
1533 pub fn reset_value() -> Self {
1534 Apb2enrW { bits: 0 }
1535 }
1536 # [ doc = "Bit 0 - SYSCFG clock enable" ]
1537 pub fn syscfgen(&mut self, value: bool) -> &mut Self {
1538 const OFFSET: u8 = 0u8;
1539 if value {
1540 self.bits |= 1 << OFFSET;
1541 } else {
1542 self.bits &= !(1 << OFFSET);
1543 }
1544 self
1545 }
1546 # [ doc = "Bit 11 - TIM1 Timer clock enable" ]
1547 pub fn tim1en(&mut self, value: bool) -> &mut Self {
1548 const OFFSET: u8 = 11u8;
1549 if value {
1550 self.bits |= 1 << OFFSET;
1551 } else {
1552 self.bits &= !(1 << OFFSET);
1553 }
1554 self
1555 }
1556 # [ doc = "Bit 12 - SPI 1 clock enable" ]
1557 pub fn spi1en(&mut self, value: bool) -> &mut Self {
1558 const OFFSET: u8 = 12u8;
1559 if value {
1560 self.bits |= 1 << OFFSET;
1561 } else {
1562 self.bits &= !(1 << OFFSET);
1563 }
1564 self
1565 }
1566 # [ doc = "Bit 13 - TIM8 Timer clock enable" ]
1567 pub fn tim8en(&mut self, value: bool) -> &mut Self {
1568 const OFFSET: u8 = 13u8;
1569 if value {
1570 self.bits |= 1 << OFFSET;
1571 } else {
1572 self.bits &= !(1 << OFFSET);
1573 }
1574 self
1575 }
1576 # [ doc = "Bit 14 - USART1 clock enable" ]
1577 pub fn usart1en(&mut self, value: bool) -> &mut Self {
1578 const OFFSET: u8 = 14u8;
1579 if value {
1580 self.bits |= 1 << OFFSET;
1581 } else {
1582 self.bits &= !(1 << OFFSET);
1583 }
1584 self
1585 }
1586 # [ doc = "Bit 16 - TIM15 timer clock enable" ]
1587 pub fn tim15en(&mut self, value: bool) -> &mut Self {
1588 const OFFSET: u8 = 16u8;
1589 if value {
1590 self.bits |= 1 << OFFSET;
1591 } else {
1592 self.bits &= !(1 << OFFSET);
1593 }
1594 self
1595 }
1596 # [ doc = "Bit 17 - TIM16 timer clock enable" ]
1597 pub fn tim16en(&mut self, value: bool) -> &mut Self {
1598 const OFFSET: u8 = 17u8;
1599 if value {
1600 self.bits |= 1 << OFFSET;
1601 } else {
1602 self.bits &= !(1 << OFFSET);
1603 }
1604 self
1605 }
1606 # [ doc = "Bit 18 - TIM17 timer clock enable" ]
1607 pub fn tim17en(&mut self, value: bool) -> &mut Self {
1608 const OFFSET: u8 = 18u8;
1609 if value {
1610 self.bits |= 1 << OFFSET;
1611 } else {
1612 self.bits &= !(1 << OFFSET);
1613 }
1614 self
1615 }
1616}
1617
1618# [ repr ( C ) ]
1619pub struct Apb1enr {
1620 register: ::volatile_register::RW<u32>,
1621}
1622
1623impl Apb1enr {
1624 pub fn read_bits(&self) -> u32 {
1625 self.register.read()
1626 }
1627 pub unsafe fn modify_bits<F>(&mut self, f: F)
1628 where F: FnOnce(&mut u32)
1629 {
1630 let mut bits = self.register.read();
1631 f(&mut bits);
1632 self.register.write(bits);
1633 }
1634 pub unsafe fn write_bits(&mut self, bits: u32) {
1635 self.register.write(bits);
1636 }
1637 pub fn modify<F>(&mut self, f: F)
1638 where for<'w> F: FnOnce(&Apb1enrR, &'w mut Apb1enrW) -> &'w mut Apb1enrW
1639 {
1640 let bits = self.register.read();
1641 let r = Apb1enrR { bits: bits };
1642 let mut w = Apb1enrW { bits: bits };
1643 f(&r, &mut w);
1644 self.register.write(w.bits);
1645 }
1646 pub fn read(&self) -> Apb1enrR {
1647 Apb1enrR { bits: self.register.read() }
1648 }
1649 pub fn write<F>(&mut self, f: F)
1650 where F: FnOnce(&mut Apb1enrW) -> &mut Apb1enrW
1651 {
1652 let mut w = Apb1enrW::reset_value();
1653 f(&mut w);
1654 self.register.write(w.bits);
1655 }
1656}
1657
1658# [ derive ( Clone , Copy ) ]
1659# [ repr ( C ) ]
1660pub struct Apb1enrR {
1661 bits: u32,
1662}
1663
1664impl Apb1enrR {
1665 # [ doc = "Bit 0 - Timer 2 clock enable" ]
1666 pub fn tim2en(&self) -> bool {
1667 const OFFSET: u8 = 0u8;
1668 self.bits & (1 << OFFSET) != 0
1669 }
1670 # [ doc = "Bit 1 - Timer 3 clock enable" ]
1671 pub fn tim3en(&self) -> bool {
1672 const OFFSET: u8 = 1u8;
1673 self.bits & (1 << OFFSET) != 0
1674 }
1675 # [ doc = "Bit 2 - Timer 4 clock enable" ]
1676 pub fn tim4en(&self) -> bool {
1677 const OFFSET: u8 = 2u8;
1678 self.bits & (1 << OFFSET) != 0
1679 }
1680 # [ doc = "Bit 4 - Timer 6 clock enable" ]
1681 pub fn tim6en(&self) -> bool {
1682 const OFFSET: u8 = 4u8;
1683 self.bits & (1 << OFFSET) != 0
1684 }
1685 # [ doc = "Bit 5 - Timer 7 clock enable" ]
1686 pub fn tim7en(&self) -> bool {
1687 const OFFSET: u8 = 5u8;
1688 self.bits & (1 << OFFSET) != 0
1689 }
1690 # [ doc = "Bit 11 - Window watchdog clock enable" ]
1691 pub fn wwdgen(&self) -> bool {
1692 const OFFSET: u8 = 11u8;
1693 self.bits & (1 << OFFSET) != 0
1694 }
1695 # [ doc = "Bit 14 - SPI 2 clock enable" ]
1696 pub fn spi2en(&self) -> bool {
1697 const OFFSET: u8 = 14u8;
1698 self.bits & (1 << OFFSET) != 0
1699 }
1700 # [ doc = "Bit 15 - SPI 3 clock enable" ]
1701 pub fn spi3en(&self) -> bool {
1702 const OFFSET: u8 = 15u8;
1703 self.bits & (1 << OFFSET) != 0
1704 }
1705 # [ doc = "Bit 17 - USART 2 clock enable" ]
1706 pub fn usart2en(&self) -> bool {
1707 const OFFSET: u8 = 17u8;
1708 self.bits & (1 << OFFSET) != 0
1709 }
1710 # [ doc = "Bit 21 - I2C 1 clock enable" ]
1711 pub fn i2c1en(&self) -> bool {
1712 const OFFSET: u8 = 21u8;
1713 self.bits & (1 << OFFSET) != 0
1714 }
1715 # [ doc = "Bit 22 - I2C 2 clock enable" ]
1716 pub fn i2c2en(&self) -> bool {
1717 const OFFSET: u8 = 22u8;
1718 self.bits & (1 << OFFSET) != 0
1719 }
1720 # [ doc = "Bit 23 - USB clock enable" ]
1721 pub fn usben(&self) -> bool {
1722 const OFFSET: u8 = 23u8;
1723 self.bits & (1 << OFFSET) != 0
1724 }
1725 # [ doc = "Bit 25 - CAN clock enable" ]
1726 pub fn canen(&self) -> bool {
1727 const OFFSET: u8 = 25u8;
1728 self.bits & (1 << OFFSET) != 0
1729 }
1730 # [ doc = "Bit 28 - Power interface clock enable" ]
1731 pub fn pwren(&self) -> bool {
1732 const OFFSET: u8 = 28u8;
1733 self.bits & (1 << OFFSET) != 0
1734 }
1735 # [ doc = "Bit 29 - DAC interface clock enable" ]
1736 pub fn dacen(&self) -> bool {
1737 const OFFSET: u8 = 29u8;
1738 self.bits & (1 << OFFSET) != 0
1739 }
1740}
1741
1742# [ derive ( Clone , Copy ) ]
1743# [ repr ( C ) ]
1744pub struct Apb1enrW {
1745 bits: u32,
1746}
1747
1748impl Apb1enrW {
1749 # [ doc = r" Reset value" ]
1750 pub fn reset_value() -> Self {
1751 Apb1enrW { bits: 0 }
1752 }
1753 # [ doc = "Bit 0 - Timer 2 clock enable" ]
1754 pub fn tim2en(&mut self, value: bool) -> &mut Self {
1755 const OFFSET: u8 = 0u8;
1756 if value {
1757 self.bits |= 1 << OFFSET;
1758 } else {
1759 self.bits &= !(1 << OFFSET);
1760 }
1761 self
1762 }
1763 # [ doc = "Bit 1 - Timer 3 clock enable" ]
1764 pub fn tim3en(&mut self, value: bool) -> &mut Self {
1765 const OFFSET: u8 = 1u8;
1766 if value {
1767 self.bits |= 1 << OFFSET;
1768 } else {
1769 self.bits &= !(1 << OFFSET);
1770 }
1771 self
1772 }
1773 # [ doc = "Bit 2 - Timer 4 clock enable" ]
1774 pub fn tim4en(&mut self, value: bool) -> &mut Self {
1775 const OFFSET: u8 = 2u8;
1776 if value {
1777 self.bits |= 1 << OFFSET;
1778 } else {
1779 self.bits &= !(1 << OFFSET);
1780 }
1781 self
1782 }
1783 # [ doc = "Bit 4 - Timer 6 clock enable" ]
1784 pub fn tim6en(&mut self, value: bool) -> &mut Self {
1785 const OFFSET: u8 = 4u8;
1786 if value {
1787 self.bits |= 1 << OFFSET;
1788 } else {
1789 self.bits &= !(1 << OFFSET);
1790 }
1791 self
1792 }
1793 # [ doc = "Bit 5 - Timer 7 clock enable" ]
1794 pub fn tim7en(&mut self, value: bool) -> &mut Self {
1795 const OFFSET: u8 = 5u8;
1796 if value {
1797 self.bits |= 1 << OFFSET;
1798 } else {
1799 self.bits &= !(1 << OFFSET);
1800 }
1801 self
1802 }
1803 # [ doc = "Bit 11 - Window watchdog clock enable" ]
1804 pub fn wwdgen(&mut self, value: bool) -> &mut Self {
1805 const OFFSET: u8 = 11u8;
1806 if value {
1807 self.bits |= 1 << OFFSET;
1808 } else {
1809 self.bits &= !(1 << OFFSET);
1810 }
1811 self
1812 }
1813 # [ doc = "Bit 14 - SPI 2 clock enable" ]
1814 pub fn spi2en(&mut self, value: bool) -> &mut Self {
1815 const OFFSET: u8 = 14u8;
1816 if value {
1817 self.bits |= 1 << OFFSET;
1818 } else {
1819 self.bits &= !(1 << OFFSET);
1820 }
1821 self
1822 }
1823 # [ doc = "Bit 15 - SPI 3 clock enable" ]
1824 pub fn spi3en(&mut self, value: bool) -> &mut Self {
1825 const OFFSET: u8 = 15u8;
1826 if value {
1827 self.bits |= 1 << OFFSET;
1828 } else {
1829 self.bits &= !(1 << OFFSET);
1830 }
1831 self
1832 }
1833 # [ doc = "Bit 17 - USART 2 clock enable" ]
1834 pub fn usart2en(&mut self, value: bool) -> &mut Self {
1835 const OFFSET: u8 = 17u8;
1836 if value {
1837 self.bits |= 1 << OFFSET;
1838 } else {
1839 self.bits &= !(1 << OFFSET);
1840 }
1841 self
1842 }
1843 # [ doc = "Bit 21 - I2C 1 clock enable" ]
1844 pub fn i2c1en(&mut self, value: bool) -> &mut Self {
1845 const OFFSET: u8 = 21u8;
1846 if value {
1847 self.bits |= 1 << OFFSET;
1848 } else {
1849 self.bits &= !(1 << OFFSET);
1850 }
1851 self
1852 }
1853 # [ doc = "Bit 22 - I2C 2 clock enable" ]
1854 pub fn i2c2en(&mut self, value: bool) -> &mut Self {
1855 const OFFSET: u8 = 22u8;
1856 if value {
1857 self.bits |= 1 << OFFSET;
1858 } else {
1859 self.bits &= !(1 << OFFSET);
1860 }
1861 self
1862 }
1863 # [ doc = "Bit 23 - USB clock enable" ]
1864 pub fn usben(&mut self, value: bool) -> &mut Self {
1865 const OFFSET: u8 = 23u8;
1866 if value {
1867 self.bits |= 1 << OFFSET;
1868 } else {
1869 self.bits &= !(1 << OFFSET);
1870 }
1871 self
1872 }
1873 # [ doc = "Bit 25 - CAN clock enable" ]
1874 pub fn canen(&mut self, value: bool) -> &mut Self {
1875 const OFFSET: u8 = 25u8;
1876 if value {
1877 self.bits |= 1 << OFFSET;
1878 } else {
1879 self.bits &= !(1 << OFFSET);
1880 }
1881 self
1882 }
1883 # [ doc = "Bit 28 - Power interface clock enable" ]
1884 pub fn pwren(&mut self, value: bool) -> &mut Self {
1885 const OFFSET: u8 = 28u8;
1886 if value {
1887 self.bits |= 1 << OFFSET;
1888 } else {
1889 self.bits &= !(1 << OFFSET);
1890 }
1891 self
1892 }
1893 # [ doc = "Bit 29 - DAC interface clock enable" ]
1894 pub fn dacen(&mut self, value: bool) -> &mut Self {
1895 const OFFSET: u8 = 29u8;
1896 if value {
1897 self.bits |= 1 << OFFSET;
1898 } else {
1899 self.bits &= !(1 << OFFSET);
1900 }
1901 self
1902 }
1903}
1904
1905# [ repr ( C ) ]
1906pub struct Bdcr {
1907 register: ::volatile_register::RW<u32>,
1908}
1909
1910impl Bdcr {
1911 pub fn read_bits(&self) -> u32 {
1912 self.register.read()
1913 }
1914 pub unsafe fn modify_bits<F>(&mut self, f: F)
1915 where F: FnOnce(&mut u32)
1916 {
1917 let mut bits = self.register.read();
1918 f(&mut bits);
1919 self.register.write(bits);
1920 }
1921 pub unsafe fn write_bits(&mut self, bits: u32) {
1922 self.register.write(bits);
1923 }
1924 pub fn modify<F>(&mut self, f: F)
1925 where for<'w> F: FnOnce(&BdcrR, &'w mut BdcrW) -> &'w mut BdcrW
1926 {
1927 let bits = self.register.read();
1928 let r = BdcrR { bits: bits };
1929 let mut w = BdcrW { bits: bits };
1930 f(&r, &mut w);
1931 self.register.write(w.bits);
1932 }
1933 pub fn read(&self) -> BdcrR {
1934 BdcrR { bits: self.register.read() }
1935 }
1936 pub fn write<F>(&mut self, f: F)
1937 where F: FnOnce(&mut BdcrW) -> &mut BdcrW
1938 {
1939 let mut w = BdcrW::reset_value();
1940 f(&mut w);
1941 self.register.write(w.bits);
1942 }
1943}
1944
1945# [ derive ( Clone , Copy ) ]
1946# [ repr ( C ) ]
1947pub struct BdcrR {
1948 bits: u32,
1949}
1950
1951impl BdcrR {
1952 # [ doc = "Bit 0 - External Low Speed oscillator enable" ]
1953 pub fn lseon(&self) -> bool {
1954 const OFFSET: u8 = 0u8;
1955 self.bits & (1 << OFFSET) != 0
1956 }
1957 # [ doc = "Bit 1 - External Low Speed oscillator ready" ]
1958 pub fn lserdy(&self) -> bool {
1959 const OFFSET: u8 = 1u8;
1960 self.bits & (1 << OFFSET) != 0
1961 }
1962 # [ doc = "Bit 2 - External Low Speed oscillator bypass" ]
1963 pub fn lsebyp(&self) -> bool {
1964 const OFFSET: u8 = 2u8;
1965 self.bits & (1 << OFFSET) != 0
1966 }
1967 # [ doc = "Bits 3:4 - LSE oscillator drive capability" ]
1968 pub fn lsedrv(&self) -> u8 {
1969 const MASK: u32 = 3;
1970 const OFFSET: u8 = 3u8;
1971 ((self.bits >> OFFSET) & MASK) as u8
1972 }
1973 # [ doc = "Bits 8:9 - RTC clock source selection" ]
1974 pub fn rtcsel(&self) -> u8 {
1975 const MASK: u32 = 3;
1976 const OFFSET: u8 = 8u8;
1977 ((self.bits >> OFFSET) & MASK) as u8
1978 }
1979 # [ doc = "Bit 15 - RTC clock enable" ]
1980 pub fn rtcen(&self) -> bool {
1981 const OFFSET: u8 = 15u8;
1982 self.bits & (1 << OFFSET) != 0
1983 }
1984 # [ doc = "Bit 16 - Backup domain software reset" ]
1985 pub fn bdrst(&self) -> bool {
1986 const OFFSET: u8 = 16u8;
1987 self.bits & (1 << OFFSET) != 0
1988 }
1989}
1990
1991# [ derive ( Clone , Copy ) ]
1992# [ repr ( C ) ]
1993pub struct BdcrW {
1994 bits: u32,
1995}
1996
1997impl BdcrW {
1998 # [ doc = r" Reset value" ]
1999 pub fn reset_value() -> Self {
2000 BdcrW { bits: 0 }
2001 }
2002 # [ doc = "Bit 0 - External Low Speed oscillator enable" ]
2003 pub fn lseon(&mut self, value: bool) -> &mut Self {
2004 const OFFSET: u8 = 0u8;
2005 if value {
2006 self.bits |= 1 << OFFSET;
2007 } else {
2008 self.bits &= !(1 << OFFSET);
2009 }
2010 self
2011 }
2012 # [ doc = "Bit 2 - External Low Speed oscillator bypass" ]
2013 pub fn lsebyp(&mut self, value: bool) -> &mut Self {
2014 const OFFSET: u8 = 2u8;
2015 if value {
2016 self.bits |= 1 << OFFSET;
2017 } else {
2018 self.bits &= !(1 << OFFSET);
2019 }
2020 self
2021 }
2022 # [ doc = "Bits 3:4 - LSE oscillator drive capability" ]
2023 pub fn lsedrv(&mut self, value: u8) -> &mut Self {
2024 const OFFSET: u8 = 3u8;
2025 const MASK: u8 = 3;
2026 self.bits &= !((MASK as u32) << OFFSET);
2027 self.bits |= ((value & MASK) as u32) << OFFSET;
2028 self
2029 }
2030 # [ doc = "Bits 8:9 - RTC clock source selection" ]
2031 pub fn rtcsel(&mut self, value: u8) -> &mut Self {
2032 const OFFSET: u8 = 8u8;
2033 const MASK: u8 = 3;
2034 self.bits &= !((MASK as u32) << OFFSET);
2035 self.bits |= ((value & MASK) as u32) << OFFSET;
2036 self
2037 }
2038 # [ doc = "Bit 15 - RTC clock enable" ]
2039 pub fn rtcen(&mut self, value: bool) -> &mut Self {
2040 const OFFSET: u8 = 15u8;
2041 if value {
2042 self.bits |= 1 << OFFSET;
2043 } else {
2044 self.bits &= !(1 << OFFSET);
2045 }
2046 self
2047 }
2048 # [ doc = "Bit 16 - Backup domain software reset" ]
2049 pub fn bdrst(&mut self, value: bool) -> &mut Self {
2050 const OFFSET: u8 = 16u8;
2051 if value {
2052 self.bits |= 1 << OFFSET;
2053 } else {
2054 self.bits &= !(1 << OFFSET);
2055 }
2056 self
2057 }
2058}
2059
2060# [ repr ( C ) ]
2061pub struct Csr {
2062 register: ::volatile_register::RW<u32>,
2063}
2064
2065impl Csr {
2066 pub fn read_bits(&self) -> u32 {
2067 self.register.read()
2068 }
2069 pub unsafe fn modify_bits<F>(&mut self, f: F)
2070 where F: FnOnce(&mut u32)
2071 {
2072 let mut bits = self.register.read();
2073 f(&mut bits);
2074 self.register.write(bits);
2075 }
2076 pub unsafe fn write_bits(&mut self, bits: u32) {
2077 self.register.write(bits);
2078 }
2079 pub fn modify<F>(&mut self, f: F)
2080 where for<'w> F: FnOnce(&CsrR, &'w mut CsrW) -> &'w mut CsrW
2081 {
2082 let bits = self.register.read();
2083 let r = CsrR { bits: bits };
2084 let mut w = CsrW { bits: bits };
2085 f(&r, &mut w);
2086 self.register.write(w.bits);
2087 }
2088 pub fn read(&self) -> CsrR {
2089 CsrR { bits: self.register.read() }
2090 }
2091 pub fn write<F>(&mut self, f: F)
2092 where F: FnOnce(&mut CsrW) -> &mut CsrW
2093 {
2094 let mut w = CsrW::reset_value();
2095 f(&mut w);
2096 self.register.write(w.bits);
2097 }
2098}
2099
2100# [ derive ( Clone , Copy ) ]
2101# [ repr ( C ) ]
2102pub struct CsrR {
2103 bits: u32,
2104}
2105
2106impl CsrR {
2107 # [ doc = "Bit 0 - Internal low speed oscillator enable" ]
2108 pub fn lsion(&self) -> bool {
2109 const OFFSET: u8 = 0u8;
2110 self.bits & (1 << OFFSET) != 0
2111 }
2112 # [ doc = "Bit 1 - Internal low speed oscillator ready" ]
2113 pub fn lsirdy(&self) -> bool {
2114 const OFFSET: u8 = 1u8;
2115 self.bits & (1 << OFFSET) != 0
2116 }
2117 # [ doc = "Bit 24 - Remove reset flag" ]
2118 pub fn rmvf(&self) -> bool {
2119 const OFFSET: u8 = 24u8;
2120 self.bits & (1 << OFFSET) != 0
2121 }
2122 # [ doc = "Bit 25 - Option byte loader reset flag" ]
2123 pub fn oblrstf(&self) -> bool {
2124 const OFFSET: u8 = 25u8;
2125 self.bits & (1 << OFFSET) != 0
2126 }
2127 # [ doc = "Bit 26 - PIN reset flag" ]
2128 pub fn pinrstf(&self) -> bool {
2129 const OFFSET: u8 = 26u8;
2130 self.bits & (1 << OFFSET) != 0
2131 }
2132 # [ doc = "Bit 27 - POR/PDR reset flag" ]
2133 pub fn porrstf(&self) -> bool {
2134 const OFFSET: u8 = 27u8;
2135 self.bits & (1 << OFFSET) != 0
2136 }
2137 # [ doc = "Bit 28 - Software reset flag" ]
2138 pub fn sftrstf(&self) -> bool {
2139 const OFFSET: u8 = 28u8;
2140 self.bits & (1 << OFFSET) != 0
2141 }
2142 # [ doc = "Bit 29 - Independent watchdog reset flag" ]
2143 pub fn iwdgrstf(&self) -> bool {
2144 const OFFSET: u8 = 29u8;
2145 self.bits & (1 << OFFSET) != 0
2146 }
2147 # [ doc = "Bit 30 - Window watchdog reset flag" ]
2148 pub fn wwdgrstf(&self) -> bool {
2149 const OFFSET: u8 = 30u8;
2150 self.bits & (1 << OFFSET) != 0
2151 }
2152 # [ doc = "Bit 31 - Low-power reset flag" ]
2153 pub fn lpwrrstf(&self) -> bool {
2154 const OFFSET: u8 = 31u8;
2155 self.bits & (1 << OFFSET) != 0
2156 }
2157}
2158
2159# [ derive ( Clone , Copy ) ]
2160# [ repr ( C ) ]
2161pub struct CsrW {
2162 bits: u32,
2163}
2164
2165impl CsrW {
2166 # [ doc = r" Reset value" ]
2167 pub fn reset_value() -> Self {
2168 CsrW { bits: 201326592 }
2169 }
2170 # [ doc = "Bit 0 - Internal low speed oscillator enable" ]
2171 pub fn lsion(&mut self, value: bool) -> &mut Self {
2172 const OFFSET: u8 = 0u8;
2173 if value {
2174 self.bits |= 1 << OFFSET;
2175 } else {
2176 self.bits &= !(1 << OFFSET);
2177 }
2178 self
2179 }
2180 # [ doc = "Bit 24 - Remove reset flag" ]
2181 pub fn rmvf(&mut self, value: bool) -> &mut Self {
2182 const OFFSET: u8 = 24u8;
2183 if value {
2184 self.bits |= 1 << OFFSET;
2185 } else {
2186 self.bits &= !(1 << OFFSET);
2187 }
2188 self
2189 }
2190 # [ doc = "Bit 25 - Option byte loader reset flag" ]
2191 pub fn oblrstf(&mut self, value: bool) -> &mut Self {
2192 const OFFSET: u8 = 25u8;
2193 if value {
2194 self.bits |= 1 << OFFSET;
2195 } else {
2196 self.bits &= !(1 << OFFSET);
2197 }
2198 self
2199 }
2200 # [ doc = "Bit 26 - PIN reset flag" ]
2201 pub fn pinrstf(&mut self, value: bool) -> &mut Self {
2202 const OFFSET: u8 = 26u8;
2203 if value {
2204 self.bits |= 1 << OFFSET;
2205 } else {
2206 self.bits &= !(1 << OFFSET);
2207 }
2208 self
2209 }
2210 # [ doc = "Bit 27 - POR/PDR reset flag" ]
2211 pub fn porrstf(&mut self, value: bool) -> &mut Self {
2212 const OFFSET: u8 = 27u8;
2213 if value {
2214 self.bits |= 1 << OFFSET;
2215 } else {
2216 self.bits &= !(1 << OFFSET);
2217 }
2218 self
2219 }
2220 # [ doc = "Bit 28 - Software reset flag" ]
2221 pub fn sftrstf(&mut self, value: bool) -> &mut Self {
2222 const OFFSET: u8 = 28u8;
2223 if value {
2224 self.bits |= 1 << OFFSET;
2225 } else {
2226 self.bits &= !(1 << OFFSET);
2227 }
2228 self
2229 }
2230 # [ doc = "Bit 29 - Independent watchdog reset flag" ]
2231 pub fn iwdgrstf(&mut self, value: bool) -> &mut Self {
2232 const OFFSET: u8 = 29u8;
2233 if value {
2234 self.bits |= 1 << OFFSET;
2235 } else {
2236 self.bits &= !(1 << OFFSET);
2237 }
2238 self
2239 }
2240 # [ doc = "Bit 30 - Window watchdog reset flag" ]
2241 pub fn wwdgrstf(&mut self, value: bool) -> &mut Self {
2242 const OFFSET: u8 = 30u8;
2243 if value {
2244 self.bits |= 1 << OFFSET;
2245 } else {
2246 self.bits &= !(1 << OFFSET);
2247 }
2248 self
2249 }
2250 # [ doc = "Bit 31 - Low-power reset flag" ]
2251 pub fn lpwrrstf(&mut self, value: bool) -> &mut Self {
2252 const OFFSET: u8 = 31u8;
2253 if value {
2254 self.bits |= 1 << OFFSET;
2255 } else {
2256 self.bits &= !(1 << OFFSET);
2257 }
2258 self
2259 }
2260}
2261
2262# [ repr ( C ) ]
2263pub struct Ahbrstr {
2264 register: ::volatile_register::RW<u32>,
2265}
2266
2267impl Ahbrstr {
2268 pub fn read_bits(&self) -> u32 {
2269 self.register.read()
2270 }
2271 pub unsafe fn modify_bits<F>(&mut self, f: F)
2272 where F: FnOnce(&mut u32)
2273 {
2274 let mut bits = self.register.read();
2275 f(&mut bits);
2276 self.register.write(bits);
2277 }
2278 pub unsafe fn write_bits(&mut self, bits: u32) {
2279 self.register.write(bits);
2280 }
2281 pub fn modify<F>(&mut self, f: F)
2282 where for<'w> F: FnOnce(&AhbrstrR, &'w mut AhbrstrW) -> &'w mut AhbrstrW
2283 {
2284 let bits = self.register.read();
2285 let r = AhbrstrR { bits: bits };
2286 let mut w = AhbrstrW { bits: bits };
2287 f(&r, &mut w);
2288 self.register.write(w.bits);
2289 }
2290 pub fn read(&self) -> AhbrstrR {
2291 AhbrstrR { bits: self.register.read() }
2292 }
2293 pub fn write<F>(&mut self, f: F)
2294 where F: FnOnce(&mut AhbrstrW) -> &mut AhbrstrW
2295 {
2296 let mut w = AhbrstrW::reset_value();
2297 f(&mut w);
2298 self.register.write(w.bits);
2299 }
2300}
2301
2302# [ derive ( Clone , Copy ) ]
2303# [ repr ( C ) ]
2304pub struct AhbrstrR {
2305 bits: u32,
2306}
2307
2308impl AhbrstrR {
2309 # [ doc = "Bit 17 - I/O port A reset" ]
2310 pub fn ioparst(&self) -> bool {
2311 const OFFSET: u8 = 17u8;
2312 self.bits & (1 << OFFSET) != 0
2313 }
2314 # [ doc = "Bit 18 - I/O port B reset" ]
2315 pub fn iopbrst(&self) -> bool {
2316 const OFFSET: u8 = 18u8;
2317 self.bits & (1 << OFFSET) != 0
2318 }
2319 # [ doc = "Bit 19 - I/O port C reset" ]
2320 pub fn iopcrst(&self) -> bool {
2321 const OFFSET: u8 = 19u8;
2322 self.bits & (1 << OFFSET) != 0
2323 }
2324 # [ doc = "Bit 20 - I/O port D reset" ]
2325 pub fn iopdrst(&self) -> bool {
2326 const OFFSET: u8 = 20u8;
2327 self.bits & (1 << OFFSET) != 0
2328 }
2329 # [ doc = "Bit 21 - I/O port E reset" ]
2330 pub fn ioperst(&self) -> bool {
2331 const OFFSET: u8 = 21u8;
2332 self.bits & (1 << OFFSET) != 0
2333 }
2334 # [ doc = "Bit 22 - I/O port F reset" ]
2335 pub fn iopfrst(&self) -> bool {
2336 const OFFSET: u8 = 22u8;
2337 self.bits & (1 << OFFSET) != 0
2338 }
2339 # [ doc = "Bit 24 - Touch sensing controller reset" ]
2340 pub fn tscrst(&self) -> bool {
2341 const OFFSET: u8 = 24u8;
2342 self.bits & (1 << OFFSET) != 0
2343 }
2344 # [ doc = "Bit 28 - ADC1 and ADC2 reset" ]
2345 pub fn adc12rst(&self) -> bool {
2346 const OFFSET: u8 = 28u8;
2347 self.bits & (1 << OFFSET) != 0
2348 }
2349 # [ doc = "Bit 29 - ADC3 and ADC4 reset" ]
2350 pub fn adc34rst(&self) -> bool {
2351 const OFFSET: u8 = 29u8;
2352 self.bits & (1 << OFFSET) != 0
2353 }
2354}
2355
2356# [ derive ( Clone , Copy ) ]
2357# [ repr ( C ) ]
2358pub struct AhbrstrW {
2359 bits: u32,
2360}
2361
2362impl AhbrstrW {
2363 # [ doc = r" Reset value" ]
2364 pub fn reset_value() -> Self {
2365 AhbrstrW { bits: 0 }
2366 }
2367 # [ doc = "Bit 17 - I/O port A reset" ]
2368 pub fn ioparst(&mut self, value: bool) -> &mut Self {
2369 const OFFSET: u8 = 17u8;
2370 if value {
2371 self.bits |= 1 << OFFSET;
2372 } else {
2373 self.bits &= !(1 << OFFSET);
2374 }
2375 self
2376 }
2377 # [ doc = "Bit 18 - I/O port B reset" ]
2378 pub fn iopbrst(&mut self, value: bool) -> &mut Self {
2379 const OFFSET: u8 = 18u8;
2380 if value {
2381 self.bits |= 1 << OFFSET;
2382 } else {
2383 self.bits &= !(1 << OFFSET);
2384 }
2385 self
2386 }
2387 # [ doc = "Bit 19 - I/O port C reset" ]
2388 pub fn iopcrst(&mut self, value: bool) -> &mut Self {
2389 const OFFSET: u8 = 19u8;
2390 if value {
2391 self.bits |= 1 << OFFSET;
2392 } else {
2393 self.bits &= !(1 << OFFSET);
2394 }
2395 self
2396 }
2397 # [ doc = "Bit 20 - I/O port D reset" ]
2398 pub fn iopdrst(&mut self, value: bool) -> &mut Self {
2399 const OFFSET: u8 = 20u8;
2400 if value {
2401 self.bits |= 1 << OFFSET;
2402 } else {
2403 self.bits &= !(1 << OFFSET);
2404 }
2405 self
2406 }
2407 # [ doc = "Bit 21 - I/O port E reset" ]
2408 pub fn ioperst(&mut self, value: bool) -> &mut Self {
2409 const OFFSET: u8 = 21u8;
2410 if value {
2411 self.bits |= 1 << OFFSET;
2412 } else {
2413 self.bits &= !(1 << OFFSET);
2414 }
2415 self
2416 }
2417 # [ doc = "Bit 22 - I/O port F reset" ]
2418 pub fn iopfrst(&mut self, value: bool) -> &mut Self {
2419 const OFFSET: u8 = 22u8;
2420 if value {
2421 self.bits |= 1 << OFFSET;
2422 } else {
2423 self.bits &= !(1 << OFFSET);
2424 }
2425 self
2426 }
2427 # [ doc = "Bit 24 - Touch sensing controller reset" ]
2428 pub fn tscrst(&mut self, value: bool) -> &mut Self {
2429 const OFFSET: u8 = 24u8;
2430 if value {
2431 self.bits |= 1 << OFFSET;
2432 } else {
2433 self.bits &= !(1 << OFFSET);
2434 }
2435 self
2436 }
2437 # [ doc = "Bit 28 - ADC1 and ADC2 reset" ]
2438 pub fn adc12rst(&mut self, value: bool) -> &mut Self {
2439 const OFFSET: u8 = 28u8;
2440 if value {
2441 self.bits |= 1 << OFFSET;
2442 } else {
2443 self.bits &= !(1 << OFFSET);
2444 }
2445 self
2446 }
2447 # [ doc = "Bit 29 - ADC3 and ADC4 reset" ]
2448 pub fn adc34rst(&mut self, value: bool) -> &mut Self {
2449 const OFFSET: u8 = 29u8;
2450 if value {
2451 self.bits |= 1 << OFFSET;
2452 } else {
2453 self.bits &= !(1 << OFFSET);
2454 }
2455 self
2456 }
2457}
2458
2459# [ repr ( C ) ]
2460pub struct Cfgr2 {
2461 register: ::volatile_register::RW<u32>,
2462}
2463
2464impl Cfgr2 {
2465 pub fn read_bits(&self) -> u32 {
2466 self.register.read()
2467 }
2468 pub unsafe fn modify_bits<F>(&mut self, f: F)
2469 where F: FnOnce(&mut u32)
2470 {
2471 let mut bits = self.register.read();
2472 f(&mut bits);
2473 self.register.write(bits);
2474 }
2475 pub unsafe fn write_bits(&mut self, bits: u32) {
2476 self.register.write(bits);
2477 }
2478 pub fn modify<F>(&mut self, f: F)
2479 where for<'w> F: FnOnce(&Cfgr2R, &'w mut Cfgr2W) -> &'w mut Cfgr2W
2480 {
2481 let bits = self.register.read();
2482 let r = Cfgr2R { bits: bits };
2483 let mut w = Cfgr2W { bits: bits };
2484 f(&r, &mut w);
2485 self.register.write(w.bits);
2486 }
2487 pub fn read(&self) -> Cfgr2R {
2488 Cfgr2R { bits: self.register.read() }
2489 }
2490 pub fn write<F>(&mut self, f: F)
2491 where F: FnOnce(&mut Cfgr2W) -> &mut Cfgr2W
2492 {
2493 let mut w = Cfgr2W::reset_value();
2494 f(&mut w);
2495 self.register.write(w.bits);
2496 }
2497}
2498
2499# [ derive ( Clone , Copy ) ]
2500# [ repr ( C ) ]
2501pub struct Cfgr2R {
2502 bits: u32,
2503}
2504
2505impl Cfgr2R {
2506 # [ doc = "Bits 0:3 - PREDIV division factor" ]
2507 pub fn prediv(&self) -> u8 {
2508 const MASK: u32 = 15;
2509 const OFFSET: u8 = 0u8;
2510 ((self.bits >> OFFSET) & MASK) as u8
2511 }
2512 # [ doc = "Bits 4:8 - ADC1 and ADC2 prescaler" ]
2513 pub fn adc12pres(&self) -> u8 {
2514 const MASK: u32 = 31;
2515 const OFFSET: u8 = 4u8;
2516 ((self.bits >> OFFSET) & MASK) as u8
2517 }
2518 # [ doc = "Bits 9:13 - ADC3 and ADC4 prescaler" ]
2519 pub fn adc34pres(&self) -> u8 {
2520 const MASK: u32 = 31;
2521 const OFFSET: u8 = 9u8;
2522 ((self.bits >> OFFSET) & MASK) as u8
2523 }
2524}
2525
2526# [ derive ( Clone , Copy ) ]
2527# [ repr ( C ) ]
2528pub struct Cfgr2W {
2529 bits: u32,
2530}
2531
2532impl Cfgr2W {
2533 # [ doc = r" Reset value" ]
2534 pub fn reset_value() -> Self {
2535 Cfgr2W { bits: 0 }
2536 }
2537 # [ doc = "Bits 0:3 - PREDIV division factor" ]
2538 pub fn prediv(&mut self, value: u8) -> &mut Self {
2539 const OFFSET: u8 = 0u8;
2540 const MASK: u8 = 15;
2541 self.bits &= !((MASK as u32) << OFFSET);
2542 self.bits |= ((value & MASK) as u32) << OFFSET;
2543 self
2544 }
2545 # [ doc = "Bits 4:8 - ADC1 and ADC2 prescaler" ]
2546 pub fn adc12pres(&mut self, value: u8) -> &mut Self {
2547 const OFFSET: u8 = 4u8;
2548 const MASK: u8 = 31;
2549 self.bits &= !((MASK as u32) << OFFSET);
2550 self.bits |= ((value & MASK) as u32) << OFFSET;
2551 self
2552 }
2553 # [ doc = "Bits 9:13 - ADC3 and ADC4 prescaler" ]
2554 pub fn adc34pres(&mut self, value: u8) -> &mut Self {
2555 const OFFSET: u8 = 9u8;
2556 const MASK: u8 = 31;
2557 self.bits &= !((MASK as u32) << OFFSET);
2558 self.bits |= ((value & MASK) as u32) << OFFSET;
2559 self
2560 }
2561}
2562
2563# [ repr ( C ) ]
2564pub struct Cfgr3 {
2565 register: ::volatile_register::RW<u32>,
2566}
2567
2568impl Cfgr3 {
2569 pub fn read_bits(&self) -> u32 {
2570 self.register.read()
2571 }
2572 pub unsafe fn modify_bits<F>(&mut self, f: F)
2573 where F: FnOnce(&mut u32)
2574 {
2575 let mut bits = self.register.read();
2576 f(&mut bits);
2577 self.register.write(bits);
2578 }
2579 pub unsafe fn write_bits(&mut self, bits: u32) {
2580 self.register.write(bits);
2581 }
2582 pub fn modify<F>(&mut self, f: F)
2583 where for<'w> F: FnOnce(&Cfgr3R, &'w mut Cfgr3W) -> &'w mut Cfgr3W
2584 {
2585 let bits = self.register.read();
2586 let r = Cfgr3R { bits: bits };
2587 let mut w = Cfgr3W { bits: bits };
2588 f(&r, &mut w);
2589 self.register.write(w.bits);
2590 }
2591 pub fn read(&self) -> Cfgr3R {
2592 Cfgr3R { bits: self.register.read() }
2593 }
2594 pub fn write<F>(&mut self, f: F)
2595 where F: FnOnce(&mut Cfgr3W) -> &mut Cfgr3W
2596 {
2597 let mut w = Cfgr3W::reset_value();
2598 f(&mut w);
2599 self.register.write(w.bits);
2600 }
2601}
2602
2603# [ derive ( Clone , Copy ) ]
2604# [ repr ( C ) ]
2605pub struct Cfgr3R {
2606 bits: u32,
2607}
2608
2609impl Cfgr3R {
2610 # [ doc = "Bits 0:1 - USART1 clock source selection" ]
2611 pub fn usart1sw(&self) -> u8 {
2612 const MASK: u32 = 3;
2613 const OFFSET: u8 = 0u8;
2614 ((self.bits >> OFFSET) & MASK) as u8
2615 }
2616 # [ doc = "Bit 4 - I2C1 clock source selection" ]
2617 pub fn i2c1sw(&self) -> bool {
2618 const OFFSET: u8 = 4u8;
2619 self.bits & (1 << OFFSET) != 0
2620 }
2621 # [ doc = "Bit 5 - I2C2 clock source selection" ]
2622 pub fn i2c2sw(&self) -> bool {
2623 const OFFSET: u8 = 5u8;
2624 self.bits & (1 << OFFSET) != 0
2625 }
2626 # [ doc = "Bits 16:17 - USART2 clock source selection" ]
2627 pub fn usart2sw(&self) -> u8 {
2628 const MASK: u32 = 3;
2629 const OFFSET: u8 = 16u8;
2630 ((self.bits >> OFFSET) & MASK) as u8
2631 }
2632 # [ doc = "Bits 18:19 - USART3 clock source selection" ]
2633 pub fn usart3sw(&self) -> u8 {
2634 const MASK: u32 = 3;
2635 const OFFSET: u8 = 18u8;
2636 ((self.bits >> OFFSET) & MASK) as u8
2637 }
2638 # [ doc = "Bit 8 - Timer1 clock source selection" ]
2639 pub fn tim1sw(&self) -> bool {
2640 const OFFSET: u8 = 8u8;
2641 self.bits & (1 << OFFSET) != 0
2642 }
2643 # [ doc = "Bit 9 - Timer8 clock source selection" ]
2644 pub fn tim8sw(&self) -> bool {
2645 const OFFSET: u8 = 9u8;
2646 self.bits & (1 << OFFSET) != 0
2647 }
2648 # [ doc = "Bits 20:21 - UART4 clock source selection" ]
2649 pub fn uart4sw(&self) -> u8 {
2650 const MASK: u32 = 3;
2651 const OFFSET: u8 = 20u8;
2652 ((self.bits >> OFFSET) & MASK) as u8
2653 }
2654 # [ doc = "Bits 22:23 - UART5 clock source selection" ]
2655 pub fn uart5sw(&self) -> u8 {
2656 const MASK: u32 = 3;
2657 const OFFSET: u8 = 22u8;
2658 ((self.bits >> OFFSET) & MASK) as u8
2659 }
2660}
2661
2662# [ derive ( Clone , Copy ) ]
2663# [ repr ( C ) ]
2664pub struct Cfgr3W {
2665 bits: u32,
2666}
2667
2668impl Cfgr3W {
2669 # [ doc = r" Reset value" ]
2670 pub fn reset_value() -> Self {
2671 Cfgr3W { bits: 0 }
2672 }
2673 # [ doc = "Bits 0:1 - USART1 clock source selection" ]
2674 pub fn usart1sw(&mut self, value: u8) -> &mut Self {
2675 const OFFSET: u8 = 0u8;
2676 const MASK: u8 = 3;
2677 self.bits &= !((MASK as u32) << OFFSET);
2678 self.bits |= ((value & MASK) as u32) << OFFSET;
2679 self
2680 }
2681 # [ doc = "Bit 4 - I2C1 clock source selection" ]
2682 pub fn i2c1sw(&mut self, value: bool) -> &mut Self {
2683 const OFFSET: u8 = 4u8;
2684 if value {
2685 self.bits |= 1 << OFFSET;
2686 } else {
2687 self.bits &= !(1 << OFFSET);
2688 }
2689 self
2690 }
2691 # [ doc = "Bit 5 - I2C2 clock source selection" ]
2692 pub fn i2c2sw(&mut self, value: bool) -> &mut Self {
2693 const OFFSET: u8 = 5u8;
2694 if value {
2695 self.bits |= 1 << OFFSET;
2696 } else {
2697 self.bits &= !(1 << OFFSET);
2698 }
2699 self
2700 }
2701 # [ doc = "Bits 16:17 - USART2 clock source selection" ]
2702 pub fn usart2sw(&mut self, value: u8) -> &mut Self {
2703 const OFFSET: u8 = 16u8;
2704 const MASK: u8 = 3;
2705 self.bits &= !((MASK as u32) << OFFSET);
2706 self.bits |= ((value & MASK) as u32) << OFFSET;
2707 self
2708 }
2709 # [ doc = "Bits 18:19 - USART3 clock source selection" ]
2710 pub fn usart3sw(&mut self, value: u8) -> &mut Self {
2711 const OFFSET: u8 = 18u8;
2712 const MASK: u8 = 3;
2713 self.bits &= !((MASK as u32) << OFFSET);
2714 self.bits |= ((value & MASK) as u32) << OFFSET;
2715 self
2716 }
2717 # [ doc = "Bit 8 - Timer1 clock source selection" ]
2718 pub fn tim1sw(&mut self, value: bool) -> &mut Self {
2719 const OFFSET: u8 = 8u8;
2720 if value {
2721 self.bits |= 1 << OFFSET;
2722 } else {
2723 self.bits &= !(1 << OFFSET);
2724 }
2725 self
2726 }
2727 # [ doc = "Bit 9 - Timer8 clock source selection" ]
2728 pub fn tim8sw(&mut self, value: bool) -> &mut Self {
2729 const OFFSET: u8 = 9u8;
2730 if value {
2731 self.bits |= 1 << OFFSET;
2732 } else {
2733 self.bits &= !(1 << OFFSET);
2734 }
2735 self
2736 }
2737 # [ doc = "Bits 20:21 - UART4 clock source selection" ]
2738 pub fn uart4sw(&mut self, value: u8) -> &mut Self {
2739 const OFFSET: u8 = 20u8;
2740 const MASK: u8 = 3;
2741 self.bits &= !((MASK as u32) << OFFSET);
2742 self.bits |= ((value & MASK) as u32) << OFFSET;
2743 self
2744 }
2745 # [ doc = "Bits 22:23 - UART5 clock source selection" ]
2746 pub fn uart5sw(&mut self, value: u8) -> &mut Self {
2747 const OFFSET: u8 = 22u8;
2748 const MASK: u8 = 3;
2749 self.bits &= !((MASK as u32) << OFFSET);
2750 self.bits |= ((value & MASK) as u32) << OFFSET;
2751 self
2752 }
2753}