stm32f30x_memory_map/
i2c.rs

1# [ doc = "Inter-integrated circuit" ]
2# [ repr ( C ) ]
3pub struct I2c {
4    # [ doc = "0x00 - Control register 1" ]
5    pub cr1: Cr1,
6    # [ doc = "0x04 - Control register 2" ]
7    pub cr2: Cr2,
8    # [ doc = "0x08 - Own address register 1" ]
9    pub oar1: Oar1,
10    # [ doc = "0x0c - Own address register 2" ]
11    pub oar2: Oar2,
12    # [ doc = "0x10 - Timing register" ]
13    pub timingr: Timingr,
14    # [ doc = "0x14 - Status register 1" ]
15    pub timeoutr: Timeoutr,
16    # [ doc = "0x18 - Interrupt and Status register" ]
17    pub isr: Isr,
18    # [ doc = "0x1c - Interrupt clear register" ]
19    pub icr: Icr,
20    # [ doc = "0x20 - PEC register" ]
21    pub pecr: Pecr,
22    # [ doc = "0x24 - Receive data register" ]
23    pub rxdr: Rxdr,
24    # [ doc = "0x28 - Transmit data register" ]
25    pub txdr: Txdr,
26}
27
28# [ repr ( C ) ]
29pub struct Cr1 {
30    register: ::volatile_register::RW<u32>,
31}
32
33impl Cr1 {
34    pub fn read_bits(&self) -> u32 {
35        self.register.read()
36    }
37    pub unsafe fn modify_bits<F>(&mut self, f: F)
38        where F: FnOnce(&mut u32)
39    {
40        let mut bits = self.register.read();
41        f(&mut bits);
42        self.register.write(bits);
43    }
44    pub unsafe fn write_bits(&mut self, bits: u32) {
45        self.register.write(bits);
46    }
47    pub fn modify<F>(&mut self, f: F)
48        where for<'w> F: FnOnce(&Cr1R, &'w mut Cr1W) -> &'w mut Cr1W
49    {
50        let bits = self.register.read();
51        let r = Cr1R { bits: bits };
52        let mut w = Cr1W { bits: bits };
53        f(&r, &mut w);
54        self.register.write(w.bits);
55    }
56    pub fn read(&self) -> Cr1R {
57        Cr1R { bits: self.register.read() }
58    }
59    pub fn write<F>(&mut self, f: F)
60        where F: FnOnce(&mut Cr1W) -> &mut Cr1W
61    {
62        let mut w = Cr1W::reset_value();
63        f(&mut w);
64        self.register.write(w.bits);
65    }
66}
67
68# [ derive ( Clone , Copy ) ]
69# [ repr ( C ) ]
70pub struct Cr1R {
71    bits: u32,
72}
73
74impl Cr1R {
75    # [ doc = "Bit 0 - Peripheral enable" ]
76    pub fn pe(&self) -> bool {
77        const OFFSET: u8 = 0u8;
78        self.bits & (1 << OFFSET) != 0
79    }
80    # [ doc = "Bit 1 - TX Interrupt enable" ]
81    pub fn txie(&self) -> bool {
82        const OFFSET: u8 = 1u8;
83        self.bits & (1 << OFFSET) != 0
84    }
85    # [ doc = "Bit 2 - RX Interrupt enable" ]
86    pub fn rxie(&self) -> bool {
87        const OFFSET: u8 = 2u8;
88        self.bits & (1 << OFFSET) != 0
89    }
90    # [ doc = "Bit 3 - Address match interrupt enable (slave only)" ]
91    pub fn addrie(&self) -> bool {
92        const OFFSET: u8 = 3u8;
93        self.bits & (1 << OFFSET) != 0
94    }
95    # [ doc = "Bit 4 - Not acknowledge received interrupt enable" ]
96    pub fn nackie(&self) -> bool {
97        const OFFSET: u8 = 4u8;
98        self.bits & (1 << OFFSET) != 0
99    }
100    # [ doc = "Bit 5 - STOP detection Interrupt enable" ]
101    pub fn stopie(&self) -> bool {
102        const OFFSET: u8 = 5u8;
103        self.bits & (1 << OFFSET) != 0
104    }
105    # [ doc = "Bit 6 - Transfer Complete interrupt enable" ]
106    pub fn tcie(&self) -> bool {
107        const OFFSET: u8 = 6u8;
108        self.bits & (1 << OFFSET) != 0
109    }
110    # [ doc = "Bit 7 - Error interrupts enable" ]
111    pub fn errie(&self) -> bool {
112        const OFFSET: u8 = 7u8;
113        self.bits & (1 << OFFSET) != 0
114    }
115    # [ doc = "Bits 8:11 - Digital noise filter" ]
116    pub fn dnf(&self) -> u8 {
117        const MASK: u32 = 15;
118        const OFFSET: u8 = 8u8;
119        ((self.bits >> OFFSET) & MASK) as u8
120    }
121    # [ doc = "Bit 12 - Analog noise filter OFF" ]
122    pub fn anfoff(&self) -> bool {
123        const OFFSET: u8 = 12u8;
124        self.bits & (1 << OFFSET) != 0
125    }
126    # [ doc = "Bit 14 - DMA transmission requests enable" ]
127    pub fn txdmaen(&self) -> bool {
128        const OFFSET: u8 = 14u8;
129        self.bits & (1 << OFFSET) != 0
130    }
131    # [ doc = "Bit 15 - DMA reception requests enable" ]
132    pub fn rxdmaen(&self) -> bool {
133        const OFFSET: u8 = 15u8;
134        self.bits & (1 << OFFSET) != 0
135    }
136    # [ doc = "Bit 16 - Slave byte control" ]
137    pub fn sbc(&self) -> bool {
138        const OFFSET: u8 = 16u8;
139        self.bits & (1 << OFFSET) != 0
140    }
141    # [ doc = "Bit 17 - Clock stretching disable" ]
142    pub fn nostretch(&self) -> bool {
143        const OFFSET: u8 = 17u8;
144        self.bits & (1 << OFFSET) != 0
145    }
146    # [ doc = "Bit 18 - Wakeup from STOP enable" ]
147    pub fn wupen(&self) -> bool {
148        const OFFSET: u8 = 18u8;
149        self.bits & (1 << OFFSET) != 0
150    }
151    # [ doc = "Bit 19 - General call enable" ]
152    pub fn gcen(&self) -> bool {
153        const OFFSET: u8 = 19u8;
154        self.bits & (1 << OFFSET) != 0
155    }
156    # [ doc = "Bit 20 - SMBus Host address enable" ]
157    pub fn smbhen(&self) -> bool {
158        const OFFSET: u8 = 20u8;
159        self.bits & (1 << OFFSET) != 0
160    }
161    # [ doc = "Bit 21 - SMBus Device Default address enable" ]
162    pub fn smbden(&self) -> bool {
163        const OFFSET: u8 = 21u8;
164        self.bits & (1 << OFFSET) != 0
165    }
166    # [ doc = "Bit 22 - SMBUS alert enable" ]
167    pub fn alerten(&self) -> bool {
168        const OFFSET: u8 = 22u8;
169        self.bits & (1 << OFFSET) != 0
170    }
171    # [ doc = "Bit 23 - PEC enable" ]
172    pub fn pecen(&self) -> bool {
173        const OFFSET: u8 = 23u8;
174        self.bits & (1 << OFFSET) != 0
175    }
176}
177
178# [ derive ( Clone , Copy ) ]
179# [ repr ( C ) ]
180pub struct Cr1W {
181    bits: u32,
182}
183
184impl Cr1W {
185    # [ doc = r" Reset value" ]
186    pub fn reset_value() -> Self {
187        Cr1W { bits: 0 }
188    }
189    # [ doc = "Bit 0 - Peripheral enable" ]
190    pub fn pe(&mut self, value: bool) -> &mut Self {
191        const OFFSET: u8 = 0u8;
192        if value {
193            self.bits |= 1 << OFFSET;
194        } else {
195            self.bits &= !(1 << OFFSET);
196        }
197        self
198    }
199    # [ doc = "Bit 1 - TX Interrupt enable" ]
200    pub fn txie(&mut self, value: bool) -> &mut Self {
201        const OFFSET: u8 = 1u8;
202        if value {
203            self.bits |= 1 << OFFSET;
204        } else {
205            self.bits &= !(1 << OFFSET);
206        }
207        self
208    }
209    # [ doc = "Bit 2 - RX Interrupt enable" ]
210    pub fn rxie(&mut self, value: bool) -> &mut Self {
211        const OFFSET: u8 = 2u8;
212        if value {
213            self.bits |= 1 << OFFSET;
214        } else {
215            self.bits &= !(1 << OFFSET);
216        }
217        self
218    }
219    # [ doc = "Bit 3 - Address match interrupt enable (slave only)" ]
220    pub fn addrie(&mut self, value: bool) -> &mut Self {
221        const OFFSET: u8 = 3u8;
222        if value {
223            self.bits |= 1 << OFFSET;
224        } else {
225            self.bits &= !(1 << OFFSET);
226        }
227        self
228    }
229    # [ doc = "Bit 4 - Not acknowledge received interrupt enable" ]
230    pub fn nackie(&mut self, value: bool) -> &mut Self {
231        const OFFSET: u8 = 4u8;
232        if value {
233            self.bits |= 1 << OFFSET;
234        } else {
235            self.bits &= !(1 << OFFSET);
236        }
237        self
238    }
239    # [ doc = "Bit 5 - STOP detection Interrupt enable" ]
240    pub fn stopie(&mut self, value: bool) -> &mut Self {
241        const OFFSET: u8 = 5u8;
242        if value {
243            self.bits |= 1 << OFFSET;
244        } else {
245            self.bits &= !(1 << OFFSET);
246        }
247        self
248    }
249    # [ doc = "Bit 6 - Transfer Complete interrupt enable" ]
250    pub fn tcie(&mut self, value: bool) -> &mut Self {
251        const OFFSET: u8 = 6u8;
252        if value {
253            self.bits |= 1 << OFFSET;
254        } else {
255            self.bits &= !(1 << OFFSET);
256        }
257        self
258    }
259    # [ doc = "Bit 7 - Error interrupts enable" ]
260    pub fn errie(&mut self, value: bool) -> &mut Self {
261        const OFFSET: u8 = 7u8;
262        if value {
263            self.bits |= 1 << OFFSET;
264        } else {
265            self.bits &= !(1 << OFFSET);
266        }
267        self
268    }
269    # [ doc = "Bits 8:11 - Digital noise filter" ]
270    pub fn dnf(&mut self, value: u8) -> &mut Self {
271        const OFFSET: u8 = 8u8;
272        const MASK: u8 = 15;
273        self.bits &= !((MASK as u32) << OFFSET);
274        self.bits |= ((value & MASK) as u32) << OFFSET;
275        self
276    }
277    # [ doc = "Bit 12 - Analog noise filter OFF" ]
278    pub fn anfoff(&mut self, value: bool) -> &mut Self {
279        const OFFSET: u8 = 12u8;
280        if value {
281            self.bits |= 1 << OFFSET;
282        } else {
283            self.bits &= !(1 << OFFSET);
284        }
285        self
286    }
287    # [ doc = "Bit 13 - Software reset" ]
288    pub fn swrst(&mut self, value: bool) -> &mut Self {
289        const OFFSET: u8 = 13u8;
290        if value {
291            self.bits |= 1 << OFFSET;
292        } else {
293            self.bits &= !(1 << OFFSET);
294        }
295        self
296    }
297    # [ doc = "Bit 14 - DMA transmission requests enable" ]
298    pub fn txdmaen(&mut self, value: bool) -> &mut Self {
299        const OFFSET: u8 = 14u8;
300        if value {
301            self.bits |= 1 << OFFSET;
302        } else {
303            self.bits &= !(1 << OFFSET);
304        }
305        self
306    }
307    # [ doc = "Bit 15 - DMA reception requests enable" ]
308    pub fn rxdmaen(&mut self, value: bool) -> &mut Self {
309        const OFFSET: u8 = 15u8;
310        if value {
311            self.bits |= 1 << OFFSET;
312        } else {
313            self.bits &= !(1 << OFFSET);
314        }
315        self
316    }
317    # [ doc = "Bit 16 - Slave byte control" ]
318    pub fn sbc(&mut self, value: bool) -> &mut Self {
319        const OFFSET: u8 = 16u8;
320        if value {
321            self.bits |= 1 << OFFSET;
322        } else {
323            self.bits &= !(1 << OFFSET);
324        }
325        self
326    }
327    # [ doc = "Bit 17 - Clock stretching disable" ]
328    pub fn nostretch(&mut self, value: bool) -> &mut Self {
329        const OFFSET: u8 = 17u8;
330        if value {
331            self.bits |= 1 << OFFSET;
332        } else {
333            self.bits &= !(1 << OFFSET);
334        }
335        self
336    }
337    # [ doc = "Bit 18 - Wakeup from STOP enable" ]
338    pub fn wupen(&mut self, value: bool) -> &mut Self {
339        const OFFSET: u8 = 18u8;
340        if value {
341            self.bits |= 1 << OFFSET;
342        } else {
343            self.bits &= !(1 << OFFSET);
344        }
345        self
346    }
347    # [ doc = "Bit 19 - General call enable" ]
348    pub fn gcen(&mut self, value: bool) -> &mut Self {
349        const OFFSET: u8 = 19u8;
350        if value {
351            self.bits |= 1 << OFFSET;
352        } else {
353            self.bits &= !(1 << OFFSET);
354        }
355        self
356    }
357    # [ doc = "Bit 20 - SMBus Host address enable" ]
358    pub fn smbhen(&mut self, value: bool) -> &mut Self {
359        const OFFSET: u8 = 20u8;
360        if value {
361            self.bits |= 1 << OFFSET;
362        } else {
363            self.bits &= !(1 << OFFSET);
364        }
365        self
366    }
367    # [ doc = "Bit 21 - SMBus Device Default address enable" ]
368    pub fn smbden(&mut self, value: bool) -> &mut Self {
369        const OFFSET: u8 = 21u8;
370        if value {
371            self.bits |= 1 << OFFSET;
372        } else {
373            self.bits &= !(1 << OFFSET);
374        }
375        self
376    }
377    # [ doc = "Bit 22 - SMBUS alert enable" ]
378    pub fn alerten(&mut self, value: bool) -> &mut Self {
379        const OFFSET: u8 = 22u8;
380        if value {
381            self.bits |= 1 << OFFSET;
382        } else {
383            self.bits &= !(1 << OFFSET);
384        }
385        self
386    }
387    # [ doc = "Bit 23 - PEC enable" ]
388    pub fn pecen(&mut self, value: bool) -> &mut Self {
389        const OFFSET: u8 = 23u8;
390        if value {
391            self.bits |= 1 << OFFSET;
392        } else {
393            self.bits &= !(1 << OFFSET);
394        }
395        self
396    }
397}
398
399# [ repr ( C ) ]
400pub struct Cr2 {
401    register: ::volatile_register::RW<u32>,
402}
403
404impl Cr2 {
405    pub fn read_bits(&self) -> u32 {
406        self.register.read()
407    }
408    pub unsafe fn modify_bits<F>(&mut self, f: F)
409        where F: FnOnce(&mut u32)
410    {
411        let mut bits = self.register.read();
412        f(&mut bits);
413        self.register.write(bits);
414    }
415    pub unsafe fn write_bits(&mut self, bits: u32) {
416        self.register.write(bits);
417    }
418    pub fn modify<F>(&mut self, f: F)
419        where for<'w> F: FnOnce(&Cr2R, &'w mut Cr2W) -> &'w mut Cr2W
420    {
421        let bits = self.register.read();
422        let r = Cr2R { bits: bits };
423        let mut w = Cr2W { bits: bits };
424        f(&r, &mut w);
425        self.register.write(w.bits);
426    }
427    pub fn read(&self) -> Cr2R {
428        Cr2R { bits: self.register.read() }
429    }
430    pub fn write<F>(&mut self, f: F)
431        where F: FnOnce(&mut Cr2W) -> &mut Cr2W
432    {
433        let mut w = Cr2W::reset_value();
434        f(&mut w);
435        self.register.write(w.bits);
436    }
437}
438
439# [ derive ( Clone , Copy ) ]
440# [ repr ( C ) ]
441pub struct Cr2R {
442    bits: u32,
443}
444
445impl Cr2R {
446    # [ doc = "Bit 26 - Packet error checking byte" ]
447    pub fn pecbyte(&self) -> bool {
448        const OFFSET: u8 = 26u8;
449        self.bits & (1 << OFFSET) != 0
450    }
451    # [ doc = "Bit 25 - Automatic end mode (master mode)" ]
452    pub fn autoend(&self) -> bool {
453        const OFFSET: u8 = 25u8;
454        self.bits & (1 << OFFSET) != 0
455    }
456    # [ doc = "Bit 24 - NBYTES reload mode" ]
457    pub fn reload(&self) -> bool {
458        const OFFSET: u8 = 24u8;
459        self.bits & (1 << OFFSET) != 0
460    }
461    # [ doc = "Bits 16:23 - Number of bytes" ]
462    pub fn nbytes(&self) -> u8 {
463        const MASK: u32 = 255;
464        const OFFSET: u8 = 16u8;
465        ((self.bits >> OFFSET) & MASK) as u8
466    }
467    # [ doc = "Bit 15 - NACK generation (slave mode)" ]
468    pub fn nack(&self) -> bool {
469        const OFFSET: u8 = 15u8;
470        self.bits & (1 << OFFSET) != 0
471    }
472    # [ doc = "Bit 14 - Stop generation (master mode)" ]
473    pub fn stop(&self) -> bool {
474        const OFFSET: u8 = 14u8;
475        self.bits & (1 << OFFSET) != 0
476    }
477    # [ doc = "Bit 13 - Start generation" ]
478    pub fn start(&self) -> bool {
479        const OFFSET: u8 = 13u8;
480        self.bits & (1 << OFFSET) != 0
481    }
482    # [ doc = "Bit 12 - 10-bit address header only read direction (master receiver mode)" ]
483    pub fn head10r(&self) -> bool {
484        const OFFSET: u8 = 12u8;
485        self.bits & (1 << OFFSET) != 0
486    }
487    # [ doc = "Bit 11 - 10-bit addressing mode (master mode)" ]
488    pub fn add10(&self) -> bool {
489        const OFFSET: u8 = 11u8;
490        self.bits & (1 << OFFSET) != 0
491    }
492    # [ doc = "Bit 10 - Transfer direction (master mode)" ]
493    pub fn rd_wrn(&self) -> bool {
494        const OFFSET: u8 = 10u8;
495        self.bits & (1 << OFFSET) != 0
496    }
497    # [ doc = "Bits 8:9 - Slave address bit 9:8 (master mode)" ]
498    pub fn sadd8(&self) -> u8 {
499        const MASK: u32 = 3;
500        const OFFSET: u8 = 8u8;
501        ((self.bits >> OFFSET) & MASK) as u8
502    }
503    # [ doc = "Bits 1:7 - Slave address bit 7:1 (master mode)" ]
504    pub fn sadd1(&self) -> u8 {
505        const MASK: u32 = 127;
506        const OFFSET: u8 = 1u8;
507        ((self.bits >> OFFSET) & MASK) as u8
508    }
509    # [ doc = "Bit 0 - Slave address bit 0 (master mode)" ]
510    pub fn sadd0(&self) -> bool {
511        const OFFSET: u8 = 0u8;
512        self.bits & (1 << OFFSET) != 0
513    }
514}
515
516# [ derive ( Clone , Copy ) ]
517# [ repr ( C ) ]
518pub struct Cr2W {
519    bits: u32,
520}
521
522impl Cr2W {
523    # [ doc = r" Reset value" ]
524    pub fn reset_value() -> Self {
525        Cr2W { bits: 0 }
526    }
527    # [ doc = "Bit 26 - Packet error checking byte" ]
528    pub fn pecbyte(&mut self, value: bool) -> &mut Self {
529        const OFFSET: u8 = 26u8;
530        if value {
531            self.bits |= 1 << OFFSET;
532        } else {
533            self.bits &= !(1 << OFFSET);
534        }
535        self
536    }
537    # [ doc = "Bit 25 - Automatic end mode (master mode)" ]
538    pub fn autoend(&mut self, value: bool) -> &mut Self {
539        const OFFSET: u8 = 25u8;
540        if value {
541            self.bits |= 1 << OFFSET;
542        } else {
543            self.bits &= !(1 << OFFSET);
544        }
545        self
546    }
547    # [ doc = "Bit 24 - NBYTES reload mode" ]
548    pub fn reload(&mut self, value: bool) -> &mut Self {
549        const OFFSET: u8 = 24u8;
550        if value {
551            self.bits |= 1 << OFFSET;
552        } else {
553            self.bits &= !(1 << OFFSET);
554        }
555        self
556    }
557    # [ doc = "Bits 16:23 - Number of bytes" ]
558    pub fn nbytes(&mut self, value: u8) -> &mut Self {
559        const OFFSET: u8 = 16u8;
560        const MASK: u8 = 255;
561        self.bits &= !((MASK as u32) << OFFSET);
562        self.bits |= ((value & MASK) as u32) << OFFSET;
563        self
564    }
565    # [ doc = "Bit 15 - NACK generation (slave mode)" ]
566    pub fn nack(&mut self, value: bool) -> &mut Self {
567        const OFFSET: u8 = 15u8;
568        if value {
569            self.bits |= 1 << OFFSET;
570        } else {
571            self.bits &= !(1 << OFFSET);
572        }
573        self
574    }
575    # [ doc = "Bit 14 - Stop generation (master mode)" ]
576    pub fn stop(&mut self, value: bool) -> &mut Self {
577        const OFFSET: u8 = 14u8;
578        if value {
579            self.bits |= 1 << OFFSET;
580        } else {
581            self.bits &= !(1 << OFFSET);
582        }
583        self
584    }
585    # [ doc = "Bit 13 - Start generation" ]
586    pub fn start(&mut self, value: bool) -> &mut Self {
587        const OFFSET: u8 = 13u8;
588        if value {
589            self.bits |= 1 << OFFSET;
590        } else {
591            self.bits &= !(1 << OFFSET);
592        }
593        self
594    }
595    # [ doc = "Bit 12 - 10-bit address header only read direction (master receiver mode)" ]
596    pub fn head10r(&mut self, value: bool) -> &mut Self {
597        const OFFSET: u8 = 12u8;
598        if value {
599            self.bits |= 1 << OFFSET;
600        } else {
601            self.bits &= !(1 << OFFSET);
602        }
603        self
604    }
605    # [ doc = "Bit 11 - 10-bit addressing mode (master mode)" ]
606    pub fn add10(&mut self, value: bool) -> &mut Self {
607        const OFFSET: u8 = 11u8;
608        if value {
609            self.bits |= 1 << OFFSET;
610        } else {
611            self.bits &= !(1 << OFFSET);
612        }
613        self
614    }
615    # [ doc = "Bit 10 - Transfer direction (master mode)" ]
616    pub fn rd_wrn(&mut self, value: bool) -> &mut Self {
617        const OFFSET: u8 = 10u8;
618        if value {
619            self.bits |= 1 << OFFSET;
620        } else {
621            self.bits &= !(1 << OFFSET);
622        }
623        self
624    }
625    # [ doc = "Bits 8:9 - Slave address bit 9:8 (master mode)" ]
626    pub fn sadd8(&mut self, value: u8) -> &mut Self {
627        const OFFSET: u8 = 8u8;
628        const MASK: u8 = 3;
629        self.bits &= !((MASK as u32) << OFFSET);
630        self.bits |= ((value & MASK) as u32) << OFFSET;
631        self
632    }
633    # [ doc = "Bits 1:7 - Slave address bit 7:1 (master mode)" ]
634    pub fn sadd1(&mut self, value: u8) -> &mut Self {
635        const OFFSET: u8 = 1u8;
636        const MASK: u8 = 127;
637        self.bits &= !((MASK as u32) << OFFSET);
638        self.bits |= ((value & MASK) as u32) << OFFSET;
639        self
640    }
641    # [ doc = "Bit 0 - Slave address bit 0 (master mode)" ]
642    pub fn sadd0(&mut self, value: bool) -> &mut Self {
643        const OFFSET: u8 = 0u8;
644        if value {
645            self.bits |= 1 << OFFSET;
646        } else {
647            self.bits &= !(1 << OFFSET);
648        }
649        self
650    }
651}
652
653# [ repr ( C ) ]
654pub struct Oar1 {
655    register: ::volatile_register::RW<u32>,
656}
657
658impl Oar1 {
659    pub fn read_bits(&self) -> u32 {
660        self.register.read()
661    }
662    pub unsafe fn modify_bits<F>(&mut self, f: F)
663        where F: FnOnce(&mut u32)
664    {
665        let mut bits = self.register.read();
666        f(&mut bits);
667        self.register.write(bits);
668    }
669    pub unsafe fn write_bits(&mut self, bits: u32) {
670        self.register.write(bits);
671    }
672    pub fn modify<F>(&mut self, f: F)
673        where for<'w> F: FnOnce(&Oar1R, &'w mut Oar1W) -> &'w mut Oar1W
674    {
675        let bits = self.register.read();
676        let r = Oar1R { bits: bits };
677        let mut w = Oar1W { bits: bits };
678        f(&r, &mut w);
679        self.register.write(w.bits);
680    }
681    pub fn read(&self) -> Oar1R {
682        Oar1R { bits: self.register.read() }
683    }
684    pub fn write<F>(&mut self, f: F)
685        where F: FnOnce(&mut Oar1W) -> &mut Oar1W
686    {
687        let mut w = Oar1W::reset_value();
688        f(&mut w);
689        self.register.write(w.bits);
690    }
691}
692
693# [ derive ( Clone , Copy ) ]
694# [ repr ( C ) ]
695pub struct Oar1R {
696    bits: u32,
697}
698
699impl Oar1R {
700    # [ doc = "Bit 0 - Interface address" ]
701    pub fn oa1_0(&self) -> bool {
702        const OFFSET: u8 = 0u8;
703        self.bits & (1 << OFFSET) != 0
704    }
705    # [ doc = "Bits 1:7 - Interface address" ]
706    pub fn oa1_1(&self) -> u8 {
707        const MASK: u32 = 127;
708        const OFFSET: u8 = 1u8;
709        ((self.bits >> OFFSET) & MASK) as u8
710    }
711    # [ doc = "Bits 8:9 - Interface address" ]
712    pub fn oa1_8(&self) -> u8 {
713        const MASK: u32 = 3;
714        const OFFSET: u8 = 8u8;
715        ((self.bits >> OFFSET) & MASK) as u8
716    }
717    # [ doc = "Bit 10 - Own Address 1 10-bit mode" ]
718    pub fn oa1mode(&self) -> bool {
719        const OFFSET: u8 = 10u8;
720        self.bits & (1 << OFFSET) != 0
721    }
722    # [ doc = "Bit 15 - Own Address 1 enable" ]
723    pub fn oa1en(&self) -> bool {
724        const OFFSET: u8 = 15u8;
725        self.bits & (1 << OFFSET) != 0
726    }
727}
728
729# [ derive ( Clone , Copy ) ]
730# [ repr ( C ) ]
731pub struct Oar1W {
732    bits: u32,
733}
734
735impl Oar1W {
736    # [ doc = r" Reset value" ]
737    pub fn reset_value() -> Self {
738        Oar1W { bits: 0 }
739    }
740    # [ doc = "Bit 0 - Interface address" ]
741    pub fn oa1_0(&mut self, value: bool) -> &mut Self {
742        const OFFSET: u8 = 0u8;
743        if value {
744            self.bits |= 1 << OFFSET;
745        } else {
746            self.bits &= !(1 << OFFSET);
747        }
748        self
749    }
750    # [ doc = "Bits 1:7 - Interface address" ]
751    pub fn oa1_1(&mut self, value: u8) -> &mut Self {
752        const OFFSET: u8 = 1u8;
753        const MASK: u8 = 127;
754        self.bits &= !((MASK as u32) << OFFSET);
755        self.bits |= ((value & MASK) as u32) << OFFSET;
756        self
757    }
758    # [ doc = "Bits 8:9 - Interface address" ]
759    pub fn oa1_8(&mut self, value: u8) -> &mut Self {
760        const OFFSET: u8 = 8u8;
761        const MASK: u8 = 3;
762        self.bits &= !((MASK as u32) << OFFSET);
763        self.bits |= ((value & MASK) as u32) << OFFSET;
764        self
765    }
766    # [ doc = "Bit 10 - Own Address 1 10-bit mode" ]
767    pub fn oa1mode(&mut self, value: bool) -> &mut Self {
768        const OFFSET: u8 = 10u8;
769        if value {
770            self.bits |= 1 << OFFSET;
771        } else {
772            self.bits &= !(1 << OFFSET);
773        }
774        self
775    }
776    # [ doc = "Bit 15 - Own Address 1 enable" ]
777    pub fn oa1en(&mut self, value: bool) -> &mut Self {
778        const OFFSET: u8 = 15u8;
779        if value {
780            self.bits |= 1 << OFFSET;
781        } else {
782            self.bits &= !(1 << OFFSET);
783        }
784        self
785    }
786}
787
788# [ repr ( C ) ]
789pub struct Oar2 {
790    register: ::volatile_register::RW<u32>,
791}
792
793impl Oar2 {
794    pub fn read_bits(&self) -> u32 {
795        self.register.read()
796    }
797    pub unsafe fn modify_bits<F>(&mut self, f: F)
798        where F: FnOnce(&mut u32)
799    {
800        let mut bits = self.register.read();
801        f(&mut bits);
802        self.register.write(bits);
803    }
804    pub unsafe fn write_bits(&mut self, bits: u32) {
805        self.register.write(bits);
806    }
807    pub fn modify<F>(&mut self, f: F)
808        where for<'w> F: FnOnce(&Oar2R, &'w mut Oar2W) -> &'w mut Oar2W
809    {
810        let bits = self.register.read();
811        let r = Oar2R { bits: bits };
812        let mut w = Oar2W { bits: bits };
813        f(&r, &mut w);
814        self.register.write(w.bits);
815    }
816    pub fn read(&self) -> Oar2R {
817        Oar2R { bits: self.register.read() }
818    }
819    pub fn write<F>(&mut self, f: F)
820        where F: FnOnce(&mut Oar2W) -> &mut Oar2W
821    {
822        let mut w = Oar2W::reset_value();
823        f(&mut w);
824        self.register.write(w.bits);
825    }
826}
827
828# [ derive ( Clone , Copy ) ]
829# [ repr ( C ) ]
830pub struct Oar2R {
831    bits: u32,
832}
833
834impl Oar2R {
835    # [ doc = "Bits 1:7 - Interface address" ]
836    pub fn oa2(&self) -> u8 {
837        const MASK: u32 = 127;
838        const OFFSET: u8 = 1u8;
839        ((self.bits >> OFFSET) & MASK) as u8
840    }
841    # [ doc = "Bits 8:10 - Own Address 2 masks" ]
842    pub fn oa2msk(&self) -> u8 {
843        const MASK: u32 = 7;
844        const OFFSET: u8 = 8u8;
845        ((self.bits >> OFFSET) & MASK) as u8
846    }
847    # [ doc = "Bit 15 - Own Address 2 enable" ]
848    pub fn oa2en(&self) -> bool {
849        const OFFSET: u8 = 15u8;
850        self.bits & (1 << OFFSET) != 0
851    }
852}
853
854# [ derive ( Clone , Copy ) ]
855# [ repr ( C ) ]
856pub struct Oar2W {
857    bits: u32,
858}
859
860impl Oar2W {
861    # [ doc = r" Reset value" ]
862    pub fn reset_value() -> Self {
863        Oar2W { bits: 0 }
864    }
865    # [ doc = "Bits 1:7 - Interface address" ]
866    pub fn oa2(&mut self, value: u8) -> &mut Self {
867        const OFFSET: u8 = 1u8;
868        const MASK: u8 = 127;
869        self.bits &= !((MASK as u32) << OFFSET);
870        self.bits |= ((value & MASK) as u32) << OFFSET;
871        self
872    }
873    # [ doc = "Bits 8:10 - Own Address 2 masks" ]
874    pub fn oa2msk(&mut self, value: u8) -> &mut Self {
875        const OFFSET: u8 = 8u8;
876        const MASK: u8 = 7;
877        self.bits &= !((MASK as u32) << OFFSET);
878        self.bits |= ((value & MASK) as u32) << OFFSET;
879        self
880    }
881    # [ doc = "Bit 15 - Own Address 2 enable" ]
882    pub fn oa2en(&mut self, value: bool) -> &mut Self {
883        const OFFSET: u8 = 15u8;
884        if value {
885            self.bits |= 1 << OFFSET;
886        } else {
887            self.bits &= !(1 << OFFSET);
888        }
889        self
890    }
891}
892
893# [ repr ( C ) ]
894pub struct Timingr {
895    register: ::volatile_register::RW<u32>,
896}
897
898impl Timingr {
899    pub fn read_bits(&self) -> u32 {
900        self.register.read()
901    }
902    pub unsafe fn modify_bits<F>(&mut self, f: F)
903        where F: FnOnce(&mut u32)
904    {
905        let mut bits = self.register.read();
906        f(&mut bits);
907        self.register.write(bits);
908    }
909    pub unsafe fn write_bits(&mut self, bits: u32) {
910        self.register.write(bits);
911    }
912    pub fn modify<F>(&mut self, f: F)
913        where for<'w> F: FnOnce(&TimingrR, &'w mut TimingrW) -> &'w mut TimingrW
914    {
915        let bits = self.register.read();
916        let r = TimingrR { bits: bits };
917        let mut w = TimingrW { bits: bits };
918        f(&r, &mut w);
919        self.register.write(w.bits);
920    }
921    pub fn read(&self) -> TimingrR {
922        TimingrR { bits: self.register.read() }
923    }
924    pub fn write<F>(&mut self, f: F)
925        where F: FnOnce(&mut TimingrW) -> &mut TimingrW
926    {
927        let mut w = TimingrW::reset_value();
928        f(&mut w);
929        self.register.write(w.bits);
930    }
931}
932
933# [ derive ( Clone , Copy ) ]
934# [ repr ( C ) ]
935pub struct TimingrR {
936    bits: u32,
937}
938
939impl TimingrR {
940    # [ doc = "Bits 0:7 - SCL low period (master mode)" ]
941    pub fn scll(&self) -> u8 {
942        const MASK: u32 = 255;
943        const OFFSET: u8 = 0u8;
944        ((self.bits >> OFFSET) & MASK) as u8
945    }
946    # [ doc = "Bits 8:15 - SCL high period (master mode)" ]
947    pub fn sclh(&self) -> u8 {
948        const MASK: u32 = 255;
949        const OFFSET: u8 = 8u8;
950        ((self.bits >> OFFSET) & MASK) as u8
951    }
952    # [ doc = "Bits 16:19 - Data hold time" ]
953    pub fn sdadel(&self) -> u8 {
954        const MASK: u32 = 15;
955        const OFFSET: u8 = 16u8;
956        ((self.bits >> OFFSET) & MASK) as u8
957    }
958    # [ doc = "Bits 20:23 - Data setup time" ]
959    pub fn scldel(&self) -> u8 {
960        const MASK: u32 = 15;
961        const OFFSET: u8 = 20u8;
962        ((self.bits >> OFFSET) & MASK) as u8
963    }
964    # [ doc = "Bits 28:31 - Timing prescaler" ]
965    pub fn presc(&self) -> u8 {
966        const MASK: u32 = 15;
967        const OFFSET: u8 = 28u8;
968        ((self.bits >> OFFSET) & MASK) as u8
969    }
970}
971
972# [ derive ( Clone , Copy ) ]
973# [ repr ( C ) ]
974pub struct TimingrW {
975    bits: u32,
976}
977
978impl TimingrW {
979    # [ doc = r" Reset value" ]
980    pub fn reset_value() -> Self {
981        TimingrW { bits: 0 }
982    }
983    # [ doc = "Bits 0:7 - SCL low period (master mode)" ]
984    pub fn scll(&mut self, value: u8) -> &mut Self {
985        const OFFSET: u8 = 0u8;
986        const MASK: u8 = 255;
987        self.bits &= !((MASK as u32) << OFFSET);
988        self.bits |= ((value & MASK) as u32) << OFFSET;
989        self
990    }
991    # [ doc = "Bits 8:15 - SCL high period (master mode)" ]
992    pub fn sclh(&mut self, value: u8) -> &mut Self {
993        const OFFSET: u8 = 8u8;
994        const MASK: u8 = 255;
995        self.bits &= !((MASK as u32) << OFFSET);
996        self.bits |= ((value & MASK) as u32) << OFFSET;
997        self
998    }
999    # [ doc = "Bits 16:19 - Data hold time" ]
1000    pub fn sdadel(&mut self, value: u8) -> &mut Self {
1001        const OFFSET: u8 = 16u8;
1002        const MASK: u8 = 15;
1003        self.bits &= !((MASK as u32) << OFFSET);
1004        self.bits |= ((value & MASK) as u32) << OFFSET;
1005        self
1006    }
1007    # [ doc = "Bits 20:23 - Data setup time" ]
1008    pub fn scldel(&mut self, value: u8) -> &mut Self {
1009        const OFFSET: u8 = 20u8;
1010        const MASK: u8 = 15;
1011        self.bits &= !((MASK as u32) << OFFSET);
1012        self.bits |= ((value & MASK) as u32) << OFFSET;
1013        self
1014    }
1015    # [ doc = "Bits 28:31 - Timing prescaler" ]
1016    pub fn presc(&mut self, value: u8) -> &mut Self {
1017        const OFFSET: u8 = 28u8;
1018        const MASK: u8 = 15;
1019        self.bits &= !((MASK as u32) << OFFSET);
1020        self.bits |= ((value & MASK) as u32) << OFFSET;
1021        self
1022    }
1023}
1024
1025# [ repr ( C ) ]
1026pub struct Timeoutr {
1027    register: ::volatile_register::RW<u32>,
1028}
1029
1030impl Timeoutr {
1031    pub fn read_bits(&self) -> u32 {
1032        self.register.read()
1033    }
1034    pub unsafe fn modify_bits<F>(&mut self, f: F)
1035        where F: FnOnce(&mut u32)
1036    {
1037        let mut bits = self.register.read();
1038        f(&mut bits);
1039        self.register.write(bits);
1040    }
1041    pub unsafe fn write_bits(&mut self, bits: u32) {
1042        self.register.write(bits);
1043    }
1044    pub fn modify<F>(&mut self, f: F)
1045        where for<'w> F: FnOnce(&TimeoutrR, &'w mut TimeoutrW)
1046                                -> &'w mut TimeoutrW
1047    {
1048        let bits = self.register.read();
1049        let r = TimeoutrR { bits: bits };
1050        let mut w = TimeoutrW { bits: bits };
1051        f(&r, &mut w);
1052        self.register.write(w.bits);
1053    }
1054    pub fn read(&self) -> TimeoutrR {
1055        TimeoutrR { bits: self.register.read() }
1056    }
1057    pub fn write<F>(&mut self, f: F)
1058        where F: FnOnce(&mut TimeoutrW) -> &mut TimeoutrW
1059    {
1060        let mut w = TimeoutrW::reset_value();
1061        f(&mut w);
1062        self.register.write(w.bits);
1063    }
1064}
1065
1066# [ derive ( Clone , Copy ) ]
1067# [ repr ( C ) ]
1068pub struct TimeoutrR {
1069    bits: u32,
1070}
1071
1072impl TimeoutrR {
1073    # [ doc = "Bits 0:11 - Bus timeout A" ]
1074    pub fn timeouta(&self) -> u16 {
1075        const MASK: u32 = 4095;
1076        const OFFSET: u8 = 0u8;
1077        ((self.bits >> OFFSET) & MASK) as u16
1078    }
1079    # [ doc = "Bit 12 - Idle clock timeout detection" ]
1080    pub fn tidle(&self) -> bool {
1081        const OFFSET: u8 = 12u8;
1082        self.bits & (1 << OFFSET) != 0
1083    }
1084    # [ doc = "Bit 15 - Clock timeout enable" ]
1085    pub fn timouten(&self) -> bool {
1086        const OFFSET: u8 = 15u8;
1087        self.bits & (1 << OFFSET) != 0
1088    }
1089    # [ doc = "Bits 16:27 - Bus timeout B" ]
1090    pub fn timeoutb(&self) -> u16 {
1091        const MASK: u32 = 4095;
1092        const OFFSET: u8 = 16u8;
1093        ((self.bits >> OFFSET) & MASK) as u16
1094    }
1095    # [ doc = "Bit 31 - Extended clock timeout enable" ]
1096    pub fn texten(&self) -> bool {
1097        const OFFSET: u8 = 31u8;
1098        self.bits & (1 << OFFSET) != 0
1099    }
1100}
1101
1102# [ derive ( Clone , Copy ) ]
1103# [ repr ( C ) ]
1104pub struct TimeoutrW {
1105    bits: u32,
1106}
1107
1108impl TimeoutrW {
1109    # [ doc = r" Reset value" ]
1110    pub fn reset_value() -> Self {
1111        TimeoutrW { bits: 0 }
1112    }
1113    # [ doc = "Bits 0:11 - Bus timeout A" ]
1114    pub fn timeouta(&mut self, value: u16) -> &mut Self {
1115        const OFFSET: u8 = 0u8;
1116        const MASK: u16 = 4095;
1117        self.bits &= !((MASK as u32) << OFFSET);
1118        self.bits |= ((value & MASK) as u32) << OFFSET;
1119        self
1120    }
1121    # [ doc = "Bit 12 - Idle clock timeout detection" ]
1122    pub fn tidle(&mut self, value: bool) -> &mut Self {
1123        const OFFSET: u8 = 12u8;
1124        if value {
1125            self.bits |= 1 << OFFSET;
1126        } else {
1127            self.bits &= !(1 << OFFSET);
1128        }
1129        self
1130    }
1131    # [ doc = "Bit 15 - Clock timeout enable" ]
1132    pub fn timouten(&mut self, value: bool) -> &mut Self {
1133        const OFFSET: u8 = 15u8;
1134        if value {
1135            self.bits |= 1 << OFFSET;
1136        } else {
1137            self.bits &= !(1 << OFFSET);
1138        }
1139        self
1140    }
1141    # [ doc = "Bits 16:27 - Bus timeout B" ]
1142    pub fn timeoutb(&mut self, value: u16) -> &mut Self {
1143        const OFFSET: u8 = 16u8;
1144        const MASK: u16 = 4095;
1145        self.bits &= !((MASK as u32) << OFFSET);
1146        self.bits |= ((value & MASK) as u32) << OFFSET;
1147        self
1148    }
1149    # [ doc = "Bit 31 - Extended clock timeout enable" ]
1150    pub fn texten(&mut self, value: bool) -> &mut Self {
1151        const OFFSET: u8 = 31u8;
1152        if value {
1153            self.bits |= 1 << OFFSET;
1154        } else {
1155            self.bits &= !(1 << OFFSET);
1156        }
1157        self
1158    }
1159}
1160
1161# [ repr ( C ) ]
1162pub struct Isr {
1163    register: ::volatile_register::RW<u32>,
1164}
1165
1166impl Isr {
1167    pub fn read_bits(&self) -> u32 {
1168        self.register.read()
1169    }
1170    pub unsafe fn modify_bits<F>(&mut self, f: F)
1171        where F: FnOnce(&mut u32)
1172    {
1173        let mut bits = self.register.read();
1174        f(&mut bits);
1175        self.register.write(bits);
1176    }
1177    pub unsafe fn write_bits(&mut self, bits: u32) {
1178        self.register.write(bits);
1179    }
1180    pub fn modify<F>(&mut self, f: F)
1181        where for<'w> F: FnOnce(&IsrR, &'w mut IsrW) -> &'w mut IsrW
1182    {
1183        let bits = self.register.read();
1184        let r = IsrR { bits: bits };
1185        let mut w = IsrW { bits: bits };
1186        f(&r, &mut w);
1187        self.register.write(w.bits);
1188    }
1189    pub fn read(&self) -> IsrR {
1190        IsrR { bits: self.register.read() }
1191    }
1192    pub fn write<F>(&mut self, f: F)
1193        where F: FnOnce(&mut IsrW) -> &mut IsrW
1194    {
1195        let mut w = IsrW::reset_value();
1196        f(&mut w);
1197        self.register.write(w.bits);
1198    }
1199}
1200
1201# [ derive ( Clone , Copy ) ]
1202# [ repr ( C ) ]
1203pub struct IsrR {
1204    bits: u32,
1205}
1206
1207impl IsrR {
1208    # [ doc = "Bits 17:23 - Address match code (Slave mode)" ]
1209    pub fn addcode(&self) -> u8 {
1210        const MASK: u32 = 127;
1211        const OFFSET: u8 = 17u8;
1212        ((self.bits >> OFFSET) & MASK) as u8
1213    }
1214    # [ doc = "Bit 16 - Transfer direction (Slave mode)" ]
1215    pub fn dir(&self) -> bool {
1216        const OFFSET: u8 = 16u8;
1217        self.bits & (1 << OFFSET) != 0
1218    }
1219    # [ doc = "Bit 15 - Bus busy" ]
1220    pub fn busy(&self) -> bool {
1221        const OFFSET: u8 = 15u8;
1222        self.bits & (1 << OFFSET) != 0
1223    }
1224    # [ doc = "Bit 13 - SMBus alert" ]
1225    pub fn alert(&self) -> bool {
1226        const OFFSET: u8 = 13u8;
1227        self.bits & (1 << OFFSET) != 0
1228    }
1229    # [ doc = "Bit 12 - Timeout or t_low detection flag" ]
1230    pub fn timeout(&self) -> bool {
1231        const OFFSET: u8 = 12u8;
1232        self.bits & (1 << OFFSET) != 0
1233    }
1234    # [ doc = "Bit 11 - PEC Error in reception" ]
1235    pub fn pecerr(&self) -> bool {
1236        const OFFSET: u8 = 11u8;
1237        self.bits & (1 << OFFSET) != 0
1238    }
1239    # [ doc = "Bit 10 - Overrun/Underrun (slave mode)" ]
1240    pub fn ovr(&self) -> bool {
1241        const OFFSET: u8 = 10u8;
1242        self.bits & (1 << OFFSET) != 0
1243    }
1244    # [ doc = "Bit 9 - Arbitration lost" ]
1245    pub fn arlo(&self) -> bool {
1246        const OFFSET: u8 = 9u8;
1247        self.bits & (1 << OFFSET) != 0
1248    }
1249    # [ doc = "Bit 8 - Bus error" ]
1250    pub fn berr(&self) -> bool {
1251        const OFFSET: u8 = 8u8;
1252        self.bits & (1 << OFFSET) != 0
1253    }
1254    # [ doc = "Bit 7 - Transfer Complete Reload" ]
1255    pub fn tcr(&self) -> bool {
1256        const OFFSET: u8 = 7u8;
1257        self.bits & (1 << OFFSET) != 0
1258    }
1259    # [ doc = "Bit 6 - Transfer Complete (master mode)" ]
1260    pub fn tc(&self) -> bool {
1261        const OFFSET: u8 = 6u8;
1262        self.bits & (1 << OFFSET) != 0
1263    }
1264    # [ doc = "Bit 5 - Stop detection flag" ]
1265    pub fn stopf(&self) -> bool {
1266        const OFFSET: u8 = 5u8;
1267        self.bits & (1 << OFFSET) != 0
1268    }
1269    # [ doc = "Bit 4 - Not acknowledge received flag" ]
1270    pub fn nackf(&self) -> bool {
1271        const OFFSET: u8 = 4u8;
1272        self.bits & (1 << OFFSET) != 0
1273    }
1274    # [ doc = "Bit 3 - Address matched (slave mode)" ]
1275    pub fn addr(&self) -> bool {
1276        const OFFSET: u8 = 3u8;
1277        self.bits & (1 << OFFSET) != 0
1278    }
1279    # [ doc = "Bit 2 - Receive data register not empty (receivers)" ]
1280    pub fn rxne(&self) -> bool {
1281        const OFFSET: u8 = 2u8;
1282        self.bits & (1 << OFFSET) != 0
1283    }
1284    # [ doc = "Bit 1 - Transmit interrupt status (transmitters)" ]
1285    pub fn txis(&self) -> bool {
1286        const OFFSET: u8 = 1u8;
1287        self.bits & (1 << OFFSET) != 0
1288    }
1289    # [ doc = "Bit 0 - Transmit data register empty (transmitters)" ]
1290    pub fn txe(&self) -> bool {
1291        const OFFSET: u8 = 0u8;
1292        self.bits & (1 << OFFSET) != 0
1293    }
1294}
1295
1296# [ derive ( Clone , Copy ) ]
1297# [ repr ( C ) ]
1298pub struct IsrW {
1299    bits: u32,
1300}
1301
1302impl IsrW {
1303    # [ doc = r" Reset value" ]
1304    pub fn reset_value() -> Self {
1305        IsrW { bits: 1 }
1306    }
1307    # [ doc = "Bit 1 - Transmit interrupt status (transmitters)" ]
1308    pub fn txis(&mut self, value: bool) -> &mut Self {
1309        const OFFSET: u8 = 1u8;
1310        if value {
1311            self.bits |= 1 << OFFSET;
1312        } else {
1313            self.bits &= !(1 << OFFSET);
1314        }
1315        self
1316    }
1317    # [ doc = "Bit 0 - Transmit data register empty (transmitters)" ]
1318    pub fn txe(&mut self, value: bool) -> &mut Self {
1319        const OFFSET: u8 = 0u8;
1320        if value {
1321            self.bits |= 1 << OFFSET;
1322        } else {
1323            self.bits &= !(1 << OFFSET);
1324        }
1325        self
1326    }
1327}
1328
1329# [ repr ( C ) ]
1330pub struct Icr {
1331    register: ::volatile_register::WO<u32>,
1332}
1333
1334impl Icr {
1335    pub unsafe fn write_bits(&mut self, bits: u32) {
1336        self.register.write(bits);
1337    }
1338    pub fn write<F>(&self, f: F)
1339        where F: FnOnce(&mut IcrW) -> &mut IcrW
1340    {
1341        let mut w = IcrW::reset_value();
1342        f(&mut w);
1343        self.register.write(w.bits);
1344    }
1345}
1346
1347# [ derive ( Clone , Copy ) ]
1348# [ repr ( C ) ]
1349pub struct IcrW {
1350    bits: u32,
1351}
1352
1353impl IcrW {
1354    # [ doc = r" Reset value" ]
1355    pub fn reset_value() -> Self {
1356        IcrW { bits: 0 }
1357    }
1358    # [ doc = "Bit 13 - Alert flag clear" ]
1359    pub fn alertcf(&mut self, value: bool) -> &mut Self {
1360        const OFFSET: u8 = 13u8;
1361        if value {
1362            self.bits |= 1 << OFFSET;
1363        } else {
1364            self.bits &= !(1 << OFFSET);
1365        }
1366        self
1367    }
1368    # [ doc = "Bit 12 - Timeout detection flag clear" ]
1369    pub fn timoutcf(&mut self, value: bool) -> &mut Self {
1370        const OFFSET: u8 = 12u8;
1371        if value {
1372            self.bits |= 1 << OFFSET;
1373        } else {
1374            self.bits &= !(1 << OFFSET);
1375        }
1376        self
1377    }
1378    # [ doc = "Bit 11 - PEC Error flag clear" ]
1379    pub fn peccf(&mut self, value: bool) -> &mut Self {
1380        const OFFSET: u8 = 11u8;
1381        if value {
1382            self.bits |= 1 << OFFSET;
1383        } else {
1384            self.bits &= !(1 << OFFSET);
1385        }
1386        self
1387    }
1388    # [ doc = "Bit 10 - Overrun/Underrun flag clear" ]
1389    pub fn ovrcf(&mut self, value: bool) -> &mut Self {
1390        const OFFSET: u8 = 10u8;
1391        if value {
1392            self.bits |= 1 << OFFSET;
1393        } else {
1394            self.bits &= !(1 << OFFSET);
1395        }
1396        self
1397    }
1398    # [ doc = "Bit 9 - Arbitration lost flag clear" ]
1399    pub fn arlocf(&mut self, value: bool) -> &mut Self {
1400        const OFFSET: u8 = 9u8;
1401        if value {
1402            self.bits |= 1 << OFFSET;
1403        } else {
1404            self.bits &= !(1 << OFFSET);
1405        }
1406        self
1407    }
1408    # [ doc = "Bit 8 - Bus error flag clear" ]
1409    pub fn berrcf(&mut self, value: bool) -> &mut Self {
1410        const OFFSET: u8 = 8u8;
1411        if value {
1412            self.bits |= 1 << OFFSET;
1413        } else {
1414            self.bits &= !(1 << OFFSET);
1415        }
1416        self
1417    }
1418    # [ doc = "Bit 5 - Stop detection flag clear" ]
1419    pub fn stopcf(&mut self, value: bool) -> &mut Self {
1420        const OFFSET: u8 = 5u8;
1421        if value {
1422            self.bits |= 1 << OFFSET;
1423        } else {
1424            self.bits &= !(1 << OFFSET);
1425        }
1426        self
1427    }
1428    # [ doc = "Bit 4 - Not Acknowledge flag clear" ]
1429    pub fn nackcf(&mut self, value: bool) -> &mut Self {
1430        const OFFSET: u8 = 4u8;
1431        if value {
1432            self.bits |= 1 << OFFSET;
1433        } else {
1434            self.bits &= !(1 << OFFSET);
1435        }
1436        self
1437    }
1438    # [ doc = "Bit 3 - Address Matched flag clear" ]
1439    pub fn addrcf(&mut self, value: bool) -> &mut Self {
1440        const OFFSET: u8 = 3u8;
1441        if value {
1442            self.bits |= 1 << OFFSET;
1443        } else {
1444            self.bits &= !(1 << OFFSET);
1445        }
1446        self
1447    }
1448}
1449
1450# [ repr ( C ) ]
1451pub struct Pecr {
1452    register: ::volatile_register::RO<u32>,
1453}
1454
1455impl Pecr {
1456    pub fn read_bits(&self) -> u32 {
1457        self.register.read()
1458    }
1459    pub fn read(&self) -> PecrR {
1460        PecrR { bits: self.register.read() }
1461    }
1462}
1463
1464# [ derive ( Clone , Copy ) ]
1465# [ repr ( C ) ]
1466pub struct PecrR {
1467    bits: u32,
1468}
1469
1470impl PecrR {
1471    # [ doc = "Bits 0:7 - Packet error checking register" ]
1472    pub fn pec(&self) -> u8 {
1473        const MASK: u32 = 255;
1474        const OFFSET: u8 = 0u8;
1475        ((self.bits >> OFFSET) & MASK) as u8
1476    }
1477}
1478
1479# [ repr ( C ) ]
1480pub struct Rxdr {
1481    register: ::volatile_register::RO<u32>,
1482}
1483
1484impl Rxdr {
1485    pub fn read_bits(&self) -> u32 {
1486        self.register.read()
1487    }
1488    pub fn read(&self) -> RxdrR {
1489        RxdrR { bits: self.register.read() }
1490    }
1491}
1492
1493# [ derive ( Clone , Copy ) ]
1494# [ repr ( C ) ]
1495pub struct RxdrR {
1496    bits: u32,
1497}
1498
1499impl RxdrR {
1500    # [ doc = "Bits 0:7 - 8-bit receive data" ]
1501    pub fn rxdata(&self) -> u8 {
1502        const MASK: u32 = 255;
1503        const OFFSET: u8 = 0u8;
1504        ((self.bits >> OFFSET) & MASK) as u8
1505    }
1506}
1507
1508# [ repr ( C ) ]
1509pub struct Txdr {
1510    register: ::volatile_register::RW<u32>,
1511}
1512
1513impl Txdr {
1514    pub fn read_bits(&self) -> u32 {
1515        self.register.read()
1516    }
1517    pub unsafe fn modify_bits<F>(&mut self, f: F)
1518        where F: FnOnce(&mut u32)
1519    {
1520        let mut bits = self.register.read();
1521        f(&mut bits);
1522        self.register.write(bits);
1523    }
1524    pub unsafe fn write_bits(&mut self, bits: u32) {
1525        self.register.write(bits);
1526    }
1527    pub fn modify<F>(&mut self, f: F)
1528        where for<'w> F: FnOnce(&TxdrR, &'w mut TxdrW) -> &'w mut TxdrW
1529    {
1530        let bits = self.register.read();
1531        let r = TxdrR { bits: bits };
1532        let mut w = TxdrW { bits: bits };
1533        f(&r, &mut w);
1534        self.register.write(w.bits);
1535    }
1536    pub fn read(&self) -> TxdrR {
1537        TxdrR { bits: self.register.read() }
1538    }
1539    pub fn write<F>(&mut self, f: F)
1540        where F: FnOnce(&mut TxdrW) -> &mut TxdrW
1541    {
1542        let mut w = TxdrW::reset_value();
1543        f(&mut w);
1544        self.register.write(w.bits);
1545    }
1546}
1547
1548# [ derive ( Clone , Copy ) ]
1549# [ repr ( C ) ]
1550pub struct TxdrR {
1551    bits: u32,
1552}
1553
1554impl TxdrR {
1555    # [ doc = "Bits 0:7 - 8-bit transmit data" ]
1556    pub fn txdata(&self) -> u8 {
1557        const MASK: u32 = 255;
1558        const OFFSET: u8 = 0u8;
1559        ((self.bits >> OFFSET) & MASK) as u8
1560    }
1561}
1562
1563# [ derive ( Clone , Copy ) ]
1564# [ repr ( C ) ]
1565pub struct TxdrW {
1566    bits: u32,
1567}
1568
1569impl TxdrW {
1570    # [ doc = r" Reset value" ]
1571    pub fn reset_value() -> Self {
1572        TxdrW { bits: 0 }
1573    }
1574    # [ doc = "Bits 0:7 - 8-bit transmit data" ]
1575    pub fn txdata(&mut self, value: u8) -> &mut Self {
1576        const OFFSET: u8 = 0u8;
1577        const MASK: u8 = 255;
1578        self.bits &= !((MASK as u32) << OFFSET);
1579        self.bits |= ((value & MASK) as u32) << OFFSET;
1580        self
1581    }
1582}
stm32f30x_memory_map/i2c.rs

stm32f30x_memory_map/
i2c.rs
