stm32f3/stm32f373/tim13/
ccmr1_output.rs

1///Register `CCMR1_Output` reader
2pub type R = crate::R<CCMR1_OUTPUTrs>;
3///Register `CCMR1_Output` writer
4pub type W = crate::W<CCMR1_OUTPUTrs>;
5/**Capture/Compare %s selection
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10#[repr(u8)]
11pub enum CC1S {
12    ///0: CCx channel is configured as output
13    Output = 0,
14}
15impl From<CC1S> for u8 {
16    #[inline(always)]
17    fn from(variant: CC1S) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for CC1S {
22    type Ux = u8;
23}
24impl crate::IsEnum for CC1S {}
25///Field `CCS(1-1)` reader - Capture/Compare %s selection
26pub type CCS_R = crate::FieldReader<CC1S>;
27impl CCS_R {
28    ///Get enumerated values variant
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<CC1S> {
31        match self.bits {
32            0 => Some(CC1S::Output),
33            _ => None,
34        }
35    }
36    ///CCx channel is configured as output
37    #[inline(always)]
38    pub fn is_output(&self) -> bool {
39        *self == CC1S::Output
40    }
41}
42///Field `CCS(1-1)` writer - Capture/Compare %s selection
43pub type CCS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, CC1S>;
44impl<'a, REG> CCS_W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47    REG::Ux: From<u8>,
48{
49    ///CCx channel is configured as output
50    #[inline(always)]
51    pub fn output(self) -> &'a mut crate::W<REG> {
52        self.variant(CC1S::Output)
53    }
54}
55/**Output compare %s fast enable
56
57Value on reset: 0*/
58#[cfg_attr(feature = "defmt", derive(defmt::Format))]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum OC1FE {
61    ///0: Fast output disabled
62    Disabled = 0,
63    ///1: Fast output enabled
64    Enabled = 1,
65}
66impl From<OC1FE> for bool {
67    #[inline(always)]
68    fn from(variant: OC1FE) -> Self {
69        variant as u8 != 0
70    }
71}
72///Field `OCFE(1-1)` reader - Output compare %s fast enable
73pub type OCFE_R = crate::BitReader<OC1FE>;
74impl OCFE_R {
75    ///Get enumerated values variant
76    #[inline(always)]
77    pub const fn variant(&self) -> OC1FE {
78        match self.bits {
79            false => OC1FE::Disabled,
80            true => OC1FE::Enabled,
81        }
82    }
83    ///Fast output disabled
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == OC1FE::Disabled
87    }
88    ///Fast output enabled
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == OC1FE::Enabled
92    }
93}
94///Field `OCFE(1-1)` writer - Output compare %s fast enable
95pub type OCFE_W<'a, REG> = crate::BitWriter<'a, REG, OC1FE>;
96impl<'a, REG> OCFE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    ///Fast output disabled
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(OC1FE::Disabled)
104    }
105    ///Fast output enabled
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(OC1FE::Enabled)
109    }
110}
111/**Output compare %s preload enable
112
113Value on reset: 0*/
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum OC1PE {
117    ///0: Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
118    Disabled = 0,
119    ///1: Preload register on CCRx enabled. Preload value is loaded into active register on each update event
120    Enabled = 1,
121}
122impl From<OC1PE> for bool {
123    #[inline(always)]
124    fn from(variant: OC1PE) -> Self {
125        variant as u8 != 0
126    }
127}
128///Field `OCPE(1-1)` reader - Output compare %s preload enable
129pub type OCPE_R = crate::BitReader<OC1PE>;
130impl OCPE_R {
131    ///Get enumerated values variant
132    #[inline(always)]
133    pub const fn variant(&self) -> OC1PE {
134        match self.bits {
135            false => OC1PE::Disabled,
136            true => OC1PE::Enabled,
137        }
138    }
139    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == OC1PE::Disabled
143    }
144    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == OC1PE::Enabled
148    }
149}
150///Field `OCPE(1-1)` writer - Output compare %s preload enable
151pub type OCPE_W<'a, REG> = crate::BitWriter<'a, REG, OC1PE>;
152impl<'a, REG> OCPE_W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    ///Preload register on CCRx disabled. New values written to CCRx are taken into account immediately
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(OC1PE::Disabled)
160    }
161    ///Preload register on CCRx enabled. Preload value is loaded into active register on each update event
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(OC1PE::Enabled)
165    }
166}
167/**Output compare %s mode
168
169Value on reset: 0*/
170#[cfg_attr(feature = "defmt", derive(defmt::Format))]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum OC1M {
174    ///0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
175    Frozen = 0,
176    ///1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
177    ActiveOnMatch = 1,
178    ///2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
179    InactiveOnMatch = 2,
180    ///3: OCyREF toggles when TIMx_CNT=TIMx_CCRy
181    Toggle = 3,
182    ///4: OCyREF is forced low
183    ForceInactive = 4,
184    ///5: OCyREF is forced high
185    ForceActive = 5,
186    ///6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
187    PwmMode1 = 6,
188    ///7: Inversely to PwmMode1
189    PwmMode2 = 7,
190}
191impl From<OC1M> for u8 {
192    #[inline(always)]
193    fn from(variant: OC1M) -> Self {
194        variant as _
195    }
196}
197impl crate::FieldSpec for OC1M {
198    type Ux = u8;
199}
200impl crate::IsEnum for OC1M {}
201///Field `OCM(1-1)` reader - Output compare %s mode
202pub type OCM_R = crate::FieldReader<OC1M>;
203impl OCM_R {
204    ///Get enumerated values variant
205    #[inline(always)]
206    pub const fn variant(&self) -> OC1M {
207        match self.bits {
208            0 => OC1M::Frozen,
209            1 => OC1M::ActiveOnMatch,
210            2 => OC1M::InactiveOnMatch,
211            3 => OC1M::Toggle,
212            4 => OC1M::ForceInactive,
213            5 => OC1M::ForceActive,
214            6 => OC1M::PwmMode1,
215            7 => OC1M::PwmMode2,
216            _ => unreachable!(),
217        }
218    }
219    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
220    #[inline(always)]
221    pub fn is_frozen(&self) -> bool {
222        *self == OC1M::Frozen
223    }
224    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
225    #[inline(always)]
226    pub fn is_active_on_match(&self) -> bool {
227        *self == OC1M::ActiveOnMatch
228    }
229    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
230    #[inline(always)]
231    pub fn is_inactive_on_match(&self) -> bool {
232        *self == OC1M::InactiveOnMatch
233    }
234    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy
235    #[inline(always)]
236    pub fn is_toggle(&self) -> bool {
237        *self == OC1M::Toggle
238    }
239    ///OCyREF is forced low
240    #[inline(always)]
241    pub fn is_force_inactive(&self) -> bool {
242        *self == OC1M::ForceInactive
243    }
244    ///OCyREF is forced high
245    #[inline(always)]
246    pub fn is_force_active(&self) -> bool {
247        *self == OC1M::ForceActive
248    }
249    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
250    #[inline(always)]
251    pub fn is_pwm_mode1(&self) -> bool {
252        *self == OC1M::PwmMode1
253    }
254    ///Inversely to PwmMode1
255    #[inline(always)]
256    pub fn is_pwm_mode2(&self) -> bool {
257        *self == OC1M::PwmMode2
258    }
259}
260///Field `OCM(1-1)` writer - Output compare %s mode
261pub type OCM_W<'a, REG> = crate::FieldWriter<'a, REG, 3, OC1M, crate::Safe>;
262impl<'a, REG> OCM_W<'a, REG>
263where
264    REG: crate::Writable + crate::RegisterSpec,
265    REG::Ux: From<u8>,
266{
267    ///The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
268    #[inline(always)]
269    pub fn frozen(self) -> &'a mut crate::W<REG> {
270        self.variant(OC1M::Frozen)
271    }
272    ///Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
273    #[inline(always)]
274    pub fn active_on_match(self) -> &'a mut crate::W<REG> {
275        self.variant(OC1M::ActiveOnMatch)
276    }
277    ///Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
278    #[inline(always)]
279    pub fn inactive_on_match(self) -> &'a mut crate::W<REG> {
280        self.variant(OC1M::InactiveOnMatch)
281    }
282    ///OCyREF toggles when TIMx_CNT=TIMx_CCRy
283    #[inline(always)]
284    pub fn toggle(self) -> &'a mut crate::W<REG> {
285        self.variant(OC1M::Toggle)
286    }
287    ///OCyREF is forced low
288    #[inline(always)]
289    pub fn force_inactive(self) -> &'a mut crate::W<REG> {
290        self.variant(OC1M::ForceInactive)
291    }
292    ///OCyREF is forced high
293    #[inline(always)]
294    pub fn force_active(self) -> &'a mut crate::W<REG> {
295        self.variant(OC1M::ForceActive)
296    }
297    ///In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
298    #[inline(always)]
299    pub fn pwm_mode1(self) -> &'a mut crate::W<REG> {
300        self.variant(OC1M::PwmMode1)
301    }
302    ///Inversely to PwmMode1
303    #[inline(always)]
304    pub fn pwm_mode2(self) -> &'a mut crate::W<REG> {
305        self.variant(OC1M::PwmMode2)
306    }
307}
308impl R {
309    ///Capture/Compare (1-1) selection
310    ///
311    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
312    #[inline(always)]
313    pub fn ccs(&self, n: u8) -> CCS_R {
314        #[allow(clippy::no_effect)]
315        [(); 1][n as usize];
316        CCS_R::new(((self.bits >> (n * 0)) & 3) as u8)
317    }
318    ///Iterator for array of:
319    ///Capture/Compare (1-1) selection
320    #[inline(always)]
321    pub fn ccs_iter(&self) -> impl Iterator<Item = CCS_R> + '_ {
322        (0..1).map(move |n| CCS_R::new(((self.bits >> (n * 0)) & 3) as u8))
323    }
324    ///Bits 0:1 - Capture/Compare 1 selection
325    #[inline(always)]
326    pub fn cc1s(&self) -> CCS_R {
327        CCS_R::new((self.bits & 3) as u8)
328    }
329    ///Output compare (1-1) fast enable
330    ///
331    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
332    #[inline(always)]
333    pub fn ocfe(&self, n: u8) -> OCFE_R {
334        #[allow(clippy::no_effect)]
335        [(); 1][n as usize];
336        OCFE_R::new(((self.bits >> (n * 0 + 2)) & 1) != 0)
337    }
338    ///Iterator for array of:
339    ///Output compare (1-1) fast enable
340    #[inline(always)]
341    pub fn ocfe_iter(&self) -> impl Iterator<Item = OCFE_R> + '_ {
342        (0..1).map(move |n| OCFE_R::new(((self.bits >> (n * 0 + 2)) & 1) != 0))
343    }
344    ///Bit 2 - Output compare 1 fast enable
345    #[inline(always)]
346    pub fn oc1fe(&self) -> OCFE_R {
347        OCFE_R::new(((self.bits >> 2) & 1) != 0)
348    }
349    ///Output compare (1-1) preload enable
350    ///
351    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
352    #[inline(always)]
353    pub fn ocpe(&self, n: u8) -> OCPE_R {
354        #[allow(clippy::no_effect)]
355        [(); 1][n as usize];
356        OCPE_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0)
357    }
358    ///Iterator for array of:
359    ///Output compare (1-1) preload enable
360    #[inline(always)]
361    pub fn ocpe_iter(&self) -> impl Iterator<Item = OCPE_R> + '_ {
362        (0..1).map(move |n| OCPE_R::new(((self.bits >> (n * 0 + 3)) & 1) != 0))
363    }
364    ///Bit 3 - Output compare 1 preload enable
365    #[inline(always)]
366    pub fn oc1pe(&self) -> OCPE_R {
367        OCPE_R::new(((self.bits >> 3) & 1) != 0)
368    }
369    ///Output compare (1-1) mode
370    ///
371    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
372    #[inline(always)]
373    pub fn ocm(&self, n: u8) -> OCM_R {
374        #[allow(clippy::no_effect)]
375        [(); 1][n as usize];
376        OCM_R::new(((self.bits >> (n * 0 + 4)) & 7) as u8)
377    }
378    ///Iterator for array of:
379    ///Output compare (1-1) mode
380    #[inline(always)]
381    pub fn ocm_iter(&self) -> impl Iterator<Item = OCM_R> + '_ {
382        (0..1).map(move |n| OCM_R::new(((self.bits >> (n * 0 + 4)) & 7) as u8))
383    }
384    ///Bits 4:6 - Output compare 1 mode
385    #[inline(always)]
386    pub fn oc1m(&self) -> OCM_R {
387        OCM_R::new(((self.bits >> 4) & 7) as u8)
388    }
389}
390impl core::fmt::Debug for R {
391    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
392        f.debug_struct("CCMR1_Output")
393            .field("cc1s", &self.cc1s())
394            .field("oc1fe", &self.oc1fe())
395            .field("oc1pe", &self.oc1pe())
396            .field("oc1m", &self.oc1m())
397            .finish()
398    }
399}
400impl W {
401    ///Capture/Compare (1-1) selection
402    ///
403    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1S` field.</div>
404    #[inline(always)]
405    pub fn ccs(&mut self, n: u8) -> CCS_W<CCMR1_OUTPUTrs> {
406        #[allow(clippy::no_effect)]
407        [(); 1][n as usize];
408        CCS_W::new(self, n * 0)
409    }
410    ///Bits 0:1 - Capture/Compare 1 selection
411    #[inline(always)]
412    pub fn cc1s(&mut self) -> CCS_W<CCMR1_OUTPUTrs> {
413        CCS_W::new(self, 0)
414    }
415    ///Output compare (1-1) fast enable
416    ///
417    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1FE` field.</div>
418    #[inline(always)]
419    pub fn ocfe(&mut self, n: u8) -> OCFE_W<CCMR1_OUTPUTrs> {
420        #[allow(clippy::no_effect)]
421        [(); 1][n as usize];
422        OCFE_W::new(self, n * 0 + 2)
423    }
424    ///Bit 2 - Output compare 1 fast enable
425    #[inline(always)]
426    pub fn oc1fe(&mut self) -> OCFE_W<CCMR1_OUTPUTrs> {
427        OCFE_W::new(self, 2)
428    }
429    ///Output compare (1-1) preload enable
430    ///
431    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1PE` field.</div>
432    #[inline(always)]
433    pub fn ocpe(&mut self, n: u8) -> OCPE_W<CCMR1_OUTPUTrs> {
434        #[allow(clippy::no_effect)]
435        [(); 1][n as usize];
436        OCPE_W::new(self, n * 0 + 3)
437    }
438    ///Bit 3 - Output compare 1 preload enable
439    #[inline(always)]
440    pub fn oc1pe(&mut self) -> OCPE_W<CCMR1_OUTPUTrs> {
441        OCPE_W::new(self, 3)
442    }
443    ///Output compare (1-1) mode
444    ///
445    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `OC1M` field.</div>
446    #[inline(always)]
447    pub fn ocm(&mut self, n: u8) -> OCM_W<CCMR1_OUTPUTrs> {
448        #[allow(clippy::no_effect)]
449        [(); 1][n as usize];
450        OCM_W::new(self, n * 0 + 4)
451    }
452    ///Bits 4:6 - Output compare 1 mode
453    #[inline(always)]
454    pub fn oc1m(&mut self) -> OCM_W<CCMR1_OUTPUTrs> {
455        OCM_W::new(self, 4)
456    }
457}
458/**capture/compare mode register (output mode)
459
460You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
461
462See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F373.html#TIM13:CCMR1_Output)*/
463pub struct CCMR1_OUTPUTrs;
464impl crate::RegisterSpec for CCMR1_OUTPUTrs {
465    type Ux = u32;
466}
467///`read()` method returns [`ccmr1_output::R`](R) reader structure
468impl crate::Readable for CCMR1_OUTPUTrs {}
469///`write(|w| ..)` method takes [`ccmr1_output::W`](W) writer structure
470impl crate::Writable for CCMR1_OUTPUTrs {
471    type Safety = crate::Unsafe;
472}
473///`reset()` method sets CCMR1_Output to value 0
474impl crate::Resettable for CCMR1_OUTPUTrs {}
stm32f3/stm32f373/tim13/ccmr1_output.rs

stm32f3/stm32f373/tim13/
ccmr1_output.rs
