stm32f3/stm32f303/usb/
epr.rs

1///Register `EP%sR` reader
2pub type R = crate::R<EPRrs>;
3///Register `EP%sR` writer
4pub type W = crate::W<EPRrs>;
5///Field `EA` reader - Endpoint address
6pub type EA_R = crate::FieldReader;
7///Field `EA` writer - Endpoint address
8pub type EA_W<'a, REG> = crate::FieldWriter<'a, REG, 4, u8, crate::Safe>;
9/**Status bits, for transmission transfers
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum STAT_TXR {
16    ///0: all transmission requests addressed to this endpoint are ignored
17    Disabled = 0,
18    ///1: the endpoint is stalled and all transmission requests result in a STALL handshake
19    Stall = 1,
20    ///2: the endpoint is naked and all transmission requests result in a NAK handshake
21    Nak = 2,
22    ///3: this endpoint is enabled for transmission
23    Valid = 3,
24}
25impl From<STAT_TXR> for u8 {
26    #[inline(always)]
27    fn from(variant: STAT_TXR) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for STAT_TXR {
32    type Ux = u8;
33}
34impl crate::IsEnum for STAT_TXR {}
35///Field `STAT_TX` reader - Status bits, for transmission transfers
36pub type STAT_TX_R = crate::FieldReader<STAT_TXR>;
37impl STAT_TX_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> STAT_TXR {
41        match self.bits {
42            0 => STAT_TXR::Disabled,
43            1 => STAT_TXR::Stall,
44            2 => STAT_TXR::Nak,
45            3 => STAT_TXR::Valid,
46            _ => unreachable!(),
47        }
48    }
49    ///all transmission requests addressed to this endpoint are ignored
50    #[inline(always)]
51    pub fn is_disabled(&self) -> bool {
52        *self == STAT_TXR::Disabled
53    }
54    ///the endpoint is stalled and all transmission requests result in a STALL handshake
55    #[inline(always)]
56    pub fn is_stall(&self) -> bool {
57        *self == STAT_TXR::Stall
58    }
59    ///the endpoint is naked and all transmission requests result in a NAK handshake
60    #[inline(always)]
61    pub fn is_nak(&self) -> bool {
62        *self == STAT_TXR::Nak
63    }
64    ///this endpoint is enabled for transmission
65    #[inline(always)]
66    pub fn is_valid(&self) -> bool {
67        *self == STAT_TXR::Valid
68    }
69}
70///Field `STAT_TX` writer - Status bits, for transmission transfers
71pub type STAT_TX_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STAT_TXR, crate::Safe>;
72impl<'a, REG> STAT_TX_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    ///all transmission requests addressed to this endpoint are ignored
78    #[inline(always)]
79    pub fn disabled(self) -> &'a mut crate::W<REG> {
80        self.variant(STAT_TXR::Disabled)
81    }
82    ///the endpoint is stalled and all transmission requests result in a STALL handshake
83    #[inline(always)]
84    pub fn stall(self) -> &'a mut crate::W<REG> {
85        self.variant(STAT_TXR::Stall)
86    }
87    ///the endpoint is naked and all transmission requests result in a NAK handshake
88    #[inline(always)]
89    pub fn nak(self) -> &'a mut crate::W<REG> {
90        self.variant(STAT_TXR::Nak)
91    }
92    ///this endpoint is enabled for transmission
93    #[inline(always)]
94    pub fn valid(self) -> &'a mut crate::W<REG> {
95        self.variant(STAT_TXR::Valid)
96    }
97}
98///Field `DTOG_TX` reader - Data Toggle, for transmission transfers
99pub type DTOG_TX_R = crate::BitReader;
100///Field `DTOG_TX` writer - Data Toggle, for transmission transfers
101pub type DTOG_TX_W<'a, REG> = crate::BitWriter1T<'a, REG>;
102///Field `CTR_TX` reader - Correct Transfer for transmission
103pub type CTR_TX_R = crate::BitReader;
104///Field `CTR_TX` writer - Correct Transfer for transmission
105pub type CTR_TX_W<'a, REG> = crate::BitWriter0C<'a, REG>;
106///Field `EP_KIND` reader - Endpoint kind
107pub type EP_KIND_R = crate::BitReader;
108///Field `EP_KIND` writer - Endpoint kind
109pub type EP_KIND_W<'a, REG> = crate::BitWriter<'a, REG>;
110/**Endpoint type
111
112Value on reset: 0*/
113#[cfg_attr(feature = "defmt", derive(defmt::Format))]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115#[repr(u8)]
116pub enum EP_TYPE {
117    ///0: Bulk endpoint
118    Bulk = 0,
119    ///1: Control endpoint
120    Control = 1,
121    ///2: Iso endpoint
122    Iso = 2,
123    ///3: Interrupt endpoint
124    Interrupt = 3,
125}
126impl From<EP_TYPE> for u8 {
127    #[inline(always)]
128    fn from(variant: EP_TYPE) -> Self {
129        variant as _
130    }
131}
132impl crate::FieldSpec for EP_TYPE {
133    type Ux = u8;
134}
135impl crate::IsEnum for EP_TYPE {}
136///Field `EP_TYPE` reader - Endpoint type
137pub type EP_TYPE_R = crate::FieldReader<EP_TYPE>;
138impl EP_TYPE_R {
139    ///Get enumerated values variant
140    #[inline(always)]
141    pub const fn variant(&self) -> EP_TYPE {
142        match self.bits {
143            0 => EP_TYPE::Bulk,
144            1 => EP_TYPE::Control,
145            2 => EP_TYPE::Iso,
146            3 => EP_TYPE::Interrupt,
147            _ => unreachable!(),
148        }
149    }
150    ///Bulk endpoint
151    #[inline(always)]
152    pub fn is_bulk(&self) -> bool {
153        *self == EP_TYPE::Bulk
154    }
155    ///Control endpoint
156    #[inline(always)]
157    pub fn is_control(&self) -> bool {
158        *self == EP_TYPE::Control
159    }
160    ///Iso endpoint
161    #[inline(always)]
162    pub fn is_iso(&self) -> bool {
163        *self == EP_TYPE::Iso
164    }
165    ///Interrupt endpoint
166    #[inline(always)]
167    pub fn is_interrupt(&self) -> bool {
168        *self == EP_TYPE::Interrupt
169    }
170}
171///Field `EP_TYPE` writer - Endpoint type
172pub type EP_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 2, EP_TYPE, crate::Safe>;
173impl<'a, REG> EP_TYPE_W<'a, REG>
174where
175    REG: crate::Writable + crate::RegisterSpec,
176    REG::Ux: From<u8>,
177{
178    ///Bulk endpoint
179    #[inline(always)]
180    pub fn bulk(self) -> &'a mut crate::W<REG> {
181        self.variant(EP_TYPE::Bulk)
182    }
183    ///Control endpoint
184    #[inline(always)]
185    pub fn control(self) -> &'a mut crate::W<REG> {
186        self.variant(EP_TYPE::Control)
187    }
188    ///Iso endpoint
189    #[inline(always)]
190    pub fn iso(self) -> &'a mut crate::W<REG> {
191        self.variant(EP_TYPE::Iso)
192    }
193    ///Interrupt endpoint
194    #[inline(always)]
195    pub fn interrupt(self) -> &'a mut crate::W<REG> {
196        self.variant(EP_TYPE::Interrupt)
197    }
198}
199///Field `SETUP` reader - Setup transaction completed
200pub type SETUP_R = crate::BitReader;
201/**Status bits, for reception transfers
202
203Value on reset: 0*/
204#[cfg_attr(feature = "defmt", derive(defmt::Format))]
205#[derive(Clone, Copy, Debug, PartialEq, Eq)]
206#[repr(u8)]
207pub enum STAT_RXR {
208    ///0: all reception requests addressed to this endpoint are ignored
209    Disabled = 0,
210    ///1: the endpoint is stalled and all reception requests result in a STALL handshake
211    Stall = 1,
212    ///2: the endpoint is naked and all reception requests result in a NAK handshake
213    Nak = 2,
214    ///3: this endpoint is enabled for reception
215    Valid = 3,
216}
217impl From<STAT_RXR> for u8 {
218    #[inline(always)]
219    fn from(variant: STAT_RXR) -> Self {
220        variant as _
221    }
222}
223impl crate::FieldSpec for STAT_RXR {
224    type Ux = u8;
225}
226impl crate::IsEnum for STAT_RXR {}
227///Field `STAT_RX` reader - Status bits, for reception transfers
228pub type STAT_RX_R = crate::FieldReader<STAT_RXR>;
229impl STAT_RX_R {
230    ///Get enumerated values variant
231    #[inline(always)]
232    pub const fn variant(&self) -> STAT_RXR {
233        match self.bits {
234            0 => STAT_RXR::Disabled,
235            1 => STAT_RXR::Stall,
236            2 => STAT_RXR::Nak,
237            3 => STAT_RXR::Valid,
238            _ => unreachable!(),
239        }
240    }
241    ///all reception requests addressed to this endpoint are ignored
242    #[inline(always)]
243    pub fn is_disabled(&self) -> bool {
244        *self == STAT_RXR::Disabled
245    }
246    ///the endpoint is stalled and all reception requests result in a STALL handshake
247    #[inline(always)]
248    pub fn is_stall(&self) -> bool {
249        *self == STAT_RXR::Stall
250    }
251    ///the endpoint is naked and all reception requests result in a NAK handshake
252    #[inline(always)]
253    pub fn is_nak(&self) -> bool {
254        *self == STAT_RXR::Nak
255    }
256    ///this endpoint is enabled for reception
257    #[inline(always)]
258    pub fn is_valid(&self) -> bool {
259        *self == STAT_RXR::Valid
260    }
261}
262///Field `STAT_RX` writer - Status bits, for reception transfers
263pub type STAT_RX_W<'a, REG> = crate::FieldWriter<'a, REG, 2, STAT_RXR, crate::Safe>;
264impl<'a, REG> STAT_RX_W<'a, REG>
265where
266    REG: crate::Writable + crate::RegisterSpec,
267    REG::Ux: From<u8>,
268{
269    ///all reception requests addressed to this endpoint are ignored
270    #[inline(always)]
271    pub fn disabled(self) -> &'a mut crate::W<REG> {
272        self.variant(STAT_RXR::Disabled)
273    }
274    ///the endpoint is stalled and all reception requests result in a STALL handshake
275    #[inline(always)]
276    pub fn stall(self) -> &'a mut crate::W<REG> {
277        self.variant(STAT_RXR::Stall)
278    }
279    ///the endpoint is naked and all reception requests result in a NAK handshake
280    #[inline(always)]
281    pub fn nak(self) -> &'a mut crate::W<REG> {
282        self.variant(STAT_RXR::Nak)
283    }
284    ///this endpoint is enabled for reception
285    #[inline(always)]
286    pub fn valid(self) -> &'a mut crate::W<REG> {
287        self.variant(STAT_RXR::Valid)
288    }
289}
290///Field `DTOG_RX` reader - Data Toggle, for reception transfers
291pub type DTOG_RX_R = crate::BitReader;
292///Field `DTOG_RX` writer - Data Toggle, for reception transfers
293pub type DTOG_RX_W<'a, REG> = crate::BitWriter1T<'a, REG>;
294///Field `CTR_RX` reader - Correct transfer for reception
295pub type CTR_RX_R = crate::BitReader;
296///Field `CTR_RX` writer - Correct transfer for reception
297pub type CTR_RX_W<'a, REG> = crate::BitWriter0C<'a, REG>;
298impl R {
299    ///Bits 0:3 - Endpoint address
300    #[inline(always)]
301    pub fn ea(&self) -> EA_R {
302        EA_R::new((self.bits & 0x0f) as u8)
303    }
304    ///Bits 4:5 - Status bits, for transmission transfers
305    #[inline(always)]
306    pub fn stat_tx(&self) -> STAT_TX_R {
307        STAT_TX_R::new(((self.bits >> 4) & 3) as u8)
308    }
309    ///Bit 6 - Data Toggle, for transmission transfers
310    #[inline(always)]
311    pub fn dtog_tx(&self) -> DTOG_TX_R {
312        DTOG_TX_R::new(((self.bits >> 6) & 1) != 0)
313    }
314    ///Bit 7 - Correct Transfer for transmission
315    #[inline(always)]
316    pub fn ctr_tx(&self) -> CTR_TX_R {
317        CTR_TX_R::new(((self.bits >> 7) & 1) != 0)
318    }
319    ///Bit 8 - Endpoint kind
320    #[inline(always)]
321    pub fn ep_kind(&self) -> EP_KIND_R {
322        EP_KIND_R::new(((self.bits >> 8) & 1) != 0)
323    }
324    ///Bits 9:10 - Endpoint type
325    #[inline(always)]
326    pub fn ep_type(&self) -> EP_TYPE_R {
327        EP_TYPE_R::new(((self.bits >> 9) & 3) as u8)
328    }
329    ///Bit 11 - Setup transaction completed
330    #[inline(always)]
331    pub fn setup(&self) -> SETUP_R {
332        SETUP_R::new(((self.bits >> 11) & 1) != 0)
333    }
334    ///Bits 12:13 - Status bits, for reception transfers
335    #[inline(always)]
336    pub fn stat_rx(&self) -> STAT_RX_R {
337        STAT_RX_R::new(((self.bits >> 12) & 3) as u8)
338    }
339    ///Bit 14 - Data Toggle, for reception transfers
340    #[inline(always)]
341    pub fn dtog_rx(&self) -> DTOG_RX_R {
342        DTOG_RX_R::new(((self.bits >> 14) & 1) != 0)
343    }
344    ///Bit 15 - Correct transfer for reception
345    #[inline(always)]
346    pub fn ctr_rx(&self) -> CTR_RX_R {
347        CTR_RX_R::new(((self.bits >> 15) & 1) != 0)
348    }
349}
350impl core::fmt::Debug for R {
351    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
352        f.debug_struct("EPR")
353            .field("ea", &self.ea())
354            .field("stat_tx", &self.stat_tx())
355            .field("dtog_tx", &self.dtog_tx())
356            .field("ctr_tx", &self.ctr_tx())
357            .field("ep_kind", &self.ep_kind())
358            .field("ep_type", &self.ep_type())
359            .field("setup", &self.setup())
360            .field("stat_rx", &self.stat_rx())
361            .field("dtog_rx", &self.dtog_rx())
362            .field("ctr_rx", &self.ctr_rx())
363            .finish()
364    }
365}
366impl W {
367    ///Bits 0:3 - Endpoint address
368    #[inline(always)]
369    pub fn ea(&mut self) -> EA_W<EPRrs> {
370        EA_W::new(self, 0)
371    }
372    ///Bits 4:5 - Status bits, for transmission transfers
373    #[inline(always)]
374    pub fn stat_tx(&mut self) -> STAT_TX_W<EPRrs> {
375        STAT_TX_W::new(self, 4)
376    }
377    ///Bit 6 - Data Toggle, for transmission transfers
378    #[inline(always)]
379    pub fn dtog_tx(&mut self) -> DTOG_TX_W<EPRrs> {
380        DTOG_TX_W::new(self, 6)
381    }
382    ///Bit 7 - Correct Transfer for transmission
383    #[inline(always)]
384    pub fn ctr_tx(&mut self) -> CTR_TX_W<EPRrs> {
385        CTR_TX_W::new(self, 7)
386    }
387    ///Bit 8 - Endpoint kind
388    #[inline(always)]
389    pub fn ep_kind(&mut self) -> EP_KIND_W<EPRrs> {
390        EP_KIND_W::new(self, 8)
391    }
392    ///Bits 9:10 - Endpoint type
393    #[inline(always)]
394    pub fn ep_type(&mut self) -> EP_TYPE_W<EPRrs> {
395        EP_TYPE_W::new(self, 9)
396    }
397    ///Bits 12:13 - Status bits, for reception transfers
398    #[inline(always)]
399    pub fn stat_rx(&mut self) -> STAT_RX_W<EPRrs> {
400        STAT_RX_W::new(self, 12)
401    }
402    ///Bit 14 - Data Toggle, for reception transfers
403    #[inline(always)]
404    pub fn dtog_rx(&mut self) -> DTOG_RX_W<EPRrs> {
405        DTOG_RX_W::new(self, 14)
406    }
407    ///Bit 15 - Correct transfer for reception
408    #[inline(always)]
409    pub fn ctr_rx(&mut self) -> CTR_RX_W<EPRrs> {
410        CTR_RX_W::new(self, 15)
411    }
412}
413/**endpoint %s register
414
415You can [`read`](crate::Reg::read) this register and get [`epr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`epr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
416
417See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USB:EP[0]R)*/
418pub struct EPRrs;
419impl crate::RegisterSpec for EPRrs {
420    type Ux = u32;
421}
422///`read()` method returns [`epr::R`](R) reader structure
423impl crate::Readable for EPRrs {}
424///`write(|w| ..)` method takes [`epr::W`](W) writer structure
425impl crate::Writable for EPRrs {
426    type Safety = crate::Unsafe;
427    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x8080;
428    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x7070;
429}
430///`reset()` method sets EP%sR to value 0
431impl crate::Resettable for EPRrs {}
stm32f3/stm32f303/usb/epr.rs

stm32f3/stm32f303/usb/
epr.rs
