stm32f3/stm32f303/
mod.rs

1/*!Peripheral access API for STM32F303 microcontrollers (generated using svd2rust v0.36.1 (4052ce6 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, FPU, ITM, MPU, NVIC, SCB, SYST, TPIU};
16#[cfg(feature = "rt")]
17pub use cortex_m_rt::interrupt;
18#[cfg(feature = "rt")]
19extern "C" {
20    fn WWDG();
21    fn PVD();
22    fn TAMP_STAMP();
23    fn RTC_WKUP();
24    fn FLASH();
25    fn RCC();
26    fn EXTI0();
27    fn EXTI1();
28    fn EXTI2_TSC();
29    fn EXTI3();
30    fn EXTI4();
31    fn DMA1_CH1();
32    fn DMA1_CH2();
33    fn DMA1_CH3();
34    fn DMA1_CH4();
35    fn DMA1_CH5();
36    fn DMA1_CH6();
37    fn DMA1_CH7();
38    fn ADC1_2();
39    fn USB_HP_CAN_TX();
40    fn USB_LP_CAN_RX0();
41    fn CAN_RX1();
42    fn CAN_SCE();
43    fn EXTI9_5();
44    fn TIM1_BRK_TIM15();
45    fn TIM1_UP_TIM16();
46    fn TIM1_TRG_COM_TIM17();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV_EXTI23();
52    fn I2C1_ER();
53    fn I2C2_EV_EXTI24();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1_EXTI25();
58    fn USART2_EXTI26();
59    fn USART3_EXTI28();
60    fn EXTI15_10();
61    fn RTCALARM();
62    fn USB_WKUP();
63    fn TIM8_BRK();
64    fn TIM8_UP();
65    fn TIM8_TRG_COM();
66    fn TIM8_CC();
67    fn ADC3();
68    fn FMC();
69    fn SPI3();
70    fn UART4_EXTI34();
71    fn UART5_EXTI35();
72    fn TIM6_DACUNDER();
73    fn TIM7();
74    fn DMA2_CH1();
75    fn DMA2_CH2();
76    fn DMA2_CH3();
77    fn DMA2_CH4();
78    fn DMA2_CH5();
79    fn ADC4();
80    fn COMP1_2_3();
81    fn COMP4_5_6();
82    fn COMP7();
83    fn I2C3_EV();
84    fn I2C3_ER();
85    fn USB_HP();
86    fn USB_LP();
87    fn USB_WKUP_EXTI();
88    fn TIM20_BRK();
89    fn TIM20_UP();
90    fn TIM20_TRG_COM();
91    fn TIM20_CC();
92    fn FPU();
93    fn SPI4();
94}
95#[doc(hidden)]
96#[repr(C)]
97pub union Vector {
98    _handler: unsafe extern "C" fn(),
99    _reserved: u32,
100}
101#[cfg(feature = "rt")]
102#[doc(hidden)]
103#[link_section = ".vector_table.interrupts"]
104#[no_mangle]
105pub static __INTERRUPTS: [Vector; 85] = [
106    Vector { _handler: WWDG },
107    Vector { _handler: PVD },
108    Vector {
109        _handler: TAMP_STAMP,
110    },
111    Vector { _handler: RTC_WKUP },
112    Vector { _handler: FLASH },
113    Vector { _handler: RCC },
114    Vector { _handler: EXTI0 },
115    Vector { _handler: EXTI1 },
116    Vector {
117        _handler: EXTI2_TSC,
118    },
119    Vector { _handler: EXTI3 },
120    Vector { _handler: EXTI4 },
121    Vector { _handler: DMA1_CH1 },
122    Vector { _handler: DMA1_CH2 },
123    Vector { _handler: DMA1_CH3 },
124    Vector { _handler: DMA1_CH4 },
125    Vector { _handler: DMA1_CH5 },
126    Vector { _handler: DMA1_CH6 },
127    Vector { _handler: DMA1_CH7 },
128    Vector { _handler: ADC1_2 },
129    Vector {
130        _handler: USB_HP_CAN_TX,
131    },
132    Vector {
133        _handler: USB_LP_CAN_RX0,
134    },
135    Vector { _handler: CAN_RX1 },
136    Vector { _handler: CAN_SCE },
137    Vector { _handler: EXTI9_5 },
138    Vector {
139        _handler: TIM1_BRK_TIM15,
140    },
141    Vector {
142        _handler: TIM1_UP_TIM16,
143    },
144    Vector {
145        _handler: TIM1_TRG_COM_TIM17,
146    },
147    Vector { _handler: TIM1_CC },
148    Vector { _handler: TIM2 },
149    Vector { _handler: TIM3 },
150    Vector { _handler: TIM4 },
151    Vector {
152        _handler: I2C1_EV_EXTI23,
153    },
154    Vector { _handler: I2C1_ER },
155    Vector {
156        _handler: I2C2_EV_EXTI24,
157    },
158    Vector { _handler: I2C2_ER },
159    Vector { _handler: SPI1 },
160    Vector { _handler: SPI2 },
161    Vector {
162        _handler: USART1_EXTI25,
163    },
164    Vector {
165        _handler: USART2_EXTI26,
166    },
167    Vector {
168        _handler: USART3_EXTI28,
169    },
170    Vector {
171        _handler: EXTI15_10,
172    },
173    Vector { _handler: RTCALARM },
174    Vector { _handler: USB_WKUP },
175    Vector { _handler: TIM8_BRK },
176    Vector { _handler: TIM8_UP },
177    Vector {
178        _handler: TIM8_TRG_COM,
179    },
180    Vector { _handler: TIM8_CC },
181    Vector { _handler: ADC3 },
182    Vector { _handler: FMC },
183    Vector { _reserved: 0 },
184    Vector { _reserved: 0 },
185    Vector { _handler: SPI3 },
186    Vector {
187        _handler: UART4_EXTI34,
188    },
189    Vector {
190        _handler: UART5_EXTI35,
191    },
192    Vector {
193        _handler: TIM6_DACUNDER,
194    },
195    Vector { _handler: TIM7 },
196    Vector { _handler: DMA2_CH1 },
197    Vector { _handler: DMA2_CH2 },
198    Vector { _handler: DMA2_CH3 },
199    Vector { _handler: DMA2_CH4 },
200    Vector { _handler: DMA2_CH5 },
201    Vector { _handler: ADC4 },
202    Vector { _reserved: 0 },
203    Vector { _reserved: 0 },
204    Vector {
205        _handler: COMP1_2_3,
206    },
207    Vector {
208        _handler: COMP4_5_6,
209    },
210    Vector { _handler: COMP7 },
211    Vector { _reserved: 0 },
212    Vector { _reserved: 0 },
213    Vector { _reserved: 0 },
214    Vector { _reserved: 0 },
215    Vector { _reserved: 0 },
216    Vector { _handler: I2C3_EV },
217    Vector { _handler: I2C3_ER },
218    Vector { _handler: USB_HP },
219    Vector { _handler: USB_LP },
220    Vector {
221        _handler: USB_WKUP_EXTI,
222    },
223    Vector {
224        _handler: TIM20_BRK,
225    },
226    Vector { _handler: TIM20_UP },
227    Vector {
228        _handler: TIM20_TRG_COM,
229    },
230    Vector { _handler: TIM20_CC },
231    Vector { _handler: FPU },
232    Vector { _reserved: 0 },
233    Vector { _reserved: 0 },
234    Vector { _handler: SPI4 },
235];
236///Enumeration of all the interrupts.
237#[cfg_attr(feature = "defmt", derive(defmt::Format))]
238#[derive(Copy, Clone, Debug, PartialEq, Eq)]
239#[repr(u16)]
240pub enum Interrupt {
241    ///0 - Window Watchdog interrupt
242    WWDG = 0,
243    ///1 - PVD through EXTI line detection interrupt
244    PVD = 1,
245    ///2 - Tamper and TimeStamp interrupts
246    TAMP_STAMP = 2,
247    ///3 - RTC Wakeup interrupt through the EXTI line
248    RTC_WKUP = 3,
249    ///4 - Flash global interrupt
250    FLASH = 4,
251    ///5 - RCC global interrupt
252    RCC = 5,
253    ///6 - EXTI Line0 interrupt
254    EXTI0 = 6,
255    ///7 - EXTI Line3 interrupt
256    EXTI1 = 7,
257    ///8 - EXTI Line2 and Touch sensing interrupts
258    EXTI2_TSC = 8,
259    ///9 - EXTI Line3 interrupt
260    EXTI3 = 9,
261    ///10 - EXTI Line4 interrupt
262    EXTI4 = 10,
263    ///11 - DMA1 channel 1 interrupt
264    DMA1_CH1 = 11,
265    ///12 - DMA1 channel 2 interrupt
266    DMA1_CH2 = 12,
267    ///13 - DMA1 channel 3 interrupt
268    DMA1_CH3 = 13,
269    ///14 - DMA1 channel 4 interrupt
270    DMA1_CH4 = 14,
271    ///15 - DMA1 channel 5 interrupt
272    DMA1_CH5 = 15,
273    ///16 - DMA1 channel 6 interrupt
274    DMA1_CH6 = 16,
275    ///17 - DMA1 channel 7interrupt
276    DMA1_CH7 = 17,
277    ///18 - ADC1 and ADC2 global interrupt
278    ADC1_2 = 18,
279    ///19 - USB High Priority/CAN_TX interrupts
280    USB_HP_CAN_TX = 19,
281    ///20 - USB Low Priority/CAN_RX0 interrupts
282    USB_LP_CAN_RX0 = 20,
283    ///21 - CAN_RX1 interrupt
284    CAN_RX1 = 21,
285    ///22 - CAN_SCE interrupt
286    CAN_SCE = 22,
287    ///23 - EXTI Line5 to Line9 interrupts
288    EXTI9_5 = 23,
289    ///24 - TIM1 Break/TIM15 global interruts
290    TIM1_BRK_TIM15 = 24,
291    ///25 - TIM1 Update/TIM16 global interrupts
292    TIM1_UP_TIM16 = 25,
293    ///26 - TIM1 trigger and commutation/TIM17 interrupts
294    TIM1_TRG_COM_TIM17 = 26,
295    ///27 - TIM1 capture compare interrupt
296    TIM1_CC = 27,
297    ///28 - TIM2 global interrupt
298    TIM2 = 28,
299    ///29 - TIM3 global interrupt
300    TIM3 = 29,
301    ///30 - TIM4 global interrupt
302    TIM4 = 30,
303    ///31 - I2C1 event interrupt and EXTI Line23 interrupt
304    I2C1_EV_EXTI23 = 31,
305    ///32 - I2C1 error interrupt
306    I2C1_ER = 32,
307    ///33 - I2C2 event interrupt & EXTI Line24 interrupt
308    I2C2_EV_EXTI24 = 33,
309    ///34 - I2C2 error interrupt
310    I2C2_ER = 34,
311    ///35 - SPI1 global interrupt
312    SPI1 = 35,
313    ///36 - SPI2 global interrupt
314    SPI2 = 36,
315    ///37 - USART1 global interrupt and EXTI Line 25 interrupt
316    USART1_EXTI25 = 37,
317    ///38 - USART2 global interrupt and EXTI Line 26 interrupt
318    USART2_EXTI26 = 38,
319    ///39 - USART3 global interrupt and EXTI Line 28 interrupt
320    USART3_EXTI28 = 39,
321    ///40 - EXTI Line15 to Line10 interrupts
322    EXTI15_10 = 40,
323    ///41 - RTC alarm interrupt
324    RTCALARM = 41,
325    ///42 - USB wakeup from Suspend
326    USB_WKUP = 42,
327    ///43 - TIM8 break interrupt
328    TIM8_BRK = 43,
329    ///44 - TIM8 update interrupt
330    TIM8_UP = 44,
331    ///45 - TIM8 Trigger and commutation interrupts
332    TIM8_TRG_COM = 45,
333    ///46 - TIM8 capture compare interrupt
334    TIM8_CC = 46,
335    ///47 - ADC3 global interrupt
336    ADC3 = 47,
337    ///48 - FSMC global interrupt
338    FMC = 48,
339    ///51 - SPI3 global interrupt
340    SPI3 = 51,
341    ///52 - UART4 global and EXTI Line 34 interrupts
342    UART4_EXTI34 = 52,
343    ///53 - UART5 global and EXTI Line 35 interrupts
344    UART5_EXTI35 = 53,
345    ///54 - TIM6 global and DAC12 underrun interrupts
346    TIM6_DACUNDER = 54,
347    ///55 - TIM7 global interrupt
348    TIM7 = 55,
349    ///56 - DMA2 channel1 global interrupt
350    DMA2_CH1 = 56,
351    ///57 - DMA2 channel2 global interrupt
352    DMA2_CH2 = 57,
353    ///58 - DMA2 channel3 global interrupt
354    DMA2_CH3 = 58,
355    ///59 - DMA2 channel4 global interrupt
356    DMA2_CH4 = 59,
357    ///60 - DMA2 channel5 global interrupt
358    DMA2_CH5 = 60,
359    ///61 - ADC4 global interrupt
360    ADC4 = 61,
361    ///64 - COMP1_2_3 interrupt combined with EXTI lines 21, 22, 29
362    COMP1_2_3 = 64,
363    ///65 - COMP4_5_6 interrupt combined with EXTI lines 30, 31, 32
364    COMP4_5_6 = 65,
365    ///66 - COMP7 interrupt combined with EXTI line 33
366    COMP7 = 66,
367    ///72 - I2C3 Event interrupt
368    I2C3_EV = 72,
369    ///73 - I2C3 Error interrupt
370    I2C3_ER = 73,
371    ///74 - USB High priority interrupt
372    USB_HP = 74,
373    ///75 - USB Low priority interrupt
374    USB_LP = 75,
375    ///76 - USB wakeup from Suspend and EXTI Line 18
376    USB_WKUP_EXTI = 76,
377    ///77 - TIM20 Break interrupt
378    TIM20_BRK = 77,
379    ///78 - TIM20 Upgrade interrupt
380    TIM20_UP = 78,
381    ///79 - TIM20 Trigger and Commutation interrupt
382    TIM20_TRG_COM = 79,
383    ///80 - TIM20 Capture Compare interrupt
384    TIM20_CC = 80,
385    ///81 - Floating point unit interrupt
386    FPU = 81,
387    ///84 - SPI4 Global interrupt
388    SPI4 = 84,
389}
390unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
391    #[inline(always)]
392    fn number(self) -> u16 {
393        self as u16
394    }
395}
396///General-purpose I/Os
397///
398///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOA)
399pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4800_0000>;
400impl core::fmt::Debug for GPIOA {
401    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
402        f.debug_struct("GPIOA").finish()
403    }
404}
405///General-purpose I/Os
406pub mod gpioa;
407///General-purpose I/Os
408///
409///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOB)
410pub type GPIOB = crate::Periph<gpiob::RegisterBlock, 0x4800_0400>;
411impl core::fmt::Debug for GPIOB {
412    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
413        f.debug_struct("GPIOB").finish()
414    }
415}
416///General-purpose I/Os
417pub mod gpiob;
418///General-purpose I/Os
419///
420///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
421pub type GPIOC = crate::Periph<gpioc::RegisterBlock, 0x4800_0800>;
422impl core::fmt::Debug for GPIOC {
423    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
424        f.debug_struct("GPIOC").finish()
425    }
426}
427///General-purpose I/Os
428pub mod gpioc;
429///General-purpose I/Os
430///
431///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
432pub type GPIOD = crate::Periph<gpioc::RegisterBlock, 0x4800_0c00>;
433impl core::fmt::Debug for GPIOD {
434    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
435        f.debug_struct("GPIOD").finish()
436    }
437}
438///General-purpose I/Os
439pub use self::gpioc as gpiod;
440///General-purpose I/Os
441///
442///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
443pub type GPIOE = crate::Periph<gpioc::RegisterBlock, 0x4800_1000>;
444impl core::fmt::Debug for GPIOE {
445    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
446        f.debug_struct("GPIOE").finish()
447    }
448}
449///General-purpose I/Os
450pub use self::gpioc as gpioe;
451///General-purpose I/Os
452///
453///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
454pub type GPIOF = crate::Periph<gpioc::RegisterBlock, 0x4800_1400>;
455impl core::fmt::Debug for GPIOF {
456    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
457        f.debug_struct("GPIOF").finish()
458    }
459}
460///General-purpose I/Os
461pub use self::gpioc as gpiof;
462///General-purpose I/Os
463///
464///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
465pub type GPIOG = crate::Periph<gpioc::RegisterBlock, 0x4800_1800>;
466impl core::fmt::Debug for GPIOG {
467    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
468        f.debug_struct("GPIOG").finish()
469    }
470}
471///General-purpose I/Os
472pub use self::gpioc as gpiog;
473///General-purpose I/Os
474///
475///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#GPIOC)
476pub type GPIOH = crate::Periph<gpioc::RegisterBlock, 0x4800_1c00>;
477impl core::fmt::Debug for GPIOH {
478    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
479        f.debug_struct("GPIOH").finish()
480    }
481}
482///General-purpose I/Os
483pub use self::gpioc as gpioh;
484///Touch sensing controller
485///
486///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TSC)
487pub type TSC = crate::Periph<tsc::RegisterBlock, 0x4002_4000>;
488impl core::fmt::Debug for TSC {
489    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
490        f.debug_struct("TSC").finish()
491    }
492}
493///Touch sensing controller
494pub mod tsc;
495///cyclic redundancy check calculation unit
496///
497///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#CRC)
498pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
499impl core::fmt::Debug for CRC {
500    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
501        f.debug_struct("CRC").finish()
502    }
503}
504///cyclic redundancy check calculation unit
505pub mod crc;
506///Flash
507///
508///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FLASH)
509pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
510impl core::fmt::Debug for FLASH {
511    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
512        f.debug_struct("FLASH").finish()
513    }
514}
515///Flash
516pub mod flash;
517///Reset and clock control
518///
519///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#RCC)
520pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
521impl core::fmt::Debug for RCC {
522    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
523        f.debug_struct("RCC").finish()
524    }
525}
526///Reset and clock control
527pub mod rcc;
528///DMA controller 1
529///
530///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#DMA1)
531pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
532impl core::fmt::Debug for DMA1 {
533    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
534        f.debug_struct("DMA1").finish()
535    }
536}
537///DMA controller 1
538pub mod dma1;
539///DMA controller 1
540///
541///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#DMA1)
542pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
543impl core::fmt::Debug for DMA2 {
544    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
545        f.debug_struct("DMA2").finish()
546    }
547}
548///DMA controller 1
549pub use self::dma1 as dma2;
550///General purpose timer
551///
552///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM2)
553pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
554impl core::fmt::Debug for TIM2 {
555    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
556        f.debug_struct("TIM2").finish()
557    }
558}
559///General purpose timer
560pub mod tim2;
561///General purpose timer
562///
563///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM3)
564pub type TIM3 = crate::Periph<tim3::RegisterBlock, 0x4000_0400>;
565impl core::fmt::Debug for TIM3 {
566    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
567        f.debug_struct("TIM3").finish()
568    }
569}
570///General purpose timer
571pub mod tim3;
572///General purpose timer
573///
574///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM3)
575pub type TIM4 = crate::Periph<tim3::RegisterBlock, 0x4000_0800>;
576impl core::fmt::Debug for TIM4 {
577    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
578        f.debug_struct("TIM4").finish()
579    }
580}
581///General purpose timer
582pub use self::tim3 as tim4;
583///General purpose timers
584///
585///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM15)
586pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
587impl core::fmt::Debug for TIM15 {
588    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
589        f.debug_struct("TIM15").finish()
590    }
591}
592///General purpose timers
593pub mod tim15;
594///General-purpose-timers
595///
596///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM16)
597pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
598impl core::fmt::Debug for TIM16 {
599    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
600        f.debug_struct("TIM16").finish()
601    }
602}
603///General-purpose-timers
604pub mod tim16;
605///General purpose timer
606///
607///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM17)
608pub type TIM17 = crate::Periph<tim17::RegisterBlock, 0x4001_4800>;
609impl core::fmt::Debug for TIM17 {
610    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
611        f.debug_struct("TIM17").finish()
612    }
613}
614///General purpose timer
615pub mod tim17;
616///Universal synchronous asynchronous receiver transmitter
617///
618///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USART1)
619pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
620impl core::fmt::Debug for USART1 {
621    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
622        f.debug_struct("USART1").finish()
623    }
624}
625///Universal synchronous asynchronous receiver transmitter
626pub mod usart1;
627///Universal synchronous asynchronous receiver transmitter
628///
629///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USART1)
630pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
631impl core::fmt::Debug for USART2 {
632    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
633        f.debug_struct("USART2").finish()
634    }
635}
636///Universal synchronous asynchronous receiver transmitter
637pub use self::usart1 as usart2;
638///Universal synchronous asynchronous receiver transmitter
639///
640///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USART1)
641pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
642impl core::fmt::Debug for USART3 {
643    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
644        f.debug_struct("USART3").finish()
645    }
646}
647///Universal synchronous asynchronous receiver transmitter
648pub use self::usart1 as usart3;
649///Universal synchronous asynchronous receiver transmitter
650///
651///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USART1)
652pub type UART4 = crate::Periph<usart1::RegisterBlock, 0x4000_4c00>;
653impl core::fmt::Debug for UART4 {
654    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
655        f.debug_struct("UART4").finish()
656    }
657}
658///Universal synchronous asynchronous receiver transmitter
659pub use self::usart1 as uart4;
660///Universal synchronous asynchronous receiver transmitter
661///
662///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USART1)
663pub type UART5 = crate::Periph<usart1::RegisterBlock, 0x4000_5000>;
664impl core::fmt::Debug for UART5 {
665    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
666        f.debug_struct("UART5").finish()
667    }
668}
669///Universal synchronous asynchronous receiver transmitter
670pub use self::usart1 as uart5;
671///Serial peripheral interface/Inter-IC sound
672///
673///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SPI1)
674pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
675impl core::fmt::Debug for SPI1 {
676    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
677        f.debug_struct("SPI1").finish()
678    }
679}
680///Serial peripheral interface/Inter-IC sound
681pub mod spi1;
682///Serial peripheral interface/Inter-IC sound
683///
684///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SPI1)
685pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
686impl core::fmt::Debug for SPI2 {
687    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
688        f.debug_struct("SPI2").finish()
689    }
690}
691///Serial peripheral interface/Inter-IC sound
692pub use self::spi1 as spi2;
693///Serial peripheral interface/Inter-IC sound
694///
695///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SPI1)
696pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
697impl core::fmt::Debug for SPI3 {
698    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
699        f.debug_struct("SPI3").finish()
700    }
701}
702///Serial peripheral interface/Inter-IC sound
703pub use self::spi1 as spi3;
704///Serial peripheral interface/Inter-IC sound
705///
706///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SPI1)
707pub type SPI4 = crate::Periph<spi1::RegisterBlock, 0x4001_3c00>;
708impl core::fmt::Debug for SPI4 {
709    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
710        f.debug_struct("SPI4").finish()
711    }
712}
713///Serial peripheral interface/Inter-IC sound
714pub use self::spi1 as spi4;
715///Serial peripheral interface/Inter-IC sound
716///
717///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#I2S2ext)
718pub type I2S2EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_3400>;
719impl core::fmt::Debug for I2S2EXT {
720    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
721        f.debug_struct("I2S2EXT").finish()
722    }
723}
724///Serial peripheral interface/Inter-IC sound
725pub mod i2s2ext;
726///Serial peripheral interface/Inter-IC sound
727///
728///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#I2S2ext)
729pub type I2S3EXT = crate::Periph<i2s2ext::RegisterBlock, 0x4000_4000>;
730impl core::fmt::Debug for I2S3EXT {
731    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
732        f.debug_struct("I2S3EXT").finish()
733    }
734}
735///Serial peripheral interface/Inter-IC sound
736pub use self::i2s2ext as i2s3ext;
737///External interrupt/event controller
738///
739///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#EXTI)
740pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
741impl core::fmt::Debug for EXTI {
742    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
743        f.debug_struct("EXTI").finish()
744    }
745}
746///External interrupt/event controller
747pub mod exti;
748///Power control
749///
750///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#PWR)
751pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
752impl core::fmt::Debug for PWR {
753    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
754        f.debug_struct("PWR").finish()
755    }
756}
757///Power control
758pub mod pwr;
759///Controller area network
760///
761///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#CAN)
762pub type CAN = crate::Periph<can::RegisterBlock, 0x4000_6400>;
763impl core::fmt::Debug for CAN {
764    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
765        f.debug_struct("CAN").finish()
766    }
767}
768///Controller area network
769pub mod can;
770///Universal serial bus full-speed device interface
771///
772///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#USB)
773pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
774impl core::fmt::Debug for USB {
775    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
776        f.debug_struct("USB").finish()
777    }
778}
779///Universal serial bus full-speed device interface
780pub mod usb;
781///Inter-integrated circuit
782///
783///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#I2C1)
784pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
785impl core::fmt::Debug for I2C1 {
786    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
787        f.debug_struct("I2C1").finish()
788    }
789}
790///Inter-integrated circuit
791pub mod i2c1;
792///Inter-integrated circuit
793///
794///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#I2C1)
795pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
796impl core::fmt::Debug for I2C2 {
797    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
798        f.debug_struct("I2C2").finish()
799    }
800}
801///Inter-integrated circuit
802pub use self::i2c1 as i2c2;
803///Inter-integrated circuit
804///
805///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#I2C1)
806pub type I2C3 = crate::Periph<i2c1::RegisterBlock, 0x4000_7800>;
807impl core::fmt::Debug for I2C3 {
808    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
809        f.debug_struct("I2C3").finish()
810    }
811}
812///Inter-integrated circuit
813pub use self::i2c1 as i2c3;
814///Digital-to-analog converter
815///
816///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#DAC1)
817pub type DAC2 = crate::Periph<dac1::RegisterBlock, 0x4000_9800>;
818impl core::fmt::Debug for DAC2 {
819    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
820        f.debug_struct("DAC2").finish()
821    }
822}
823///Digital-to-analog converter
824pub use self::dac1 as dac2;
825///Independent watchdog
826///
827///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#IWDG)
828pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
829impl core::fmt::Debug for IWDG {
830    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
831        f.debug_struct("IWDG").finish()
832    }
833}
834///Independent watchdog
835pub mod iwdg;
836///Window watchdog
837///
838///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#WWDG)
839pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
840impl core::fmt::Debug for WWDG {
841    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
842        f.debug_struct("WWDG").finish()
843    }
844}
845///Window watchdog
846pub mod wwdg;
847///Real-time clock
848///
849///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#RTC)
850pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
851impl core::fmt::Debug for RTC {
852    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
853        f.debug_struct("RTC").finish()
854    }
855}
856///Real-time clock
857pub mod rtc;
858///Basic timers
859///
860///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM6)
861pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
862impl core::fmt::Debug for TIM6 {
863    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
864        f.debug_struct("TIM6").finish()
865    }
866}
867///Basic timers
868pub mod tim6;
869///Basic timers
870///
871///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM6)
872pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
873impl core::fmt::Debug for TIM7 {
874    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
875        f.debug_struct("TIM7").finish()
876    }
877}
878///Basic timers
879pub use self::tim6 as tim7;
880///Digital-to-analog converter
881///
882///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#DAC1)
883pub type DAC1 = crate::Periph<dac1::RegisterBlock, 0x4000_7400>;
884impl core::fmt::Debug for DAC1 {
885    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
886        f.debug_struct("DAC1").finish()
887    }
888}
889///Digital-to-analog converter
890pub mod dac1;
891///Debug support
892///
893///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#DBGMCU)
894pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
895impl core::fmt::Debug for DBGMCU {
896    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
897        f.debug_struct("DBGMCU").finish()
898    }
899}
900///Debug support
901pub mod dbgmcu;
902///Advanced timer
903///
904///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM1)
905pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
906impl core::fmt::Debug for TIM1 {
907    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
908        f.debug_struct("TIM1").finish()
909    }
910}
911///Advanced timer
912pub mod tim1;
913///Advanced timer
914///
915///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM1)
916pub type TIM20 = crate::Periph<tim1::RegisterBlock, 0x4001_5000>;
917impl core::fmt::Debug for TIM20 {
918    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
919        f.debug_struct("TIM20").finish()
920    }
921}
922///Advanced timer
923pub use self::tim1 as tim20;
924///Advanced-timers
925///
926///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#TIM8)
927pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
928impl core::fmt::Debug for TIM8 {
929    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
930        f.debug_struct("TIM8").finish()
931    }
932}
933///Advanced-timers
934pub mod tim8;
935///Analog-to-Digital Converter
936///
937///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1)
938pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x5000_0000>;
939impl core::fmt::Debug for ADC1 {
940    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
941        f.debug_struct("ADC1").finish()
942    }
943}
944///Analog-to-Digital Converter
945pub mod adc1;
946///Analog-to-Digital Converter
947///
948///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1)
949pub type ADC2 = crate::Periph<adc1::RegisterBlock, 0x5000_0100>;
950impl core::fmt::Debug for ADC2 {
951    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
952        f.debug_struct("ADC2").finish()
953    }
954}
955///Analog-to-Digital Converter
956pub use self::adc1 as adc2;
957///Analog-to-Digital Converter
958///
959///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1)
960pub type ADC3 = crate::Periph<adc1::RegisterBlock, 0x5000_0400>;
961impl core::fmt::Debug for ADC3 {
962    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
963        f.debug_struct("ADC3").finish()
964    }
965}
966///Analog-to-Digital Converter
967pub use self::adc1 as adc3;
968///Analog-to-Digital Converter
969///
970///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1)
971pub type ADC4 = crate::Periph<adc1::RegisterBlock, 0x5000_0500>;
972impl core::fmt::Debug for ADC4 {
973    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
974        f.debug_struct("ADC4").finish()
975    }
976}
977///Analog-to-Digital Converter
978pub use self::adc1 as adc4;
979///Analog-to-Digital Converter
980///
981///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1_2)
982pub type ADC1_2 = crate::Periph<adc1_2::RegisterBlock, 0x5000_0300>;
983impl core::fmt::Debug for ADC1_2 {
984    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
985        f.debug_struct("ADC1_2").finish()
986    }
987}
988///Analog-to-Digital Converter
989pub mod adc1_2;
990///Analog-to-Digital Converter
991///
992///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1_2)
993pub type ADC3_4 = crate::Periph<adc1_2::RegisterBlock, 0x5000_0700>;
994impl core::fmt::Debug for ADC3_4 {
995    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
996        f.debug_struct("ADC3_4").finish()
997    }
998}
999///Analog-to-Digital Converter
1000pub use self::adc1_2 as adc3_4;
1001///System configuration controller
1002///
1003///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#SYSCFG)
1004pub type SYSCFG = crate::Periph<syscfg::RegisterBlock, 0x4001_0000>;
1005impl core::fmt::Debug for SYSCFG {
1006    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1007        f.debug_struct("SYSCFG").finish()
1008    }
1009}
1010///System configuration controller
1011pub mod syscfg;
1012///Operational Amplifier
1013///
1014///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#OPAMP)
1015pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4001_0000>;
1016impl core::fmt::Debug for OPAMP {
1017    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1018        f.debug_struct("OPAMP").finish()
1019    }
1020}
1021///Operational Amplifier
1022pub mod opamp;
1023///General purpose comparators
1024///
1025///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#COMP)
1026pub type COMP = crate::Periph<comp::RegisterBlock, 0x4001_0000>;
1027impl core::fmt::Debug for COMP {
1028    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1029        f.debug_struct("COMP").finish()
1030    }
1031}
1032///General purpose comparators
1033pub mod comp;
1034///Flexible memory controller
1035///
1036///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#FMC)
1037pub type FMC = crate::Periph<fmc::RegisterBlock, 0xa000_0400>;
1038impl core::fmt::Debug for FMC {
1039    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1040        f.debug_struct("FMC").finish()
1041    }
1042}
1043///Flexible memory controller
1044pub mod fmc;
1045#[no_mangle]
1046static mut DEVICE_PERIPHERALS: bool = false;
1047/// All the peripherals.
1048#[allow(non_snake_case)]
1049pub struct Peripherals {
1050    ///GPIOA
1051    pub GPIOA: GPIOA,
1052    ///GPIOB
1053    pub GPIOB: GPIOB,
1054    ///GPIOC
1055    pub GPIOC: GPIOC,
1056    ///GPIOD
1057    pub GPIOD: GPIOD,
1058    ///GPIOE
1059    pub GPIOE: GPIOE,
1060    ///GPIOF
1061    pub GPIOF: GPIOF,
1062    ///GPIOG
1063    pub GPIOG: GPIOG,
1064    ///GPIOH
1065    pub GPIOH: GPIOH,
1066    ///TSC
1067    pub TSC: TSC,
1068    ///CRC
1069    pub CRC: CRC,
1070    ///FLASH
1071    pub FLASH: FLASH,
1072    ///RCC
1073    pub RCC: RCC,
1074    ///DMA1
1075    pub DMA1: DMA1,
1076    ///DMA2
1077    pub DMA2: DMA2,
1078    ///TIM2
1079    pub TIM2: TIM2,
1080    ///TIM3
1081    pub TIM3: TIM3,
1082    ///TIM4
1083    pub TIM4: TIM4,
1084    ///TIM15
1085    pub TIM15: TIM15,
1086    ///TIM16
1087    pub TIM16: TIM16,
1088    ///TIM17
1089    pub TIM17: TIM17,
1090    ///USART1
1091    pub USART1: USART1,
1092    ///USART2
1093    pub USART2: USART2,
1094    ///USART3
1095    pub USART3: USART3,
1096    ///UART4
1097    pub UART4: UART4,
1098    ///UART5
1099    pub UART5: UART5,
1100    ///SPI1
1101    pub SPI1: SPI1,
1102    ///SPI2
1103    pub SPI2: SPI2,
1104    ///SPI3
1105    pub SPI3: SPI3,
1106    ///SPI4
1107    pub SPI4: SPI4,
1108    ///I2S2ext
1109    pub I2S2EXT: I2S2EXT,
1110    ///I2S3ext
1111    pub I2S3EXT: I2S3EXT,
1112    ///EXTI
1113    pub EXTI: EXTI,
1114    ///PWR
1115    pub PWR: PWR,
1116    ///CAN
1117    pub CAN: CAN,
1118    ///USB
1119    pub USB: USB,
1120    ///I2C1
1121    pub I2C1: I2C1,
1122    ///I2C2
1123    pub I2C2: I2C2,
1124    ///I2C3
1125    pub I2C3: I2C3,
1126    ///DAC2
1127    pub DAC2: DAC2,
1128    ///IWDG
1129    pub IWDG: IWDG,
1130    ///WWDG
1131    pub WWDG: WWDG,
1132    ///RTC
1133    pub RTC: RTC,
1134    ///TIM6
1135    pub TIM6: TIM6,
1136    ///TIM7
1137    pub TIM7: TIM7,
1138    ///DAC1
1139    pub DAC1: DAC1,
1140    ///DBGMCU
1141    pub DBGMCU: DBGMCU,
1142    ///TIM1
1143    pub TIM1: TIM1,
1144    ///TIM20
1145    pub TIM20: TIM20,
1146    ///TIM8
1147    pub TIM8: TIM8,
1148    ///ADC1
1149    pub ADC1: ADC1,
1150    ///ADC2
1151    pub ADC2: ADC2,
1152    ///ADC3
1153    pub ADC3: ADC3,
1154    ///ADC4
1155    pub ADC4: ADC4,
1156    ///ADC1_2
1157    pub ADC1_2: ADC1_2,
1158    ///ADC3_4
1159    pub ADC3_4: ADC3_4,
1160    ///SYSCFG
1161    pub SYSCFG: SYSCFG,
1162    ///OPAMP
1163    pub OPAMP: OPAMP,
1164    ///COMP
1165    pub COMP: COMP,
1166    ///FMC
1167    pub FMC: FMC,
1168}
1169impl Peripherals {
1170    /// Returns all the peripherals *once*.
1171    #[cfg(feature = "critical-section")]
1172    #[inline]
1173    pub fn take() -> Option<Self> {
1174        critical_section::with(|_| {
1175            if unsafe { DEVICE_PERIPHERALS } {
1176                return None;
1177            }
1178            Some(unsafe { Peripherals::steal() })
1179        })
1180    }
1181    /// Unchecked version of `Peripherals::take`.
1182    ///
1183    /// # Safety
1184    ///
1185    /// Each of the returned peripherals must be used at most once.
1186    #[inline]
1187    pub unsafe fn steal() -> Self {
1188        DEVICE_PERIPHERALS = true;
1189        Peripherals {
1190            GPIOA: GPIOA::steal(),
1191            GPIOB: GPIOB::steal(),
1192            GPIOC: GPIOC::steal(),
1193            GPIOD: GPIOD::steal(),
1194            GPIOE: GPIOE::steal(),
1195            GPIOF: GPIOF::steal(),
1196            GPIOG: GPIOG::steal(),
1197            GPIOH: GPIOH::steal(),
1198            TSC: TSC::steal(),
1199            CRC: CRC::steal(),
1200            FLASH: FLASH::steal(),
1201            RCC: RCC::steal(),
1202            DMA1: DMA1::steal(),
1203            DMA2: DMA2::steal(),
1204            TIM2: TIM2::steal(),
1205            TIM3: TIM3::steal(),
1206            TIM4: TIM4::steal(),
1207            TIM15: TIM15::steal(),
1208            TIM16: TIM16::steal(),
1209            TIM17: TIM17::steal(),
1210            USART1: USART1::steal(),
1211            USART2: USART2::steal(),
1212            USART3: USART3::steal(),
1213            UART4: UART4::steal(),
1214            UART5: UART5::steal(),
1215            SPI1: SPI1::steal(),
1216            SPI2: SPI2::steal(),
1217            SPI3: SPI3::steal(),
1218            SPI4: SPI4::steal(),
1219            I2S2EXT: I2S2EXT::steal(),
1220            I2S3EXT: I2S3EXT::steal(),
1221            EXTI: EXTI::steal(),
1222            PWR: PWR::steal(),
1223            CAN: CAN::steal(),
1224            USB: USB::steal(),
1225            I2C1: I2C1::steal(),
1226            I2C2: I2C2::steal(),
1227            I2C3: I2C3::steal(),
1228            DAC2: DAC2::steal(),
1229            IWDG: IWDG::steal(),
1230            WWDG: WWDG::steal(),
1231            RTC: RTC::steal(),
1232            TIM6: TIM6::steal(),
1233            TIM7: TIM7::steal(),
1234            DAC1: DAC1::steal(),
1235            DBGMCU: DBGMCU::steal(),
1236            TIM1: TIM1::steal(),
1237            TIM20: TIM20::steal(),
1238            TIM8: TIM8::steal(),
1239            ADC1: ADC1::steal(),
1240            ADC2: ADC2::steal(),
1241            ADC3: ADC3::steal(),
1242            ADC4: ADC4::steal(),
1243            ADC1_2: ADC1_2::steal(),
1244            ADC3_4: ADC3_4::steal(),
1245            SYSCFG: SYSCFG::steal(),
1246            OPAMP: OPAMP::steal(),
1247            COMP: COMP::steal(),
1248            FMC: FMC::steal(),
1249        }
1250    }
1251}
stm32f3/stm32f303/mod.rs

stm32f3/stm32f303/
mod.rs
