stm32f3/stm32f303/
adc1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    isr: ISR,
6    ier: IER,
7    cr: CR,
8    cfgr: CFGR,
9    _reserved4: [u8; 0x04],
10    smpr1: SMPR1,
11    smpr2: SMPR2,
12    _reserved6: [u8; 0x04],
13    tr1: TR1,
14    tr2: TR2,
15    tr3: TR3,
16    _reserved9: [u8; 0x04],
17    sqr1: SQR1,
18    sqr2: SQR2,
19    sqr3: SQR3,
20    sqr4: SQR4,
21    dr: DR,
22    _reserved14: [u8; 0x08],
23    jsqr: JSQR,
24    _reserved15: [u8; 0x10],
25    ofr: [OFR; 4],
26    _reserved16: [u8; 0x10],
27    jdr: [JDR; 4],
28    _reserved17: [u8; 0x10],
29    awd2cr: AWD2CR,
30    awd3cr: AWD3CR,
31    _reserved19: [u8; 0x08],
32    difsel: DIFSEL,
33    calfact: CALFACT,
34}
35impl RegisterBlock {
36    ///0x00 - interrupt and status register
37    #[inline(always)]
38    pub const fn isr(&self) -> &ISR {
39        &self.isr
40    }
41    ///0x04 - interrupt enable register
42    #[inline(always)]
43    pub const fn ier(&self) -> &IER {
44        &self.ier
45    }
46    ///0x08 - control register
47    #[inline(always)]
48    pub const fn cr(&self) -> &CR {
49        &self.cr
50    }
51    ///0x0c - configuration register
52    #[inline(always)]
53    pub const fn cfgr(&self) -> &CFGR {
54        &self.cfgr
55    }
56    ///0x14 - sample time register 1
57    #[inline(always)]
58    pub const fn smpr1(&self) -> &SMPR1 {
59        &self.smpr1
60    }
61    ///0x18 - sample time register 2
62    #[inline(always)]
63    pub const fn smpr2(&self) -> &SMPR2 {
64        &self.smpr2
65    }
66    ///0x20 - watchdog threshold register 1
67    #[inline(always)]
68    pub const fn tr1(&self) -> &TR1 {
69        &self.tr1
70    }
71    ///0x24 - watchdog threshold register
72    #[inline(always)]
73    pub const fn tr2(&self) -> &TR2 {
74        &self.tr2
75    }
76    ///0x28 - watchdog threshold register 3
77    #[inline(always)]
78    pub const fn tr3(&self) -> &TR3 {
79        &self.tr3
80    }
81    ///0x30 - regular sequence register 1
82    #[inline(always)]
83    pub const fn sqr1(&self) -> &SQR1 {
84        &self.sqr1
85    }
86    ///0x34 - regular sequence register 2
87    #[inline(always)]
88    pub const fn sqr2(&self) -> &SQR2 {
89        &self.sqr2
90    }
91    ///0x38 - regular sequence register 3
92    #[inline(always)]
93    pub const fn sqr3(&self) -> &SQR3 {
94        &self.sqr3
95    }
96    ///0x3c - regular sequence register 4
97    #[inline(always)]
98    pub const fn sqr4(&self) -> &SQR4 {
99        &self.sqr4
100    }
101    ///0x40 - regular Data Register
102    #[inline(always)]
103    pub const fn dr(&self) -> &DR {
104        &self.dr
105    }
106    ///0x4c - injected sequence register
107    #[inline(always)]
108    pub const fn jsqr(&self) -> &JSQR {
109        &self.jsqr
110    }
111    ///0x60..0x70 - offset register %s
112    ///
113    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `OFR1` register.</div>
114    #[inline(always)]
115    pub const fn ofr(&self, n: usize) -> &OFR {
116        &self.ofr[n]
117    }
118    ///Iterator for array of:
119    ///0x60..0x70 - offset register %s
120    #[inline(always)]
121    pub fn ofr_iter(&self) -> impl Iterator<Item = &OFR> {
122        self.ofr.iter()
123    }
124    ///0x60 - offset register 1
125    #[inline(always)]
126    pub const fn ofr1(&self) -> &OFR {
127        self.ofr(0)
128    }
129    ///0x64 - offset register 2
130    #[inline(always)]
131    pub const fn ofr2(&self) -> &OFR {
132        self.ofr(1)
133    }
134    ///0x68 - offset register 3
135    #[inline(always)]
136    pub const fn ofr3(&self) -> &OFR {
137        self.ofr(2)
138    }
139    ///0x6c - offset register 4
140    #[inline(always)]
141    pub const fn ofr4(&self) -> &OFR {
142        self.ofr(3)
143    }
144    ///0x80..0x90 - injected data register %s
145    ///
146    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `JDR1` register.</div>
147    #[inline(always)]
148    pub const fn jdr(&self, n: usize) -> &JDR {
149        &self.jdr[n]
150    }
151    ///Iterator for array of:
152    ///0x80..0x90 - injected data register %s
153    #[inline(always)]
154    pub fn jdr_iter(&self) -> impl Iterator<Item = &JDR> {
155        self.jdr.iter()
156    }
157    ///0x80 - injected data register 1
158    #[inline(always)]
159    pub const fn jdr1(&self) -> &JDR {
160        self.jdr(0)
161    }
162    ///0x84 - injected data register 2
163    #[inline(always)]
164    pub const fn jdr2(&self) -> &JDR {
165        self.jdr(1)
166    }
167    ///0x88 - injected data register 3
168    #[inline(always)]
169    pub const fn jdr3(&self) -> &JDR {
170        self.jdr(2)
171    }
172    ///0x8c - injected data register 4
173    #[inline(always)]
174    pub const fn jdr4(&self) -> &JDR {
175        self.jdr(3)
176    }
177    ///0xa0 - Analog Watchdog 2 Configuration Register
178    #[inline(always)]
179    pub const fn awd2cr(&self) -> &AWD2CR {
180        &self.awd2cr
181    }
182    ///0xa4 - Analog Watchdog 3 Configuration Register
183    #[inline(always)]
184    pub const fn awd3cr(&self) -> &AWD3CR {
185        &self.awd3cr
186    }
187    ///0xb0 - Differential Mode Selection Register 2
188    #[inline(always)]
189    pub const fn difsel(&self) -> &DIFSEL {
190        &self.difsel
191    }
192    ///0xb4 - Calibration Factors
193    #[inline(always)]
194    pub const fn calfact(&self) -> &CALFACT {
195        &self.calfact
196    }
197}
198/**ISR (rw) register accessor: interrupt and status register
199
200You can [`read`](crate::Reg::read) this register and get [`isr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`isr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:ISR)
203
204For information about available fields see [`mod@isr`] module*/
205pub type ISR = crate::Reg<isr::ISRrs>;
206///interrupt and status register
207pub mod isr;
208/**IER (rw) register accessor: interrupt enable register
209
210You can [`read`](crate::Reg::read) this register and get [`ier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:IER)
213
214For information about available fields see [`mod@ier`] module*/
215pub type IER = crate::Reg<ier::IERrs>;
216///interrupt enable register
217pub mod ier;
218/**CR (rw) register accessor: control register
219
220You can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
221
222See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:CR)
223
224For information about available fields see [`mod@cr`] module*/
225pub type CR = crate::Reg<cr::CRrs>;
226///control register
227pub mod cr;
228/**CFGR (rw) register accessor: configuration register
229
230You can [`read`](crate::Reg::read) this register and get [`cfgr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
231
232See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:CFGR)
233
234For information about available fields see [`mod@cfgr`] module*/
235pub type CFGR = crate::Reg<cfgr::CFGRrs>;
236///configuration register
237pub mod cfgr;
238/**SMPR1 (rw) register accessor: sample time register 1
239
240You can [`read`](crate::Reg::read) this register and get [`smpr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
241
242See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SMPR1)
243
244For information about available fields see [`mod@smpr1`] module*/
245pub type SMPR1 = crate::Reg<smpr1::SMPR1rs>;
246///sample time register 1
247pub mod smpr1;
248/**SMPR2 (rw) register accessor: sample time register 2
249
250You can [`read`](crate::Reg::read) this register and get [`smpr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smpr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
251
252See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SMPR2)
253
254For information about available fields see [`mod@smpr2`] module*/
255pub type SMPR2 = crate::Reg<smpr2::SMPR2rs>;
256///sample time register 2
257pub mod smpr2;
258/**TR1 (rw) register accessor: watchdog threshold register 1
259
260You can [`read`](crate::Reg::read) this register and get [`tr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
261
262See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:TR1)
263
264For information about available fields see [`mod@tr1`] module*/
265pub type TR1 = crate::Reg<tr1::TR1rs>;
266///watchdog threshold register 1
267pub mod tr1;
268/**TR2 (rw) register accessor: watchdog threshold register
269
270You can [`read`](crate::Reg::read) this register and get [`tr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
271
272See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:TR2)
273
274For information about available fields see [`mod@tr2`] module*/
275pub type TR2 = crate::Reg<tr2::TR2rs>;
276///watchdog threshold register
277pub mod tr2;
278/**TR3 (rw) register accessor: watchdog threshold register 3
279
280You can [`read`](crate::Reg::read) this register and get [`tr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
281
282See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:TR3)
283
284For information about available fields see [`mod@tr3`] module*/
285pub type TR3 = crate::Reg<tr3::TR3rs>;
286///watchdog threshold register 3
287pub mod tr3;
288/**SQR1 (rw) register accessor: regular sequence register 1
289
290You can [`read`](crate::Reg::read) this register and get [`sqr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
291
292See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SQR1)
293
294For information about available fields see [`mod@sqr1`] module*/
295pub type SQR1 = crate::Reg<sqr1::SQR1rs>;
296///regular sequence register 1
297pub mod sqr1;
298/**SQR2 (rw) register accessor: regular sequence register 2
299
300You can [`read`](crate::Reg::read) this register and get [`sqr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
301
302See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SQR2)
303
304For information about available fields see [`mod@sqr2`] module*/
305pub type SQR2 = crate::Reg<sqr2::SQR2rs>;
306///regular sequence register 2
307pub mod sqr2;
308/**SQR3 (rw) register accessor: regular sequence register 3
309
310You can [`read`](crate::Reg::read) this register and get [`sqr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
311
312See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SQR3)
313
314For information about available fields see [`mod@sqr3`] module*/
315pub type SQR3 = crate::Reg<sqr3::SQR3rs>;
316///regular sequence register 3
317pub mod sqr3;
318/**SQR4 (rw) register accessor: regular sequence register 4
319
320You can [`read`](crate::Reg::read) this register and get [`sqr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
321
322See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:SQR4)
323
324For information about available fields see [`mod@sqr4`] module*/
325pub type SQR4 = crate::Reg<sqr4::SQR4rs>;
326///regular sequence register 4
327pub mod sqr4;
328/**DR (r) register accessor: regular Data Register
329
330You can [`read`](crate::Reg::read) this register and get [`dr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
331
332See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:DR)
333
334For information about available fields see [`mod@dr`] module*/
335pub type DR = crate::Reg<dr::DRrs>;
336///regular Data Register
337pub mod dr;
338/**JSQR (rw) register accessor: injected sequence register
339
340You can [`read`](crate::Reg::read) this register and get [`jsqr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`jsqr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
341
342See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:JSQR)
343
344For information about available fields see [`mod@jsqr`] module*/
345pub type JSQR = crate::Reg<jsqr::JSQRrs>;
346///injected sequence register
347pub mod jsqr;
348/**OFR (rw) register accessor: offset register %s
349
350You can [`read`](crate::Reg::read) this register and get [`ofr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ofr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
351
352See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:OFR[1])
353
354For information about available fields see [`mod@ofr`] module*/
355pub type OFR = crate::Reg<ofr::OFRrs>;
356///offset register %s
357pub mod ofr;
358/**JDR (r) register accessor: injected data register %s
359
360You can [`read`](crate::Reg::read) this register and get [`jdr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
361
362See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:JDR[1])
363
364For information about available fields see [`mod@jdr`] module*/
365pub type JDR = crate::Reg<jdr::JDRrs>;
366///injected data register %s
367pub mod jdr;
368/**AWD2CR (rw) register accessor: Analog Watchdog 2 Configuration Register
369
370You can [`read`](crate::Reg::read) this register and get [`awd2cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd2cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
371
372See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:AWD2CR)
373
374For information about available fields see [`mod@awd2cr`] module*/
375pub type AWD2CR = crate::Reg<awd2cr::AWD2CRrs>;
376///Analog Watchdog 2 Configuration Register
377pub mod awd2cr;
378/**AWD3CR (rw) register accessor: Analog Watchdog 3 Configuration Register
379
380You can [`read`](crate::Reg::read) this register and get [`awd3cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`awd3cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
381
382See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:AWD3CR)
383
384For information about available fields see [`mod@awd3cr`] module*/
385pub type AWD3CR = crate::Reg<awd3cr::AWD3CRrs>;
386///Analog Watchdog 3 Configuration Register
387pub mod awd3cr;
388/**DIFSEL (rw) register accessor: Differential Mode Selection Register 2
389
390You can [`read`](crate::Reg::read) this register and get [`difsel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`difsel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
391
392See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:DIFSEL)
393
394For information about available fields see [`mod@difsel`] module*/
395pub type DIFSEL = crate::Reg<difsel::DIFSELrs>;
396///Differential Mode Selection Register 2
397pub mod difsel;
398/**CALFACT (rw) register accessor: Calibration Factors
399
400You can [`read`](crate::Reg::read) this register and get [`calfact::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`calfact::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
401
402See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F303.html#ADC1:CALFACT)
403
404For information about available fields see [`mod@calfact`] module*/
405pub type CALFACT = crate::Reg<calfact::CALFACTrs>;
406///Calibration Factors
407pub mod calfact;
stm32f3/stm32f303/adc1.rs

stm32f3/stm32f303/
adc1.rs
