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#[doc = r"Register block"] #[repr(C)] pub struct RegisterBlock { #[doc = "0x00 - DMA interrupt status register (DMA_ISR)"] pub isr: ISR, #[doc = "0x04 - DMA interrupt flag clear register (DMA_IFCR)"] pub ifcr: IFCR, #[doc = "0x08 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch1: CH, _reserved3: [u8; 4usize], #[doc = "0x1c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch2: CH, _reserved4: [u8; 4usize], #[doc = "0x30 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch3: CH, _reserved5: [u8; 4usize], #[doc = "0x44 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch4: CH, _reserved6: [u8; 4usize], #[doc = "0x58 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch5: CH, _reserved7: [u8; 4usize], #[doc = "0x6c - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch6: CH, _reserved8: [u8; 4usize], #[doc = "0x80 - Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub ch7: CH, } #[doc = r"Register block"] #[repr(C)] pub struct CH { #[doc = "0x00 - DMA channel configuration register (DMA_CCR)"] pub cr: self::ch::CR, #[doc = "0x04 - DMA channel 1 number of data register"] pub ndtr: self::ch::NDTR, #[doc = "0x08 - DMA channel 1 peripheral address register"] pub par: self::ch::PAR, #[doc = "0x0c - DMA channel 1 memory address register"] pub mar: self::ch::MAR, } #[doc = r"Register block"] #[doc = "Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers"] pub mod ch; #[doc = "DMA interrupt status register (DMA_ISR)\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [isr](isr) module"] pub type ISR = crate::Reg<u32, _ISR>; #[allow(missing_docs)] #[doc(hidden)] pub struct _ISR; #[doc = "`read()` method returns [isr::R](isr::R) reader structure"] impl crate::Readable for ISR {} #[doc = "DMA interrupt status register (DMA_ISR)"] pub mod isr; #[doc = "DMA interrupt flag clear register (DMA_IFCR)\n\nThis register you can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about avaliable fields see [ifcr](ifcr) module"] pub type IFCR = crate::Reg<u32, _IFCR>; #[allow(missing_docs)] #[doc(hidden)] pub struct _IFCR; #[doc = "`write(|w| ..)` method takes [ifcr::W](ifcr::W) writer structure"] impl crate::Writable for IFCR {} #[doc = "DMA interrupt flag clear register (DMA_IFCR)"] pub mod ifcr;