Struct stm32f3::stm32f3x8::fpu::fpscr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn ioc(&self) -> IOCR

Bit 0 - Invalid operation cumulative exception bit

pub fn dzc(&self) -> DZCR

Bit 1 - Division by zero cumulative exception bit.

pub fn ofc(&self) -> OFCR

Bit 2 - Overflow cumulative exception bit

pub fn ufc(&self) -> UFCR

Bit 3 - Underflow cumulative exception bit

pub fn ixc(&self) -> IXCR

Bit 4 - Inexact cumulative exception bit

pub fn idc(&self) -> IDCR

Bit 7 - Input denormal cumulative exception bit.

pub fn rmode(&self) -> RMODER

Bits 22:23 - Rounding Mode control field

pub fn fz(&self) -> FZR

Bit 24 - Flush-to-zero mode control bit:

pub fn dn(&self) -> DNR

Bit 25 - Default NaN mode control bit

pub fn ahp(&self) -> AHPR

Bit 26 - Alternative half-precision control bit

pub fn v(&self) -> VR

Bit 28 - Overflow condition code flag

pub fn c(&self) -> CR

Bit 29 - Carry condition code flag

pub fn z(&self) -> ZR

Bit 30 - Zero condition code flag

pub fn n(&self) -> NR

Bit 31 - Negative condition code flag