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#[doc = r"Value read from the register"] pub struct R { bits: u32, } #[doc = r"Value to write to the register"] pub struct W { bits: u32, } impl super::OR { #[doc = r"Modifies the contents of the register"] #[inline(always)] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); self.register.set(f(&R { bits }, &mut W { bits }).bits); } #[doc = r"Reads the contents of the register"] #[inline(always)] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r"Writes to the register"] #[inline(always)] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { self.register.set( f(&mut W { bits: Self::reset_value(), }) .bits, ); } #[doc = r"Reset value of the register"] #[inline(always)] pub const fn reset_value() -> u32 { 0 } #[doc = r"Writes the reset value to the register"] #[inline(always)] pub fn reset(&self) { self.register.set(Self::reset_value()) } } #[doc = r"Value of the field"] pub struct TIM1_ETR_ADC1_RMPR { bits: u8, } impl TIM1_ETR_ADC1_RMPR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _TIM1_ETR_ADC1_RMPW<'a> { w: &'a mut W, } impl<'a> _TIM1_ETR_ADC1_RMPW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x03 << 0); self.w.bits |= ((value as u32) & 0x03) << 0; self.w } } #[doc = r"Value of the field"] pub struct TIM1_ETR_ADC4_RMPR { bits: u8, } impl TIM1_ETR_ADC4_RMPR { #[doc = r"Value of the field as raw bits"] #[inline(always)] pub fn bits(&self) -> u8 { self.bits } } #[doc = r"Proxy"] pub struct _TIM1_ETR_ADC4_RMPW<'a> { w: &'a mut W, } impl<'a> _TIM1_ETR_ADC4_RMPW<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits &= !(0x03 << 2); self.w.bits |= ((value as u32) & 0x03) << 2; self.w } } impl R { #[doc = r"Value of the register as raw bits"] #[inline(always)] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:1 - TIM1_ETR_ADC1 remapping capability"] #[inline(always)] pub fn tim1_etr_adc1_rmp(&self) -> TIM1_ETR_ADC1_RMPR { let bits = ((self.bits >> 0) & 0x03) as u8; TIM1_ETR_ADC1_RMPR { bits } } #[doc = "Bits 2:3 - TIM1_ETR_ADC4 remapping capability"] #[inline(always)] pub fn tim1_etr_adc4_rmp(&self) -> TIM1_ETR_ADC4_RMPR { let bits = ((self.bits >> 2) & 0x03) as u8; TIM1_ETR_ADC4_RMPR { bits } } } impl W { #[doc = r"Writes raw bits to the register"] #[inline(always)] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:1 - TIM1_ETR_ADC1 remapping capability"] #[inline(always)] pub fn tim1_etr_adc1_rmp(&mut self) -> _TIM1_ETR_ADC1_RMPW { _TIM1_ETR_ADC1_RMPW { w: self } } #[doc = "Bits 2:3 - TIM1_ETR_ADC4 remapping capability"] #[inline(always)] pub fn tim1_etr_adc4_rmp(&mut self) -> _TIM1_ETR_ADC4_RMPW { _TIM1_ETR_ADC4_RMPW { w: self } } }